133 lines
3.3 KiB
Plaintext
133 lines
3.3 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: R-CarD1 SFMA (Serial Flash Memory Interface A) program script
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; @Description:
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;
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; SRAM: 0xE63A0000
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; SFMA(controller) Base: 0xFEC08000
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;
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; @Author: jjeong
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; @Chip:
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; @Keywords: Flash SPI RCARD1
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: rcard1-spi.cmm 11733 2023-01-16 08:55:12Z bschroefel $
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LOCAL &arg1
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ENTRY &arg1
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&arg1=STRing.UPpeR("&arg1") // for example "PREPAREONLY"
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&SPIBASE=0xFEC08000
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&RAMBASE=0xE63A0000
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SYStem.RESet
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SYStem.CPU R7S721063
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CORE.ASSIGN 1
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SYStem.Up
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//////////////////////
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// enable SRAM
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//////////////////////
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//Data.Set <address> %L <data>
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Data.Test &RAMBASE++0x3FFF /Prime ;s(d)ram test
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IF FOUND()
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(
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PRINT "s(d)ram is NOT initialized around 0x" ADDRESS.OFFSET(TRACK.ADDRESS())
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ENDDO
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)
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///////////////////
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// enable SFMA (clk & pin mux)
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//////////////////
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//Data.Set <address> %L <data>
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//Data.Set 0xE6150A14 %L (0x2<<6.) ; slower clk by divide the SFMA Clock source
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&pfc_base=0xE6060000
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&GPSR2=&pfc_base+0x000C ; PFC_BASE+0x4+n*4
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&IPSR4=&pfc_base+0x0030 ; PFC_BASE+0x20+m*4
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//Pin mux for SFMA0CLK,SFMA0SSL,SFMA0O00,SFMA0O10
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//GOSUB WRITE_OR &IPSR4 0x0 ; IP4[18:15]
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//GOSUB WRITE_OR &GPSR2 0x0003C000 ; GP2_[17:14]
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AREA.CLEAR
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AREA.view
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GOSUB READ_ID_TEST
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Break.RESet
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FLASHFILE.RESet
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//FLASHFILE.CONFIG <SPI Base AddRESs> ,, ,,
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FLASHFILE.CONFIG &SPIBASE
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// FLASHFILE.TARGET <code range> <data range> <Algorithm file>
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FLASHFILE.TARGET &RAMBASE++0x1FFF E:(&RAMBASE+0x2000)++0x21FF ~~/demo/arm/flash/byte/spi64_shmiobc.bin /STACKSIZE 0x400 /DualPort
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FLASHFILE.GETID
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//End of the test prepareonly
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IF "&arg1"=="PREPAREONLY"
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ENDDO
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//Read SPI FLASH
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FLASHFILE.DUMP 0x0
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//Erase SPI FLASH
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; FLASHFILE.ERASE 0x0--0xFFFFF
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//Write SPI FLASH
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; FLASHFILE.LOAD * 0x0
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ENDDO
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; --------------------------------------------------------------------------------
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READ_ID_TEST:
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(
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&SMCR=(&SPIBASE+0x20) ; SMCR_0 , SPI mode control
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&SMCMR=(&SPIBASE+0x24) ; SMCMR_0 , SPI mode command setting register
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&SMADR=(&SPIBASE+0x28) ;address
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&SMOPR=(&SPIBASE+0x2C) ;option data setting
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&SMENR=(&SPIBASE+0x30) ;enable setting
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&SMRDR=(&SPIBASE+0x38) ;data
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&SMRDR1=(&SPIBASE+0x3C) ;data
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&SMWDR=(&SPIBASE+0x40) ;data
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&SMWDR1=(&SPIBASE+0x44) ;data
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&SMDMCR=(&SPIBASE+0x60) ;dummy cycle
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Data.Set A:&SMCMR %Long (0x9f<<16.) ;read-id cmd
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Data.Set A:&SMADR %Long 0x0 ;address 0x0
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Data.Set A:&SMOPR %Long 0x0 ;address 0x0
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;Data.Set A:&SMDMCR %l 0x7 ; dummy 8 cycle number
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&smenr=(0x1<<14.)|0xF; cmd enable, 4byte data read
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Data.Set A:&SMENR %Long &smenr
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//start spi transfer
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&smcr=0x1|(0x2<<1.) ; spie and spire , SPI Read data
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Data.Set A:&SMWDR %LE %Long 0x00000000 ; write Tx buffer init
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Data.Set A:&SMCR %Long &smcr
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&read_data=Data.Long(A:&SMRDR)
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PRINT "Read 1st: 0x" (&read_data)&0xFF " (Manufacturer) "
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PRINT "Read 2nd: 0x" (&read_data>>8.)&0xFF " (Device) "
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PRINT "Read 3rd: 0x" (&read_data>>16.)&0xFF
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PRINT "Read 4th: 0x" (&read_data>>24.)&0xFF
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RETURN
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)
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WRITE_OR:
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ENTRY &addr &data
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&data=((&data)|(Data.Long(A:&addr)))
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¬_data=~(&data)
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Data.Set &pfc_base %Long ¬_data
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Data.Set &addr %Long &data
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RETURN
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