; --------------------------------------------------------------------------------
; @Title: R-CarD1 SFMA (Serial Flash Memory Interface A) program script
; @Description:
;
; SRAM: 0xE63A0000
; SFMA(controller) Base: 0xFEC08000
;
; @Author: jjeong
; @Chip:
; @Keywords: Flash SPI RCARD1
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: rcard1-spi.cmm 11733 2023-01-16 08:55:12Z bschroefel $

LOCAL &arg1
ENTRY &arg1
&arg1=STRing.UPpeR("&arg1")  // for example "PREPAREONLY"

&SPIBASE=0xFEC08000
&RAMBASE=0xE63A0000

SYStem.RESet
SYStem.CPU R7S721063
CORE.ASSIGN 1
SYStem.Up

//////////////////////
// enable SRAM
//////////////////////
//Data.Set <address> %L <data>
Data.Test &RAMBASE++0x3FFF  /Prime ;s(d)ram test
IF FOUND()
( 
PRINT "s(d)ram is NOT initialized around 0x" ADDRESS.OFFSET(TRACK.ADDRESS())
ENDDO
)

///////////////////
// enable SFMA (clk & pin mux)
//////////////////
//Data.Set <address> %L <data>
//Data.Set 0xE6150A14 %L (0x2<<6.)  ; slower clk by divide the SFMA Clock source

&pfc_base=0xE6060000
&GPSR2=&pfc_base+0x000C ; PFC_BASE+0x4+n*4
&IPSR4=&pfc_base+0x0030 ; PFC_BASE+0x20+m*4

//Pin mux for SFMA0CLK,SFMA0SSL,SFMA0O00,SFMA0O10
//GOSUB WRITE_OR &IPSR4  0x0         ; IP4[18:15]
//GOSUB WRITE_OR &GPSR2  0x0003C000  ; GP2_[17:14]

AREA.CLEAR
AREA.view
GOSUB READ_ID_TEST

 Break.RESet

 FLASHFILE.RESet

//FLASHFILE.CONFIG <SPI Base AddRESs> ,, ,,
 FLASHFILE.CONFIG &SPIBASE

// FLASHFILE.TARGET <code range> <data range> <Algorithm file>
 FLASHFILE.TARGET &RAMBASE++0x1FFF E:(&RAMBASE+0x2000)++0x21FF   ~~/demo/arm/flash/byte/spi64_shmiobc.bin   /STACKSIZE 0x400 /DualPort

 FLASHFILE.GETID

//End of the test prepareonly
IF "&arg1"=="PREPAREONLY"
ENDDO

//Read SPI FLASH
  FLASHFILE.DUMP 0x0

//Erase SPI FLASH
; FLASHFILE.ERASE 0x0--0xFFFFF

//Write SPI FLASH
; FLASHFILE.LOAD  * 0x0

ENDDO

; --------------------------------------------------------------------------------

READ_ID_TEST:
(
  &SMCR=(&SPIBASE+0x20)   ; SMCR_0  , SPI mode control
  &SMCMR=(&SPIBASE+0x24)   ; SMCMR_0  , SPI mode command setting register
  &SMADR=(&SPIBASE+0x28)    ;address
  &SMOPR=(&SPIBASE+0x2C)   ;option data setting
  &SMENR=(&SPIBASE+0x30)    ;enable setting
  &SMRDR=(&SPIBASE+0x38)    ;data
  &SMRDR1=(&SPIBASE+0x3C)    ;data
  &SMWDR=(&SPIBASE+0x40)    ;data
  &SMWDR1=(&SPIBASE+0x44)    ;data
  &SMDMCR=(&SPIBASE+0x60)    ;dummy cycle

  Data.Set A:&SMCMR %Long (0x9f<<16.)   ;read-id cmd
  Data.Set A:&SMADR %Long 0x0    ;address 0x0
  Data.Set A:&SMOPR %Long 0x0    ;address 0x0
  ;Data.Set A:&SMDMCR %l 0x7    ; dummy 8 cycle number

  &smenr=(0x1<<14.)|0xF;  cmd enable, 4byte data read

  Data.Set A:&SMENR %Long &smenr

  //start spi transfer
  &smcr=0x1|(0x2<<1.)  ; spie and spire  , SPI Read data

  Data.Set A:&SMWDR %LE %Long 0x00000000 ; write Tx buffer init

  Data.Set A:&SMCR %Long &smcr

  &read_data=Data.Long(A:&SMRDR)

  PRINT "Read 1st: 0x" (&read_data)&0xFF   " (Manufacturer) "
  PRINT "Read 2nd: 0x" (&read_data>>8.)&0xFF " (Device) "
  PRINT "Read 3rd: 0x" (&read_data>>16.)&0xFF
  PRINT "Read 4th: 0x" (&read_data>>24.)&0xFF

  RETURN
)

WRITE_OR:
ENTRY &addr &data
&data=((&data)|(Data.Long(A:&addr)))
&not_data=~(&data)
Data.Set &pfc_base %Long &not_data
Data.Set &addr %Long &data
RETURN