144 lines
6.8 KiB
Plaintext
144 lines
6.8 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: ARM720T on chip peripherals
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; @Props:
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; @Author: -
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; @Changelog:
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; @Manufacturer:
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; @Doc:
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; @Core:
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; @Chiplist: ARM720T, ARM720TR4
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; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pera720t.per 16305 2023-06-28 11:47:37Z pegold $
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config 16. 8.
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width 8.
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ASSERT VERSION.BUILD.BASE()>=80109.
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sif PER.isNOTIFICATION()
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base AVM:0x00000000
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wgroup AVM:0x00++0
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textline " Peripheral File Notification - "
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button "show missing files" "DIALOG.MESSAGE ""Please check your installation for the possibly missing files:""+CONV.CHAR(0xa)+PER.NOTIFICATION.MISSINGFILES()"
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textline " ---------------------------------------------------------------"
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textline " The peripheral file for this SoC cannot be displayed. "
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textline " Possible reasons are: "
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textline " - it is missing in the local installation or under development "
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textline " - it is confidential "
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textline " "
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textline " As fallback only the core registers are shown. "
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textline " Please check www.lauterbach.com/scripts.html "
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textline " or contact support@lauterbach.com . "
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textline " "
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endif
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;begin include file arm/mmu720.ph
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;parameters:
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group c15:0x0--0x0 "CP15"
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line.long 0x0 "ID,ID Register"
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group c15:0x1--0x1
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 0x9 " R ,ROM Protection" "off,on"
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bitfld.long 0x0 0x8 " S ,System Protection" "off,on"
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bitfld.long 0x0 0x7 " B ,Endianism" "little,big"
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textline " "
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bitfld.long 0x0 0x3 "W ,Write Buffer" "disable,enable"
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bitfld.long 0x0 0x2 " C ,Cache" "disable,enable"
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bitfld.long 0x0 0x1 " A ,Alignment Fault" "disable,enable"
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bitfld.long 0x0 0x0 " M ,MMU" "disable,enable"
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group c15:0x2--0x2
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line.long 0x0 "TTB,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 "TTBA ,Translation Table Base Address"
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group c15:0x3--0x3
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line.long 0x0 "DAC,Domain Access Control Register"
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bitfld.long 0x0 30.--31. "D15 ,Domain Access 15" "no access,client,reserved,manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "no access,client,reserved,manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "no access,client,reserved,manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 22.--23. "D11 ,Domain Access 11" "no access,client,reserved,manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "no access,client,reserved,manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "no access,client,reserved,manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 14.--15. "D7 ,Domain Access 7" "no access,client,reserved,manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "no access,client,reserved,manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "no access,client,reserved,manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "no access,client,reserved,manager"
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textline " "
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bitfld.long 0x0 6.--7. "D3 ,Domain Access 3" "no access,client,reserved,manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "no access,client,reserved,manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "no access,client,reserved,manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "no access,client,reserved,manager"
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group c15:0x5--0x5
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line.long 0x0 "FS,Fault Status Register"
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bitfld.long 0x0 0x4--0x7 "DOM ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STA ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x6--0x6
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line.long 0x0 "FA,Fault Address Registerr"
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group c15:0x7--0x7
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line.long 0x0 "CACHEOP,Cache Operations Register"
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group c15:0x8--0x8
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line.long 0x0 "TLBOP,TLB Operations Register"
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group c15:0x0d--0x0d
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line.long 0x0 "PID,Process Identifier"
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;end include file arm/mmu720.ph
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;begin include file arm/icebreaker.ph
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;parameters:
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tree "ICEBreaker"
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group ice:0x8--0x8 "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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group ice:0x9--0x9
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line.long 0x0 "AM,Address Mask"
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group ice:0x0a--0x0a
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line.long 0x0 "DV,Data Value"
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group ice:0x0b--0x0b
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line.long 0x0 "DM,Data Mask"
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group ice:0x0c--0x0c
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line.long 0x0 "CV,Control Value"
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bitfld.long 0x0 0x8 "ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x0 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x0 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x0 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x0 0x4 " nTRANS ,CPU Mode" "User,notU"
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bitfld.long 0x0 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x0 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x0 0x0 " nRW ,Read/Write" "R ,W"
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group ice:0x0d--0x0d
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line.long 0x0 "CM,Control Mask"
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bitfld.long 0x0 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x0 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x0 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x0 0x4 " nTRANS ,CPU Mode" "ENA ,DIS"
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bitfld.long 0x0 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x0 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x0 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x10 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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group ice:0x11--0x11
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line.long 0x0 "AM,Address Mask"
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group ice:0x12--0x12
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line.long 0x0 "DV,Data Value"
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group ice:0x13--0x13
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line.long 0x0 "DM,Data Mask"
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group ice:0x14--0x14
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line.long 0x0 "CV,Control Value"
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bitfld.long 0x0 0x8 "ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x0 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x0 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x0 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x0 0x4 " nTRANS ,CPU Mode" "User,notU"
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bitfld.long 0x0 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x0 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x0 0x0 " nRW ,Read/Write" "R ,W"
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group ice:0x15--0x15
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line.long 0x0 "CM,Control Mask"
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bitfld.long 0x0 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x0 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x0 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x0 0x4 " nTRANS ,CPU Mode" "ENA ,DIS"
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bitfld.long 0x0 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x0 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x0 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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;end include file arm/icebreaker.ph
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