424 lines
18 KiB
Plaintext
424 lines
18 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: TMS570LS0xx Specific Menu
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; @Props: Released
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; @Author: MKR, BCA, MRO
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; @Changelog: 2013-03-13 MKR
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; 2019-03-29 MRO
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; @Manufacturer: TI - Texas Instruments
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; @Core: Cortex-R4, Cortex-R4F
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; @Chip: TMS570LS0232, TMS570LS0714-PGE, TMS570LS0714-PZ, TMS570LS0914-PGE
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; TMS570LS0914-PZ
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mentms570ls0xx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXR4F")
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(
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popup "[:chip]Core Registers (Cortex-R4F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4F),Watchpoint Control Registers"""
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)
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)
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else if (CORENAME()=="CORTEXR4")
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(
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popup "[:chip]Core Registers (Cortex-R4)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4),Watchpoint Control Registers"""
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)
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)
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separator
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popup "SYS;System and Peripheral Control Registers"
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(
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menuitem "SYS1;Primary System Registers" "per , ""SYS (System and Peripheral Control Registers),SYS1 (Primary System Registers)"""
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menuitem "SYS2;Secondary System Registers" "per , ""SYS (System and Peripheral Control Registers),SYS2 (Secondary System Registers)"""
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menuitem "PCR;Peripheral Central Resource" "per , ""SYS (System and Peripheral Control Registers),PCR (Peripheral Central Resource)"""
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)
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if cpuis("TMS570LS09*")||cpuis("TMS570LS07*")
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(
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menuitem "PMM;Power Management Module" "per , ""PMM (Power Management Module)"""
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)
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menuitem "IOMM;I/O Multiplexing and Control Module" "per , ""IOMM (I/O Multiplexing and Control Module)"""
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menuitem "F021;Flash Module Controller" "per , ""F021 (Flash Module Controller)"""
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popup "TCRAM;Tightly-Coupled RAM"
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(
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menuitem "RAM ECC Even" "per , ""TCRAM (Tightly-Coupled RAM),RAM ECC Even"""
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menuitem "RAM ECC Odd" "per , ""TCRAM (Tightly-Coupled RAM),RAM ECC Odd"""
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)
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menuitem "PBIST;Programmable Built-In Self-Test" "per , ""PBIST (Programmable Built-In Self-Test)"""
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menuitem "STC;Self-Test Controller" "per , ""STC (Self-Test Controller)"""
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menuitem "CCM-R4;CPU Compare Module for Cortex-R4" "per , ""CCM-R4 (CPU Compare Module for Cortex-R4)"""
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menuitem "PLL;Phase-Locked Loop" "per , ""PLL (Phase-Locked Loop)"""
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menuitem "LPOCLKDET;Low-Power Oscillator and Clock Detect" "per , ""LPOCLKDET (Low-Power Oscillator and Clock Detect)"""
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menuitem "DCC;Dual-Clock Comparator" "per , ""DCC (Dual-Clock Comparator)"""
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menuitem "ESM;Error Signaling Module" "per , ""ESM (Error Signaling Module)"""
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menuitem "RTI;Real-Time Interrupt" "per , ""RTI (Real-Time Interrupt)"""
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menuitem "CRC;Cyclic Redundancy Check Controller Module" "per , ""CRC (Cyclic Redundancy Check Controller Module)"""
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menuitem "VIM;Vectored Interrupt Manager Module" "per , ""VIM (Vectored Interrupt Manager Module)"""
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if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
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(
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menuitem "DMA;Direct Memory Access" "per , ""DMA (Direct Memory Access)"""
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popup "EPWM;Enhanced Pulse Width Modulator Module"
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(
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menuitem "EPWM1" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM1"""
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menuitem "EPWM2" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM2"""
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menuitem "EPWM3" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM3"""
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menuitem "EPWM4" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM4"""
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menuitem "EPWM5" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM5"""
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menuitem "EPWM6" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM6"""
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menuitem "EPWM7" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM7"""
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)
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popup "ECAP;Enhanced Capture Module"
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(
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menuitem "ECAP1" "per , ""ECAP (Enhanced Capture Module),ECAP1"""
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menuitem "ECAP2" "per , ""ECAP (Enhanced Capture Module),ECAP2"""
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menuitem "ECAP3" "per , ""ECAP (Enhanced Capture Module),ECAP3"""
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menuitem "ECAP4" "per , ""ECAP (Enhanced Capture Module),ECAP4"""
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menuitem "ECAP5" "per , ""ECAP (Enhanced Capture Module),ECAP5"""
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menuitem "ECAP6" "per , ""ECAP (Enhanced Capture Module),ECAP6"""
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)
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)
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menuitem "eQEP;Enhanced QEP Module" "per , ""eQEP (Enhanced QEP Module)"""
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menuitem "ADC;Analog To Digital Converter Module" "per , ""ADC (Analog To Digital Converter Module)"""
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if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
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(
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popup "N2HET;High-End Timer Module"
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(
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menuitem "N2HET1" "per , ""N2HET (High-End Timer Module),N2HET1"""
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menuitem "N2HET2" "per , ""N2HET (High-End Timer Module),N2HET2"""
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)
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)
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else
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(
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menuitem "N2HET;High-End Timer Module" "per , ""N2HET (High-End Timer Module)"""
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)
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popup "HTU;High-End Timer Transfer Unit Module"
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(
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menuitem "HTU1" "per , ""HTU (High-End Timer Transfer Unit Module),HTU1"""
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menuitem "HTU2" "per , ""HTU (High-End Timer Transfer Unit Module),HTU2"""
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)
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menuitem "HTU;High-End Timer Transfer Unit Module" "per , ""HTU (High-End Timer Transfer Unit Module)"""
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popup "GIO;General Purpose Input/Output Module"
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(
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menuitem "GPIO" "per , ""GIO (General Purpose Input/Output Module),GPIO"""
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menuitem "GPIO_A" "per , ""GIO (General Purpose Input/Output Module),GPIO_A"""
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if !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714-PZ")&&!cpuis("TMS570LS0914-PZ")
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(
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menuitem "GPIO_B" "per , ""GIO (General Purpose Input/Output Module),GPIO_B"""
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)
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)
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popup "DCAN;Controller Area Network Module"
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(
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menuitem "DCAN1" "per , ""DCAN (Controller Area Network Module),DCAN1"""
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menuitem "DCAN2" "per , ""DCAN (Controller Area Network Module),DCAN2"""
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menuitem "DCAN3" "per , ""DCAN (Controller Area Network Module),DCAN3"""
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)
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if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
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(
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popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module"
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(
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menuitem "MibSPI1" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1"""
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menuitem "MibSPI1 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1 RAM"""
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menuitem "SPI2" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI2"""
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menuitem "MibSPI3" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI3"""
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menuitem "MibSPI3 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI3 RAM"""
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menuitem "SPI4" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI4"""
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menuitem "MibSPI5" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI5"""
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menuitem "MibSPI5 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI5 RAM"""
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)
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)
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else if cpuis("TMS570LS0232")
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(
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popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module"
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(
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menuitem "MibSPI1" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1"""
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menuitem "MibSPI1 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1 RAM"""
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menuitem "SPI2" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI2"""
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menuitem "SPI3" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI3"""
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)
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)
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else
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(
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popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module"
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(
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menuitem "MibSPI" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI"""
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menuitem "MibSPI RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI RAM"""
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)
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)
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if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
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(
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popup "SCI/LIN;Serial Communications Interface/Local Interconnect Network Module"
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(
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menuitem "SCI/LIN" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module),SCI/LIN"""
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menuitem "SCI" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module),SCI"""
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)
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)
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else
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(
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menuitem "SCI/LIN;Serial Communications Interface/Local Interconnect Network Module" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)"""
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)
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if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")
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(
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menuitem "I2C;Inter-Integrated Circuit" "per , ""I2C (Inter-Integrated Circuit)"""
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)
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menuitem "eFuse;Enhanced Fuse Controller" "per , ""eFuse (Enhanced Fuse Controller)"""
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)
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)
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