; -------------------------------------------------------------------------------- ; @Title: TMS570LS0xx Specific Menu ; @Props: Released ; @Author: MKR, BCA, MRO ; @Changelog: 2013-03-13 MKR ; 2019-03-29 MRO ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-R4, Cortex-R4F ; @Chip: TMS570LS0232, TMS570LS0714-PGE, TMS570LS0714-PZ, TMS570LS0914-PGE ; TMS570LS0914-PZ ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: mentms570ls0xx.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXR4F") ( popup "[:chip]Core Registers (Cortex-R4F)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4F),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4F),System Control and Configuration""" menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4F),MPU Control and Configuration""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4F),Cache Control and Configuration""" menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4F),TCM Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4F),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4F),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4F),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4F),Watchpoint Control Registers""" ) ) else if (CORENAME()=="CORTEXR4") ( popup "[:chip]Core Registers (Cortex-R4)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4),System Control and Configuration""" menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4),MPU Control and Configuration""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4),Cache Control and Configuration""" menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4),TCM Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4),Watchpoint Control Registers""" ) ) separator popup "SYS;System and Peripheral Control Registers" ( menuitem "SYS1;Primary System Registers" "per , ""SYS (System and Peripheral Control Registers),SYS1 (Primary System Registers)""" menuitem "SYS2;Secondary System Registers" "per , ""SYS (System and Peripheral Control Registers),SYS2 (Secondary System Registers)""" menuitem "PCR;Peripheral Central Resource" "per , ""SYS (System and Peripheral Control Registers),PCR (Peripheral Central Resource)""" ) if cpuis("TMS570LS09*")||cpuis("TMS570LS07*") ( menuitem "PMM;Power Management Module" "per , ""PMM (Power Management Module)""" ) menuitem "IOMM;I/O Multiplexing and Control Module" "per , ""IOMM (I/O Multiplexing and Control Module)""" menuitem "F021;Flash Module Controller" "per , ""F021 (Flash Module Controller)""" popup "TCRAM;Tightly-Coupled RAM" ( menuitem "RAM ECC Even" "per , ""TCRAM (Tightly-Coupled RAM),RAM ECC Even""" menuitem "RAM ECC Odd" "per , ""TCRAM (Tightly-Coupled RAM),RAM ECC Odd""" ) menuitem "PBIST;Programmable Built-In Self-Test" "per , ""PBIST (Programmable Built-In Self-Test)""" menuitem "STC;Self-Test Controller" "per , ""STC (Self-Test Controller)""" menuitem "CCM-R4;CPU Compare Module for Cortex-R4" "per , ""CCM-R4 (CPU Compare Module for Cortex-R4)""" menuitem "PLL;Phase-Locked Loop" "per , ""PLL (Phase-Locked Loop)""" menuitem "LPOCLKDET;Low-Power Oscillator and Clock Detect" "per , ""LPOCLKDET (Low-Power Oscillator and Clock Detect)""" menuitem "DCC;Dual-Clock Comparator" "per , ""DCC (Dual-Clock Comparator)""" menuitem "ESM;Error Signaling Module" "per , ""ESM (Error Signaling Module)""" menuitem "RTI;Real-Time Interrupt" "per , ""RTI (Real-Time Interrupt)""" menuitem "CRC;Cyclic Redundancy Check Controller Module" "per , ""CRC (Cyclic Redundancy Check Controller Module)""" menuitem "VIM;Vectored Interrupt Manager Module" "per , ""VIM (Vectored Interrupt Manager Module)""" if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") ( menuitem "DMA;Direct Memory Access" "per , ""DMA (Direct Memory Access)""" popup "EPWM;Enhanced Pulse Width Modulator Module" ( menuitem "EPWM1" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM1""" menuitem "EPWM2" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM2""" menuitem "EPWM3" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM3""" menuitem "EPWM4" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM4""" menuitem "EPWM5" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM5""" menuitem "EPWM6" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM6""" menuitem "EPWM7" "per , ""EPWM (Enhanced Pulse Width Modulator Module),EPWM7""" ) popup "ECAP;Enhanced Capture Module" ( menuitem "ECAP1" "per , ""ECAP (Enhanced Capture Module),ECAP1""" menuitem "ECAP2" "per , ""ECAP (Enhanced Capture Module),ECAP2""" menuitem "ECAP3" "per , ""ECAP (Enhanced Capture Module),ECAP3""" menuitem "ECAP4" "per , ""ECAP (Enhanced Capture Module),ECAP4""" menuitem "ECAP5" "per , ""ECAP (Enhanced Capture Module),ECAP5""" menuitem "ECAP6" "per , ""ECAP (Enhanced Capture Module),ECAP6""" ) ) menuitem "eQEP;Enhanced QEP Module" "per , ""eQEP (Enhanced QEP Module)""" menuitem "ADC;Analog To Digital Converter Module" "per , ""ADC (Analog To Digital Converter Module)""" if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") ( popup "N2HET;High-End Timer Module" ( menuitem "N2HET1" "per , ""N2HET (High-End Timer Module),N2HET1""" menuitem "N2HET2" "per , ""N2HET (High-End Timer Module),N2HET2""" ) ) else ( menuitem "N2HET;High-End Timer Module" "per , ""N2HET (High-End Timer Module)""" ) popup "HTU;High-End Timer Transfer Unit Module" ( menuitem "HTU1" "per , ""HTU (High-End Timer Transfer Unit Module),HTU1""" menuitem "HTU2" "per , ""HTU (High-End Timer Transfer Unit Module),HTU2""" ) menuitem "HTU;High-End Timer Transfer Unit Module" "per , ""HTU (High-End Timer Transfer Unit Module)""" popup "GIO;General Purpose Input/Output Module" ( menuitem "GPIO" "per , ""GIO (General Purpose Input/Output Module),GPIO""" menuitem "GPIO_A" "per , ""GIO (General Purpose Input/Output Module),GPIO_A""" if !cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714-PZ")&&!cpuis("TMS570LS0914-PZ") ( menuitem "GPIO_B" "per , ""GIO (General Purpose Input/Output Module),GPIO_B""" ) ) popup "DCAN;Controller Area Network Module" ( menuitem "DCAN1" "per , ""DCAN (Controller Area Network Module),DCAN1""" menuitem "DCAN2" "per , ""DCAN (Controller Area Network Module),DCAN2""" menuitem "DCAN3" "per , ""DCAN (Controller Area Network Module),DCAN3""" ) if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") ( popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module" ( menuitem "MibSPI1" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1""" menuitem "MibSPI1 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1 RAM""" menuitem "SPI2" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI2""" menuitem "MibSPI3" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI3""" menuitem "MibSPI3 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI3 RAM""" menuitem "SPI4" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI4""" menuitem "MibSPI5" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI5""" menuitem "MibSPI5 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI5 RAM""" ) ) else if cpuis("TMS570LS0232") ( popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module" ( menuitem "MibSPI1" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1""" menuitem "MibSPI1 RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI1 RAM""" menuitem "SPI2" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI2""" menuitem "SPI3" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),SPI3""" ) ) else ( popup "MibSPI;Multi-Buffered Serial Peripheral Interface Module" ( menuitem "MibSPI" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI""" menuitem "MibSPI RAM" "per , ""MibSPI (Multi-Buffered Serial Peripheral Interface Module),MibSPI RAM""" ) ) if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") ( popup "SCI/LIN;Serial Communications Interface/Local Interconnect Network Module" ( menuitem "SCI/LIN" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module),SCI/LIN""" menuitem "SCI" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module),SCI""" ) ) else ( menuitem "SCI/LIN;Serial Communications Interface/Local Interconnect Network Module" "per , ""SCI/LIN (Serial Communications Interface/Local Interconnect Network Module)""" ) if cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") ( menuitem "I2C;Inter-Integrated Circuit" "per , ""I2C (Inter-Integrated Circuit)""" ) menuitem "eFuse;Enhanced Fuse Controller" "per , ""eFuse (Enhanced Fuse Controller)""" ) )