476 lines
16 KiB
Plaintext
476 lines
16 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: STM32L4 Specific Menu
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; @Props: Released
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; @Author: MKK, MAJ, KOL, WWI, KAW, BCA, DPR, TRJ, ASK
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; @Changelog: 2015-11-03 MAJ
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; 2016-09-08 WWI
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; 2016-11-21 KOL
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; 2017-01-30 KAW
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; 2017-11-07 KOL
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; 2017-11-17 DPR
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; 2017-12-13 ASK
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Chip: STM32L476JG, STM32L476QE, STM32L476QG, STM32L476RC, STM32L476RE,
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; STM32L476RG, STM32L476VC, STM32L476VE, STM32L476VG, STM32L476ZE,
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; STM32L476ZG, STM32L432KC, STM32L433CC, STM32L433RC, STM32L433VC,
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; STM32L442KC, STM32L443CC, STM32L443RC, STM32L443VC, STM32L471QE,
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; STM32L471QG, STM32L471RE, STM32L471RG, STM32L471VE, STM32L471VG,
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; STM32L471ZE, STM32L471ZG, STM32L475RC, STM32L475RE, STM32L475RG,
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; STM32L475VC, STM32L475VE, STM32L475VG, STM32L476JE, STM32L476ME,
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; STM32L476MG, STM32L486JG, STM32L431CB, STM32L431CC, STM32L431KB,
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; STM32L431KC, STM32L431RB, STM32L431RC, STM32L431VC, STM32L432KB,
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; STM32L433CB, STM32L433RB, STM32L4A6RG, STM32L4A6VG, STM32L4A6QG,
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; STM32L4A6ZG, STM32L4A6AG, STM32L496RG, STM32L496RE, STM32L496VG,
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; STM32L496VE, STM32L496QG, STM32L496QE, STM32L496ZG, STM32L496ZE,
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; STM32L496AG, STM32L496AE, STM32L451CC, STM32L451CE, STM32L451RC,
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; STM32L451RE, STM32L451VC, STM32L451VE, STM32L452CC, STM32L452CE,
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; STM32L452RC, STM32L452RE, STM32L452VC, STM32L452VE, STM32L462CE,
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; STM32L462RE, STM32L462VE
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; @Core: Cortex-M4, Cortex-M4F
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menstm32l4.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if STRING.SCAN(CORENAME(),"M4F",0.)>0.
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(
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popup "[:chip]Core Registers (Cortex-M4F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-M4)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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menuitem "FLASH" "per , ""FLASH (Embedded flash memory)"""
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menuitem "FW" "per , ""FW (Firewall)"""
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menuitem "PWR" "per , ""PWR (Power control)"""
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menuitem "RCC" "per , ""RCC (Reset and clock control)"""
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if (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))
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(
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menuitem "CRS" "per , ""CRS (Clock recovery system)"""
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)
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popup "General-purpose I/Os"
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(
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menuitem "GPIO A" "per , ""GPIO (General-purpose I/Os),GPIO A"""
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menuitem "GPIO B" "per , ""GPIO (General-purpose I/Os),GPIO B"""
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menuitem "GPIO C" "per , ""GPIO (General-purpose I/Os),GPIO C"""
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if (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L431R*"))||(cpuis("STM32L433R*"))&&(!cpuis("STM32L443VC"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*"))||(cpuis("STM32L451R*"))||(cpuis("STM32L452R*"))||(cpuis("STM32L462R*"))
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(
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menuitem "GPIO D" "per , ""GPIO (General-purpose I/Os),GPIO D"""
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)
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if (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L4?6V*"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*"))
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(
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menuitem "GPIO E" "per , ""GPIO (General-purpose I/Os),GPIO E"""
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)
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if (cpuis("STM32L471ZE"))||(cpuis("STM32L471ZG"))||(cpuis("STM32L471QG"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))
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(
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menuitem "GPIO F" "per , ""GPIO (General-purpose I/Os),GPIO F"""
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menuitem "GPIO G" "per , ""GPIO (General-purpose I/Os),GPIO G"""
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)
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if (!cpuis("STM32L471VG"))
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(
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menuitem "GPIO H" "per , ""GPIO (General-purpose I/Os),GPIO H"""
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)
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if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))
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(
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menuitem "GPIO I" "per , ""GPIO (General-purpose I/Os),GPIO I"""
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)
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)
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menuitem "SYSCFG" "per , ""SYSCFG (System configuration controller)"""
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popup "DMA"
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(
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menuitem "DMA1" "per , ""DMA (Direct memory access),DMA1"""
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menuitem "DMA2" "per , ""DMA (Direct memory access),DMA2"""
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)
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if (!cpuis("STM32L462*")&&!cpuis("STM32L452*")&&!cpuis("STM32L451*"))
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(
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menuitem "DMA2D" "per , ""DMA2D (Chrom-Art Accelerator controller)"""
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)
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menuitem "EXTI" "per , ""EXTI (Extended interrupts and events controller)"""
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menuitem "CRC" "per , ""CRC (Cyclic redundancy check calculation unit)"""
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if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))
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(
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menuitem "FSMC" "per , ""FSMC (Flexible static memory controller)"""
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)
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menuitem "QUADSPI" "per , ""QUADSPI (Quad serial peripheral interface)"""
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menuitem "ADC" "per , ""ADC (Analog-to-digital converters)"""
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menuitem "DAC" "per , ""DAC (Digital-to-analog converter)"""
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if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))
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(
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menuitem "DCMI" "per , ""DCMI (Digital camera interface)"""
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)
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menuitem "VREF" "per , ""VREF (Voltage reference buffer)"""
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menuitem "COMP" "per , ""COMP (Comparator)"""
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menuitem "OPAMP" "per , ""OPAMP (Operational amplifiers)"""
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if (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L4?6*"))&&(!cpuis("STM32L431*"))
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(
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menuitem "DFSDM" "per , ""DFSDM (Digital filter for sigma delta modulators)"""
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)
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if (cpuis("STM32L4?3*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L?2*"))||(cpuis("STM32L475*"))
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(
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menuitem "LCD" "per , ""LCD (Liquid crystal display controller)"""
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)
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menuitem "TSC" "per , ""TSC (Touch sensing controller)"""
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menuitem "RNG" "per , ""RNG (Random number generator)"""
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if (!cpuis("STM32L4?1*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L433*"))&&(!cpuis("STM32L452*"))
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(
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menuitem "AES" "per , ""AES (Advanced encryption standard hardware accelerator)"""
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)
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popup "Timers"
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(
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menuitem "TIM1" "per , ""TIM1/TIM8 (Advanced-control timers 1/8),TIM1"""
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if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))
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(
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menuitem "TIM8" "per , ""TIM1/TIM8 (Advanced-control timers 1/8),TIM8"""
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)
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menuitem "TIM2" "per , ""TIM2/3/4/5 (General-purpose timers),TIM2"""
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if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))
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(
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menuitem "TIM3" "per , ""TIM2/3/4/5 (General-purpose timers),TIM3"""
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menuitem "TIM4" "per , ""TIM2/3/4/5 (General-purpose timers),TIM4"""
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menuitem "TIM5" "per , ""TIM2/3/4/5 (General-purpose timers),TIM5"""
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)
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menuitem "TIM15" "per , ""TIM15/16/17 (General-purpose timers),TIM15"""
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menuitem "TIM16" "per , ""TIM15/16/17 (General-purpose timers),TIM16"""
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if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))
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(
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menuitem "TIM17" "per , ""TIM15/16/17 (General-purpose timers),TIM17"""
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)
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menuitem "TIM6" "per , ""TIM6/7 (Basic timers),TIM6"""
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menuitem "TIM7" "per , ""TIM6/7 (Basic timers),TIM7"""
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menuitem "LPTIM1" "per , ""LPTIM1/2 (Low power timers),LPTIM1"""
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menuitem "LPTIM2" "per , ""LPTIM1/2 (Low power timers),LPTIM2"""
|
|
)
|
|
menuitem "IWDG" "per , ""IWDG (Independent watchdog)"""
|
|
menuitem "WWDG" "per , ""WWDG (System window watchdog)"""
|
|
menuitem "RTC" "per , ""RTC (Real-time clock)"""
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C 1" "per , ""I2C (Inter-integrated circuit interface),I2C 1"""
|
|
if (!cpuis("STM32L431K*"))
|
|
(
|
|
menuitem "I2C 2" "per , ""I2C (Inter-integrated circuit interface),I2C 2"""
|
|
)
|
|
menuitem "I2C 3" "per , ""I2C (Inter-integrated circuit interface),I2C 3"""
|
|
if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*"))
|
|
(
|
|
menuitem "I2C 4" "per , ""I2C (Inter-integrated circuit interface),I2C 4"""
|
|
)
|
|
)
|
|
popup "USART"
|
|
(
|
|
menuitem "USART1" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART1"""
|
|
menuitem "USART2" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART2"""
|
|
if (!cpuis("STM32L432*")&&!cpuis("STM32L442*")&&!cpuis("STM32L431K*"))
|
|
(
|
|
menuitem "USART3" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART3"""
|
|
)
|
|
if (!cpuis("STM32L4?2*")&&!cpuis("STM32L4?3*")&&!cpuis("STM32L431*")&&!cpuis("STM32L451*"))
|
|
(
|
|
menuitem "UART4" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),UART4"""
|
|
menuitem "UART5" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),UART5"""
|
|
)
|
|
)
|
|
menuitem "LPUART" "per , ""LPUART (Low-power universal asynchronous receiver/transmitter)"""
|
|
popup "SPI"
|
|
(
|
|
menuitem "SPI1" "per , ""SPI (Serial peripheral interface),SPI1"""
|
|
if (!cpuis("STM32L431K*"))
|
|
(
|
|
menuitem "SPI2" "per , ""SPI (Serial peripheral interface),SPI2"""
|
|
)
|
|
menuitem "SPI3" "per , ""SPI (Serial peripheral interface),SPI3"""
|
|
)
|
|
popup "SAI"
|
|
(
|
|
menuitem "SAI1" "per , ""SAI (Serial audio interface),SAI1"""
|
|
if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*"))
|
|
(
|
|
menuitem "SAI2" "per , ""SAI (Serial audio interface),SAI2"""
|
|
)
|
|
)
|
|
if (!cpuis("STM32L451*")&&!cpuis("STM32L452*")&&!cpuis("STM32L462*"))
|
|
(
|
|
menuitem "SWPMI" "per , ""SWPMI (Single wire protocol master interface)"""
|
|
)
|
|
if (!cpuis("STM32L432*")&&!cpuis("STM32L442*")&&!cpuis("STM32L433CB")&&!cpuis("STM32L431C*")&&!cpuis("STM32L431K*")&&!cpuis("STM32L462C*")&&!cpuis("STM32L452C*")&&!cpuis("STM32L451C*"))
|
|
(
|
|
menuitem "SDMMC" "per , ""SDMMC (SD/SDIO/MMC card host interface)"""
|
|
)
|
|
menuitem "CAN" "per , ""CAN (Controller area network)"""
|
|
if (cpuis("STM32L4?2*")||cpuis("STM32L4?3*"))
|
|
(
|
|
menuitem "USB" "per , ""USB (Universal serial bus)"""
|
|
)
|
|
if (cpuis("STM32L4?5*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))
|
|
(
|
|
menuitem "OTG_FS" "per , ""OTG_FS (USB on-the-go full-speed)"""
|
|
)
|
|
menuitem "DBG" "per , ""DBG (Debug support)"""
|
|
menuitem "Device ID" "per , ""Unique device ID registers"""
|
|
menuitem "Flash size data reg" "per , ""Flash size data register"""
|
|
)
|
|
)
|