; -------------------------------------------------------------------------------- ; @Title: STM32L4 Specific Menu ; @Props: Released ; @Author: MKK, MAJ, KOL, WWI, KAW, BCA, DPR, TRJ, ASK ; @Changelog: 2015-11-03 MAJ ; 2016-09-08 WWI ; 2016-11-21 KOL ; 2017-01-30 KAW ; 2017-11-07 KOL ; 2017-11-17 DPR ; 2017-12-13 ASK ; @Manufacturer: STM - ST Microelectronics N.V. ; @Chip: STM32L476JG, STM32L476QE, STM32L476QG, STM32L476RC, STM32L476RE, ; STM32L476RG, STM32L476VC, STM32L476VE, STM32L476VG, STM32L476ZE, ; STM32L476ZG, STM32L432KC, STM32L433CC, STM32L433RC, STM32L433VC, ; STM32L442KC, STM32L443CC, STM32L443RC, STM32L443VC, STM32L471QE, ; STM32L471QG, STM32L471RE, STM32L471RG, STM32L471VE, STM32L471VG, ; STM32L471ZE, STM32L471ZG, STM32L475RC, STM32L475RE, STM32L475RG, ; STM32L475VC, STM32L475VE, STM32L475VG, STM32L476JE, STM32L476ME, ; STM32L476MG, STM32L486JG, STM32L431CB, STM32L431CC, STM32L431KB, ; STM32L431KC, STM32L431RB, STM32L431RC, STM32L431VC, STM32L432KB, ; STM32L433CB, STM32L433RB, STM32L4A6RG, STM32L4A6VG, STM32L4A6QG, ; STM32L4A6ZG, STM32L4A6AG, STM32L496RG, STM32L496RE, STM32L496VG, ; STM32L496VE, STM32L496QG, STM32L496QE, STM32L496ZG, STM32L496ZE, ; STM32L496AG, STM32L496AE, STM32L451CC, STM32L451CE, STM32L451RC, ; STM32L451RE, STM32L451VC, STM32L451VE, STM32L452CC, STM32L452CE, ; STM32L452RC, STM32L452RE, STM32L452VC, STM32L452VE, STM32L462CE, ; STM32L462RE, STM32L462VE ; @Core: Cortex-M4, Cortex-M4F ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menstm32l4.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if STRING.SCAN(CORENAME(),"M4F",0.)>0. ( popup "[:chip]Core Registers (Cortex-M4F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) else ( popup "[:chip]Core Registers (Cortex-M4)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator menuitem "FLASH" "per , ""FLASH (Embedded flash memory)""" menuitem "FW" "per , ""FW (Firewall)""" menuitem "PWR" "per , ""PWR (Power control)""" menuitem "RCC" "per , ""RCC (Reset and clock control)""" if (cpuis("STM32L4?2*"))||(cpuis("STM32L4?3*"))||(cpuis("STM32L431*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*")) ( menuitem "CRS" "per , ""CRS (Clock recovery system)""" ) popup "General-purpose I/Os" ( menuitem "GPIO A" "per , ""GPIO (General-purpose I/Os),GPIO A""" menuitem "GPIO B" "per , ""GPIO (General-purpose I/Os),GPIO B""" menuitem "GPIO C" "per , ""GPIO (General-purpose I/Os),GPIO C""" if (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L431R*"))||(cpuis("STM32L433R*"))&&(!cpuis("STM32L443VC"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*"))||(cpuis("STM32L451R*"))||(cpuis("STM32L452R*"))||(cpuis("STM32L462R*")) ( menuitem "GPIO D" "per , ""GPIO (General-purpose I/Os),GPIO D""" ) if (cpuis("STM32L471VG"))||(cpuis("STM32L431V*"))||(cpuis("STM32L4?6V*"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451V*"))||(cpuis("STM32L452V*"))||(cpuis("STM32L462V*")) ( menuitem "GPIO E" "per , ""GPIO (General-purpose I/Os),GPIO E""" ) if (cpuis("STM32L471ZE"))||(cpuis("STM32L471ZG"))||(cpuis("STM32L471QG"))||(cpuis("STM32L4?6Q*"))||(cpuis("STM32L4?6Z*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) ( menuitem "GPIO F" "per , ""GPIO (General-purpose I/Os),GPIO F""" menuitem "GPIO G" "per , ""GPIO (General-purpose I/Os),GPIO G""" ) if (!cpuis("STM32L471VG")) ( menuitem "GPIO H" "per , ""GPIO (General-purpose I/Os),GPIO H""" ) if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) ( menuitem "GPIO I" "per , ""GPIO (General-purpose I/Os),GPIO I""" ) ) menuitem "SYSCFG" "per , ""SYSCFG (System configuration controller)""" popup "DMA" ( menuitem "DMA1" "per , ""DMA (Direct memory access),DMA1""" menuitem "DMA2" "per , ""DMA (Direct memory access),DMA2""" ) if (!cpuis("STM32L462*")&&!cpuis("STM32L452*")&&!cpuis("STM32L451*")) ( menuitem "DMA2D" "per , ""DMA2D (Chrom-Art Accelerator controller)""" ) menuitem "EXTI" "per , ""EXTI (Extended interrupts and events controller)""" menuitem "CRC" "per , ""CRC (Cyclic redundancy check calculation unit)""" if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) ( menuitem "FSMC" "per , ""FSMC (Flexible static memory controller)""" ) menuitem "QUADSPI" "per , ""QUADSPI (Quad serial peripheral interface)""" menuitem "ADC" "per , ""ADC (Analog-to-digital converters)""" menuitem "DAC" "per , ""DAC (Digital-to-analog converter)""" if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) ( menuitem "DCMI" "per , ""DCMI (Digital camera interface)""" ) menuitem "VREF" "per , ""VREF (Voltage reference buffer)""" menuitem "COMP" "per , ""COMP (Comparator)""" menuitem "OPAMP" "per , ""OPAMP (Operational amplifiers)""" if (cpuis("STM32L44*"))||(cpuis("STM32L43*"))||(cpuis("STM32L4?6*"))&&(!cpuis("STM32L431*")) ( menuitem "DFSDM" "per , ""DFSDM (Digital filter for sigma delta modulators)""" ) if (cpuis("STM32L4?3*"))||(cpuis("STM32L4?6*"))||(cpuis("STM32L?2*"))||(cpuis("STM32L475*")) ( menuitem "LCD" "per , ""LCD (Liquid crystal display controller)""" ) menuitem "TSC" "per , ""TSC (Touch sensing controller)""" menuitem "RNG" "per , ""RNG (Random number generator)""" if (!cpuis("STM32L4?1*"))&&(!cpuis("STM32L432*"))&&(!cpuis("STM32L433*"))&&(!cpuis("STM32L452*")) ( menuitem "AES" "per , ""AES (Advanced encryption standard hardware accelerator)""" ) popup "Timers" ( menuitem "TIM1" "per , ""TIM1/TIM8 (Advanced-control timers 1/8),TIM1""" if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) ( menuitem "TIM8" "per , ""TIM1/TIM8 (Advanced-control timers 1/8),TIM8""" ) menuitem "TIM2" "per , ""TIM2/3/4/5 (General-purpose timers),TIM2""" if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*")) ( menuitem "TIM3" "per , ""TIM2/3/4/5 (General-purpose timers),TIM3""" menuitem "TIM4" "per , ""TIM2/3/4/5 (General-purpose timers),TIM4""" menuitem "TIM5" "per , ""TIM2/3/4/5 (General-purpose timers),TIM5""" ) menuitem "TIM15" "per , ""TIM15/16/17 (General-purpose timers),TIM15""" menuitem "TIM16" "per , ""TIM15/16/17 (General-purpose timers),TIM16""" if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) ( menuitem "TIM17" "per , ""TIM15/16/17 (General-purpose timers),TIM17""" ) menuitem "TIM6" "per , ""TIM6/7 (Basic timers),TIM6""" menuitem "TIM7" "per , ""TIM6/7 (Basic timers),TIM7""" menuitem "LPTIM1" "per , ""LPTIM1/2 (Low power timers),LPTIM1""" menuitem "LPTIM2" "per , ""LPTIM1/2 (Low power timers),LPTIM2""" ) menuitem "IWDG" "per , ""IWDG (Independent watchdog)""" menuitem "WWDG" "per , ""WWDG (System window watchdog)""" menuitem "RTC" "per , ""RTC (Real-time clock)""" popup "I2C" ( menuitem "I2C 1" "per , ""I2C (Inter-integrated circuit interface),I2C 1""" if (!cpuis("STM32L431K*")) ( menuitem "I2C 2" "per , ""I2C (Inter-integrated circuit interface),I2C 2""" ) menuitem "I2C 3" "per , ""I2C (Inter-integrated circuit interface),I2C 3""" if (cpuis("STM32L496*"))||(cpuis("STM32L4A6*"))||(cpuis("STM32L451*"))||(cpuis("STM32L452*"))||(cpuis("STM32L462*")) ( menuitem "I2C 4" "per , ""I2C (Inter-integrated circuit interface),I2C 4""" ) ) popup "USART" ( menuitem "USART1" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART1""" menuitem "USART2" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART2""" if (!cpuis("STM32L432*")&&!cpuis("STM32L442*")&&!cpuis("STM32L431K*")) ( menuitem "USART3" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),USART3""" ) if (!cpuis("STM32L4?2*")&&!cpuis("STM32L4?3*")&&!cpuis("STM32L431*")&&!cpuis("STM32L451*")) ( menuitem "UART4" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),UART4""" menuitem "UART5" "per , ""USART (Universal synchronous asynchronous receiver/transmitter),UART5""" ) ) menuitem "LPUART" "per , ""LPUART (Low-power universal asynchronous receiver/transmitter)""" popup "SPI" ( menuitem "SPI1" "per , ""SPI (Serial peripheral interface),SPI1""" if (!cpuis("STM32L431K*")) ( menuitem "SPI2" "per , ""SPI (Serial peripheral interface),SPI2""" ) menuitem "SPI3" "per , ""SPI (Serial peripheral interface),SPI3""" ) popup "SAI" ( menuitem "SAI1" "per , ""SAI (Serial audio interface),SAI1""" if (!cpuis("STM32L4?2*"))&&(!cpuis("STM32L4?3*"))&&(!cpuis("STM32L431*"))&&(!cpuis("STM32L451*")) ( menuitem "SAI2" "per , ""SAI (Serial audio interface),SAI2""" ) ) if (!cpuis("STM32L451*")&&!cpuis("STM32L452*")&&!cpuis("STM32L462*")) ( menuitem "SWPMI" "per , ""SWPMI (Single wire protocol master interface)""" ) if (!cpuis("STM32L432*")&&!cpuis("STM32L442*")&&!cpuis("STM32L433CB")&&!cpuis("STM32L431C*")&&!cpuis("STM32L431K*")&&!cpuis("STM32L462C*")&&!cpuis("STM32L452C*")&&!cpuis("STM32L451C*")) ( menuitem "SDMMC" "per , ""SDMMC (SD/SDIO/MMC card host interface)""" ) menuitem "CAN" "per , ""CAN (Controller area network)""" if (cpuis("STM32L4?2*")||cpuis("STM32L4?3*")) ( menuitem "USB" "per , ""USB (Universal serial bus)""" ) if (cpuis("STM32L4?5*"))||(cpuis("STM32L496*"))||(cpuis("STM32L4A6*")) ( menuitem "OTG_FS" "per , ""OTG_FS (USB on-the-go full-speed)""" ) menuitem "DBG" "per , ""DBG (Debug support)""" menuitem "Device ID" "per , ""Unique device ID registers""" menuitem "Flash size data reg" "per , ""Flash size data register""" ) )