703 lines
38 KiB
Plaintext
703 lines
38 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: S32G3 Specific Menu
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; @Props: Released
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; @Author: KWI, NEJ, DAB, JON, KRZ
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; @Changelog: 2023-02-21 KRZ
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-A53, Cortex-M7F
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; @Chip: S32G338M, S32G339M, S32G358A, S32G359A, S32G378A, S32G379A,
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; S32G398A, S32G399A
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: mens32g3.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA53")
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(
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popup "[:chip]Core Registers (Cortex-A53)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch64]" "per , ""Core Registers (Cortex-A53),AArch64,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers[AArch32]" "per , ""Core Registers (Cortex-A53),AArch32,Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Interrupt Controller (GIC-500)" "per , ""Core Registers (Cortex-A53),Interrupt Controller (GIC-500)"""
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)
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)
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else if (CORENAME()=="CORTEXM7F")
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(
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popup "[:chip]Core Registers (Cortex-M7F)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M7F),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M7F),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M7F),Nested Vectored Interrupt Controller (NVIC)"""
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menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M7F),Floating-point Unit (FPU)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M7F),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M7F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M7F),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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popup "IVT Table (QSPI)"
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(
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menuitem "IVT (QSPI)" "per , ""IVT Table,IVT (QSPI)"""
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menuitem "DCD" "per , ""IVT Table,IVT (QSPI),DCD Registers"""
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menuitem "DCD Self-Test" "per , ""IVT Table,IVT (QSPI),DCD Self-Test Registers"""
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menuitem "BOOT" "per , ""IVT Table,IVT (QSPI),BOOT Registers"""
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)
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separator
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menuitem "A53_GPR;A53_CLUSTER_GPR" "per , ""A53_GPR (A53_CLUSTER_GPR)"""
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popup "ADC;SAR_ADC"
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(
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menuitem "ADC_0" "per , ""ADC (SAR_ADC),ADC_0"""
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menuitem "ADC_1" "per , ""ADC (SAR_ADC),ADC_1"""
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)
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menuitem "ATP" "per , ""ATP"""
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menuitem "BOOT_CC;Boot" "per , ""BOOT (Boot)"""
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popup "CAIU;Coherent agent interface unit (CAIU)"
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(
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menuitem "CAIU0" "per , ""CAIU (Coherent agent interface unit (CAIU)),CAIU0"""
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menuitem "CAIU1" "per , ""CAIU (Coherent agent interface unit (CAIU)),CAIU1"""
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)
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menuitem "CAIU0_QOSGENERATOR;CAIU Qos generator" "per , ""CAIU0_QOSGENERATOR (CAIU Qos generator)"""
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menuitem "CAIU1_QOSGENERATOR;CAIU Qos generator" "per , ""CAIU1_QOSGENERATOR (CAIU Qos generator)"""
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menuitem "CCTI_FAULT_CTRL;CCTI fault controller" "per , ""CCTI_FAULT_CTRL (CCTI fault controller)"""
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popup "CM7_GPR;CM7_CLUSTER_GPR"
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(
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menuitem "CM7_GPR_0" "per , ""CM7_GPR (CM7_CLUSTER_GPR),CM7_GPR_0"""
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menuitem "CM7_GPR_1" "per , ""CM7_GPR (CM7_CLUSTER_GPR),CM7_GPR_1"""
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menuitem "CM7_GPR_2" "per , ""CM7_GPR (CM7_CLUSTER_GPR),CM7_GPR_2"""
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menuitem "CM7_GPR_3" "per , ""CM7_GPR (CM7_CLUSTER_GPR),CM7_GPR_3"""
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)
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menuitem "CMIU;Coherent memory interface unit (CMIU)" "per , ""CMIU (Coherent memory interface unit (CMIU))"""
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popup "CMU_FC"
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(
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menuitem "CMU_FC_0" "per , ""CMU_FC,CMU_FC_0"""
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menuitem "CMU_FC_5" "per , ""CMU_FC,CMU_FC_5"""
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menuitem "CMU_FC_6" "per , ""CMU_FC,CMU_FC_6"""
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menuitem "CMU_FC_7" "per , ""CMU_FC,CMU_FC_7"""
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menuitem "CMU_FC_8" "per , ""CMU_FC,CMU_FC_8"""
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menuitem "CMU_FC_9" "per , ""CMU_FC,CMU_FC_9"""
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menuitem "CMU_FC_10" "per , ""CMU_FC,CMU_FC_10"""
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menuitem "CMU_FC_11" "per , ""CMU_FC,CMU_FC_11"""
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menuitem "CMU_FC_12" "per , ""CMU_FC,CMU_FC_12"""
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menuitem "CMU_FC_13" "per , ""CMU_FC,CMU_FC_13"""
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menuitem "CMU_FC_14" "per , ""CMU_FC,CMU_FC_14"""
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menuitem "CMU_FC_15" "per , ""CMU_FC,CMU_FC_15"""
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menuitem "CMU_FC_16" "per , ""CMU_FC,CMU_FC_16"""
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menuitem "CMU_FC_17" "per , ""CMU_FC,CMU_FC_17"""
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menuitem "CMU_FC_18" "per , ""CMU_FC,CMU_FC_18"""
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menuitem "CMU_FC_20" "per , ""CMU_FC,CMU_FC_20"""
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menuitem "CMU_FC_21" "per , ""CMU_FC,CMU_FC_21"""
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menuitem "CMU_FC_22" "per , ""CMU_FC,CMU_FC_22"""
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menuitem "CMU_FC_24" "per , ""CMU_FC,CMU_FC_24"""
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menuitem "CMU_FC_27" "per , ""CMU_FC,CMU_FC_27"""
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menuitem "CMU_FC_28" "per , ""CMU_FC,CMU_FC_28"""
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menuitem "CMU_FC_39" "per , ""CMU_FC,CMU_FC_39"""
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menuitem "CMU_FC_46" "per , ""CMU_FC,CMU_FC_46"""
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menuitem "CMU_FC_47" "per , ""CMU_FC,CMU_FC_47"""
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menuitem "CMU_FC_48" "per , ""CMU_FC,CMU_FC_48"""
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menuitem "CMU_FC_49" "per , ""CMU_FC,CMU_FC_49"""
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menuitem "CMU_FC_50" "per , ""CMU_FC,CMU_FC_50"""
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menuitem "CMU_FC_51" "per , ""CMU_FC,CMU_FC_51"""
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)
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popup "CMU_FM"
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(
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menuitem "CMU_FM_1" "per , ""CMU_FM,CMU_FM_1"""
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menuitem "CMU_FM_2" "per , ""CMU_FM,CMU_FM_2"""
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menuitem "CMU_FM_3" "per , ""CMU_FM,CMU_FM_3"""
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menuitem "CMU_FM_4" "per , ""CMU_FM,CMU_FM_4"""
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)
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menuitem "CRC_0;CRC" "per , ""CRC"""
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menuitem "CSR;Coherent subsystem (CSR)" "per , ""CSR (Coherent subsystem (CSR))"""
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menuitem "CTU" "per , ""CTU"""
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menuitem "DDR_GPR" "per , ""DDR_GPR"""
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menuitem "DDR_SUBSYSTEM;Subsystem" "per , ""DDR_SUBSYSTEM (Subsystem)"""
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popup "DFS"
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(
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menuitem "CORE_DFS" "per , ""DFS,CORE_DFS"""
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menuitem "PERIPH_DFS" "per , ""DFS,PERIPH_DFS"""
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)
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popup "DIRU;Directory unit (DIRU)"
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(
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menuitem "DIRU_0" "per , ""DIRU (Directory unit (DIRU)),DIRU_0"""
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menuitem "DIRU_1" "per , ""DIRU (Directory unit (DIRU)),DIRU_1"""
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)
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popup "DMA;DMA MP"
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(
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menuitem "EDMA_0_MP" "per , ""DMA (DMA MP),EDMA_0_MP"""
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menuitem "EDMA_1_MP" "per , ""DMA (DMA MP),EDMA_1_MP"""
|
|
)
|
|
popup "DMA_CRC"
|
|
(
|
|
menuitem "DMA_CRC_0" "per , ""DMA_CRC,DMA_CRC_0"""
|
|
menuitem "DMA_CRC_1" "per , ""DMA_CRC,DMA_CRC_1"""
|
|
)
|
|
popup "DMA_TCD;DMA TCD"
|
|
(
|
|
menuitem "EDMA_0_TCD" "per , ""DMA_TCD (DMA TCD),EDMA_0_TCD"""
|
|
menuitem "EDMA_1_TCD" "per , ""DMA_TCD (DMA TCD),EDMA_1_TCD"""
|
|
)
|
|
popup "DMAMUX"
|
|
(
|
|
menuitem "DMAMUX_0" "per , ""DMAMUX,DMAMUX_0"""
|
|
menuitem "DMAMUX_1" "per , ""DMAMUX,DMAMUX_1"""
|
|
menuitem "DMAMUX_2" "per , ""DMAMUX,DMAMUX_2"""
|
|
menuitem "DMAMUX_3" "per , ""DMAMUX,DMAMUX_3"""
|
|
)
|
|
popup "EIM"
|
|
(
|
|
menuitem "EIM" "per , ""EIM,EIM"""
|
|
menuitem "EIM_0" "per , ""EIM,EIM_0"""
|
|
menuitem "EIM_1" "per , ""EIM,EIM_1"""
|
|
menuitem "EIM_2" "per , ""EIM,EIM_2"""
|
|
menuitem "EIM_3" "per , ""EIM,EIM_3"""
|
|
menuitem "EIM_4" "per , ""EIM,EIM_4"""
|
|
menuitem "EIM_LLCE0" "per , ""EIM,EIM_LLCE0"""
|
|
menuitem "EIM_LLCE1" "per , ""EIM,EIM_LLCE1"""
|
|
menuitem "EIM_MISC" "per , ""EIM,EIM_MISC"""
|
|
menuitem "EIM_PFE0" "per , ""EIM,EIM_PFE0"""
|
|
menuitem "EIM_PFE1" "per , ""EIM,EIM_PFE1"""
|
|
menuitem "EIM_PFE2" "per , ""EIM,EIM_PFE2"""
|
|
menuitem "EIM_PFE3" "per , ""EIM,EIM_PFE3"""
|
|
menuitem "EIM_PFE4" "per , ""EIM,EIM_PFE4"""
|
|
menuitem "EIM_PFE5" "per , ""EIM,EIM_PFE5"""
|
|
menuitem "EIM_PFE6" "per , ""EIM,EIM_PFE6"""
|
|
)
|
|
popup "ERM"
|
|
(
|
|
menuitem "ERM_CPU0" "per , ""ERM,ERM_CPU0"""
|
|
menuitem "ERM_CPU1" "per , ""ERM,ERM_CPU1"""
|
|
menuitem "ERM_CPU2" "per , ""ERM,ERM_CPU2"""
|
|
menuitem "ERM_CPU3" "per , ""ERM,ERM_CPU3"""
|
|
menuitem "ERM_EDMA0" "per , ""ERM,ERM_EDMA0"""
|
|
menuitem "ERM_EDMA1" "per , ""ERM,ERM_EDMA1"""
|
|
menuitem "ERM_LLCE" "per , ""ERM,ERM_LLCE"""
|
|
menuitem "ERM_PER" "per , ""ERM,ERM_PER"""
|
|
menuitem "ERM_PFE0" "per , ""ERM,ERM_PFE0"""
|
|
menuitem "ERM_PFE1" "per , ""ERM,ERM_PFE1"""
|
|
menuitem "ERM_PFE2" "per , ""ERM,ERM_PFE2"""
|
|
menuitem "ERM_PFE3" "per , ""ERM,ERM_PFE3"""
|
|
menuitem "ERM_PFE4" "per , ""ERM,ERM_PFE4"""
|
|
menuitem "ERM_PFE5" "per , ""ERM,ERM_PFE5"""
|
|
menuitem "ERM_PFE6" "per , ""ERM,ERM_PFE6"""
|
|
menuitem "ERM_PFE7" "per , ""ERM,ERM_PFE7"""
|
|
menuitem "ERM_PFE8" "per , ""ERM,ERM_PFE8"""
|
|
menuitem "ERM_PFE9" "per , ""ERM,ERM_PFE9"""
|
|
menuitem "ERM_PFE10" "per , ""ERM,ERM_PFE10"""
|
|
menuitem "ERM_PFE11" "per , ""ERM,ERM_PFE11"""
|
|
menuitem "ERM_PFE12" "per , ""ERM,ERM_PFE12"""
|
|
menuitem "ERM_PFE13" "per , ""ERM,ERM_PFE13"""
|
|
menuitem "ERM_PFE14" "per , ""ERM,ERM_PFE14"""
|
|
menuitem "ERM_PFE15" "per , ""ERM,ERM_PFE15"""
|
|
menuitem "ERM_STDBY_SRAM" "per , ""ERM,ERM_STDBY_SRAM"""
|
|
)
|
|
menuitem "FCCU" "per , ""FCCU"""
|
|
popup "FLEXCAN;CAN"
|
|
(
|
|
menuitem "CAN_0" "per , ""FLEXCAN (CAN),CAN_0"""
|
|
menuitem "CAN_1" "per , ""FLEXCAN (CAN),CAN_1"""
|
|
menuitem "CAN_2" "per , ""FLEXCAN (CAN),CAN_2"""
|
|
menuitem "CAN_3" "per , ""FLEXCAN (CAN),CAN_3"""
|
|
)
|
|
menuitem "FR_0;FlexRay" "per , ""FLEXRAY (FlexRay)"""
|
|
popup "FLEXTIMER;FTM"
|
|
(
|
|
menuitem "FTM_0" "per , ""FLEXTIMER (FTM),FTM_0"""
|
|
menuitem "FTM_1" "per , ""FLEXTIMER (FTM),FTM_1"""
|
|
)
|
|
menuitem "FSC;Functional safety controller (FSC)" "per , ""FSC (Functional safety controller (FSC))"""
|
|
menuitem "FXOSC" "per , ""FXOSC"""
|
|
menuitem "GMAC_0;GMAC" "per , ""GMAC"""
|
|
popup "I2C;Inter-Integrated Circuit"
|
|
(
|
|
menuitem "I2C_0" "per , ""I2C (Inter-Integrated Circuit),I2C_0"""
|
|
menuitem "I2C_1" "per , ""I2C (Inter-Integrated Circuit),I2C_1"""
|
|
menuitem "I2C_2" "per , ""I2C (Inter-Integrated Circuit),I2C_2"""
|
|
menuitem "I2C_3" "per , ""I2C (Inter-Integrated Circuit),I2C_3"""
|
|
menuitem "I2C_4" "per , ""I2C (Inter-Integrated Circuit),I2C_4"""
|
|
)
|
|
menuitem "JDC" "per , ""JDC"""
|
|
popup "LINFLEXD;LINFlexD"
|
|
(
|
|
menuitem "LINFLEXD_0" "per , ""LINFLEXD (LINFlexD),LINFLEXD_0"""
|
|
menuitem "LINFLEXD_1" "per , ""LINFLEXD (LINFlexD),LINFLEXD_1"""
|
|
menuitem "LINFLEXD_2" "per , ""LINFLEXD (LINFlexD),LINFLEXD_2"""
|
|
)
|
|
menuitem "LLCE_CORE_TO_CORE;Core-to-core" "per , ""LLCE_CORE_TO_CORE (Core-to-core)"""
|
|
menuitem "LLCE_SYSCTRL;LLCE" "per , ""LLCE_SYSCTRL (LLCE)"""
|
|
popup "MC_CGM"
|
|
(
|
|
menuitem "MC_CGM_0" "per , ""MC_CGM,MC_CGM_0"""
|
|
menuitem "MC_CGM_1" "per , ""MC_CGM,MC_CGM_1"""
|
|
menuitem "MC_CGM_2" "per , ""MC_CGM,MC_CGM_2"""
|
|
menuitem "MC_CGM_5" "per , ""MC_CGM,MC_CGM_5"""
|
|
menuitem "MC_CGM_6" "per , ""MC_CGM,MC_CGM_6"""
|
|
)
|
|
menuitem "MC_ME" "per , ""MC_ME"""
|
|
menuitem "MC_RGM" "per , ""MC_RGM"""
|
|
menuitem "MCM" "per , ""MCM"""
|
|
menuitem "MDM_AP" "per , ""MDM_AP"""
|
|
menuitem "MSCM" "per , ""MSCM"""
|
|
popup "MU;Messaging Unit"
|
|
(
|
|
menuitem "MU0__MUA" "per , ""MU (Messaging Unit),MU0__MUA"""
|
|
menuitem "MU0__MUB" "per , ""MU (Messaging Unit),MU0__MUB"""
|
|
menuitem "MU1__MUA" "per , ""MU (Messaging Unit),MU1__MUA"""
|
|
menuitem "MU1__MUB" "per , ""MU (Messaging Unit),MU1__MUB"""
|
|
menuitem "MU2__MUA" "per , ""MU (Messaging Unit),MU2__MUA"""
|
|
menuitem "MU2__MUB" "per , ""MU (Messaging Unit),MU2__MUB"""
|
|
menuitem "MU3__MUA" "per , ""MU (Messaging Unit),MU3__MUA"""
|
|
menuitem "MU3__MUB" "per , ""MU (Messaging Unit),MU3__MUB"""
|
|
)
|
|
popup "NCBUID_RESET_VALUE;Non-coherent bridge unit (NCBU)"
|
|
(
|
|
menuitem "NCBU0" "per , ""NCBUID_RESET_VALUE (Non-coherent bridge unit (NCBU)),NCBU0"""
|
|
menuitem "NCBU1" "per , ""NCBUID_RESET_VALUE (Non-coherent bridge unit (NCBU)),NCBU1"""
|
|
)
|
|
menuitem "OCOTP_1;OCOTP" "per , ""OCOTP"""
|
|
menuitem "OCOTP_GPR;Boot" "per , ""OCOTP_GPR (Boot)"""
|
|
menuitem "PCIE_DMA" "per , ""PCIE_DMA"""
|
|
menuitem "PCIE_EP" "per , ""PCIE_EP"""
|
|
menuitem "PCIE_RC" "per , ""PCIE_RC"""
|
|
menuitem "PERF_REGISTERS;Performance monitor" "per , ""PERF_REGISTERS (Performance monitor)"""
|
|
popup "PIT"
|
|
(
|
|
menuitem "PIT_0" "per , ""PIT,PIT_0"""
|
|
menuitem "PIT_1" "per , ""PIT,PIT_1"""
|
|
)
|
|
popup "PLLDIG"
|
|
(
|
|
menuitem "ACCEL_PLL" "per , ""PLLDIG,ACCEL_PLL"""
|
|
menuitem "CORE_PLL" "per , ""PLLDIG,CORE_PLL"""
|
|
menuitem "DDR_PLL" "per , ""PLLDIG,DDR_PLL"""
|
|
menuitem "PERIPH_PLL" "per , ""PLLDIG,PERIPH_PLL"""
|
|
)
|
|
menuitem "PMC" "per , ""PMC"""
|
|
menuitem "PMUEVENTOBSERVER;PMUEVENT observer" "per , ""PMUEVENTOBSERVER (PMUEVENT observer)"""
|
|
menuitem "QUADSPI;QuadSPI" "per , ""QUADSPI (QuadSPI)"""
|
|
menuitem "QUADSPI_ARDB;ARDB" "per , ""QUADSPI_ARDB (ARDB)"""
|
|
menuitem "RDC;Reset Domain Controller (RDC)" "per , ""RESET (Reset Control)"""
|
|
menuitem "RTC" "per , ""RTC (Real-time Counter)"""
|
|
menuitem "S32G_GPR;SRC" "per , ""S32G_GPR (SRC)"""
|
|
menuitem "S32G_STDBY_GPR" "per , ""S32G_STDBY_GPR"""
|
|
menuitem "SBSW" "per , ""SBSW"""
|
|
menuitem "SECURITY_CC;Security subsystem" "per , ""SECURITY (Security subsystem)"""
|
|
popup "SELFTEST_GPR"
|
|
(
|
|
menuitem "SELFTEST_GPR_CHIPTOP" "per , ""SELFTEST_GPR,SELFTEST_GPR_CHIPTOP"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0_CPU0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0_CPU0"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0_CPU1" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0_CPU1"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0_CPU2" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0_CPU2"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0_CPU3" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0_CPU3"""
|
|
menuitem "SELFTEST_GPR_CLUSTER0_GIC0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER0_GIC0"""
|
|
menuitem "SELFTEST_GPR_CLUSTER1_CPU0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER1_CPU0"""
|
|
menuitem "SELFTEST_GPR_CLUSTER1_CPU1" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER1_CPU1"""
|
|
menuitem "SELFTEST_GPR_CLUSTER1_CPU2" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER1_CPU2"""
|
|
menuitem "SELFTEST_GPR_CLUSTER1_CPU3" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER1_CPU3"""
|
|
menuitem "SELFTEST_GPR_CLUSTER1_GIC1" "per , ""SELFTEST_GPR,SELFTEST_GPR_CLUSTER1_GIC1"""
|
|
menuitem "SELFTEST_GPR_CM7_CLUSTER_0" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_CLUSTER_0"""
|
|
menuitem "SELFTEST_GPR_CM7_CLUSTER_1" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_CLUSTER_1"""
|
|
menuitem "SELFTEST_GPR_CM7_CLUSTER_2" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_CLUSTER_2"""
|
|
menuitem "SELFTEST_GPR_CM7_CLUSTER_3" "per , ""SELFTEST_GPR,SELFTEST_GPR_CM7_CLUSTER_3"""
|
|
menuitem "SELFTEST_GPR_DDR" "per , ""SELFTEST_GPR,SELFTEST_GPR_DDR"""
|
|
menuitem "SELFTEST_GPR_DDR0" "per , ""SELFTEST_GPR,SELFTEST_GPR_DDR0"""
|
|
menuitem "SELFTEST_GPR_DDR_SS" "per , ""SELFTEST_GPR,SELFTEST_GPR_DDR_SS"""
|
|
menuitem "SELFTEST_GPR_DDR_SS1" "per , ""SELFTEST_GPR,SELFTEST_GPR_DDR_SS1"""
|
|
menuitem "SELFTEST_GPR_DDR_SS2" "per , ""SELFTEST_GPR,SELFTEST_GPR_DDR_SS2"""
|
|
menuitem "SELFTEST_GPR_FULL_CHECKER" "per , ""SELFTEST_GPR,SELFTEST_GPR_FULL_CHECKER"""
|
|
menuitem "SELFTEST_GPR_FULL_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_FULL_HYBRID"""
|
|
menuitem "SELFTEST_GPR_FULL_OFFCC" "per , ""SELFTEST_GPR,SELFTEST_GPR_FULL_OFFCC"""
|
|
menuitem "SELFTEST_GPR_FULL_PRIME" "per , ""SELFTEST_GPR,SELFTEST_GPR_FULL_PRIME"""
|
|
menuitem "SELFTEST_GPR_HSE_LLCE" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSE_LLCE"""
|
|
menuitem "SELFTEST_GPR_HSE_RUN" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSE_RUN"""
|
|
menuitem "SELFTEST_GPR_HSIO_ENET" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSIO_ENET"""
|
|
menuitem "SELFTEST_GPR_HSIO_SDHCQSPI" "per , ""SELFTEST_GPR,SELFTEST_GPR_HSIO_SDHCQSPI"""
|
|
menuitem "SELFTEST_GPR_HYBRID_SCAN" "per , ""SELFTEST_GPR,SELFTEST_GPR_HYBRID_SCAN"""
|
|
menuitem "SELFTEST_GPR_LLCE_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_LLCE_LBIST"""
|
|
menuitem "SELFTEST_GPR_LLCE_PART1" "per , ""SELFTEST_GPR,SELFTEST_GPR_LLCE_PART1"""
|
|
menuitem "SELFTEST_GPR_LLCE_PART2" "per , ""SELFTEST_GPR,SELFTEST_GPR_LLCE_PART2"""
|
|
menuitem "SELFTEST_GPR_LS_CHECKER" "per , ""SELFTEST_GPR,SELFTEST_GPR_LS_CHECKER"""
|
|
menuitem "SELFTEST_GPR_LS_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_LS_HYBRID"""
|
|
menuitem "SELFTEST_GPR_LS_PRIME" "per , ""SELFTEST_GPR,SELFTEST_GPR_LS_PRIME"""
|
|
menuitem "SELFTEST_GPR_MEM_NOC_0" "per , ""SELFTEST_GPR,SELFTEST_GPR_MEM_NOC_0"""
|
|
menuitem "SELFTEST_GPR_MEM_NOC_1" "per , ""SELFTEST_GPR,SELFTEST_GPR_MEM_NOC_1"""
|
|
menuitem "SELFTEST_GPR_MEM_NOC_2" "per , ""SELFTEST_GPR,SELFTEST_GPR_MEM_NOC_2"""
|
|
menuitem "SELFTEST_GPR_MEM_NOC_3" "per , ""SELFTEST_GPR,SELFTEST_GPR_MEM_NOC_3"""
|
|
menuitem "SELFTEST_GPR_MISC" "per , ""SELFTEST_GPR,SELFTEST_GPR_MISC"""
|
|
menuitem "SELFTEST_GPR_NCORE_0" "per , ""SELFTEST_GPR,SELFTEST_GPR_NCORE_0"""
|
|
menuitem "SELFTEST_GPR_NCORE_1" "per , ""SELFTEST_GPR,SELFTEST_GPR_NCORE_1"""
|
|
menuitem "SELFTEST_GPR_NIU" "per , ""SELFTEST_GPR,SELFTEST_GPR_NIU"""
|
|
menuitem "SELFTEST_GPR_NOC0_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC0_HYBRID"""
|
|
menuitem "SELFTEST_GPR_NOC0_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC0_LBIST"""
|
|
menuitem "SELFTEST_GPR_NOC1_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC1_HYBRID"""
|
|
menuitem "SELFTEST_GPR_NOC1_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC1_LBIST"""
|
|
menuitem "SELFTEST_GPR_NOC2_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC2_HYBRID"""
|
|
menuitem "SELFTEST_GPR_NOC2_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC2_LBIST"""
|
|
menuitem "SELFTEST_GPR_NOC3_HYBRID" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC3_HYBRID"""
|
|
menuitem "SELFTEST_GPR_NOC3_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC3_LBIST"""
|
|
menuitem "SELFTEST_GPR_NOC_PART1" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC_PART1"""
|
|
menuitem "SELFTEST_GPR_NOC_PART2" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC_PART2"""
|
|
menuitem "SELFTEST_GPR_NOC_PART3" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC_PART3"""
|
|
menuitem "SELFTEST_GPR_NOC_PART4" "per , ""SELFTEST_GPR,SELFTEST_GPR_NOC_PART4"""
|
|
menuitem "SELFTEST_GPR_PCIE" "per , ""SELFTEST_GPR,SELFTEST_GPR_PCIE"""
|
|
menuitem "SELFTEST_GPR_PCIE_SS" "per , ""SELFTEST_GPR,SELFTEST_GPR_PCIE_SS"""
|
|
menuitem "SELFTEST_GPR_PFE_PART1" "per , ""SELFTEST_GPR,SELFTEST_GPR_PFE_PART1"""
|
|
menuitem "SELFTEST_GPR_PFE_PART2" "per , ""SELFTEST_GPR,SELFTEST_GPR_PFE_PART2"""
|
|
menuitem "SELFTEST_GPR_PFE_PART3" "per , ""SELFTEST_GPR,SELFTEST_GPR_PFE_PART3"""
|
|
menuitem "SELFTEST_GPR_REST" "per , ""SELFTEST_GPR,SELFTEST_GPR_REST"""
|
|
menuitem "SELFTEST_GPR_REST_CHECKER" "per , ""SELFTEST_GPR,SELFTEST_GPR_REST_CHECKER"""
|
|
menuitem "SELFTEST_GPR_REST_LBIST" "per , ""SELFTEST_GPR,SELFTEST_GPR_REST_LBIST"""
|
|
menuitem "SELFTEST_GPR_SAFE_FULL_DOMAIN_PARTITION" "per , ""SELFTEST_GPR,SELFTEST_GPR_SAFE_FULL_DOMAIN_PARTITION"""
|
|
)
|
|
menuitem "SELFTEST_GPR_TOP" "per , ""SELFTEST_GPR_TOP"""
|
|
menuitem "SEMA42" "per , ""SEMA42"""
|
|
menuitem "SERDES_DMA_PCIE_1;PCIE_DMA" "per , ""SERDES_DMA_PCIE_1 (PCIE_DMA)"""
|
|
menuitem "SERDES_EP_PCIE_1;PCIE_EP" "per , ""SERDES_EP_PCIE_1 (PCIE_EP)"""
|
|
popup "SERDES_GPR"
|
|
(
|
|
menuitem "SERDES_0_GPR" "per , ""SERDES_GPR,SERDES_0_GPR"""
|
|
menuitem "SERDES_1_GPR" "per , ""SERDES_GPR,SERDES_1_GPR"""
|
|
)
|
|
menuitem "SERDES_PHY;SerDes_PHY" "per , ""SERDES_PHY (SerDes_PHY)"""
|
|
menuitem "SERDES_PHY_PCIE_1;SerDes_PHY" "per , ""SERDES_PHY_PCIE_1 (SerDes_PHY)"""
|
|
menuitem "SERDES_RC_PCIE_1;PCIE_RC" "per , ""SERDES_RC_PCIE_1 (PCIE_RC)"""
|
|
menuitem "SERDES_SS;SerDes_SS" "per , ""SERDES_SS (SerDes_SS)"""
|
|
menuitem "SERDES_SS_PCIE_1;SerDes_SS" "per , ""SERDES_SS_PCIE_1 (SerDes_SS)"""
|
|
menuitem "SERDES_XPCS_0;SerDes_XPCS" "per , ""SERDES_XPCS_0 (SerDes_XPCS)"""
|
|
menuitem "SERDES_XPCS_0_PCIE_1;SerDes_XPCS" "per , ""SERDES_XPCS_0_PCIE_1 (SerDes_XPCS)"""
|
|
menuitem "SERDES_XPCS_1;SerDes_XPCS" "per , ""SERDES_XPCS_1 (SerDes_XPCS)"""
|
|
menuitem "SERDES_XPCS_1_PCIE_1;SerDes_XPCS" "per , ""SERDES_XPCS_1_PCIE_1 (SerDes_XPCS)"""
|
|
popup "SIUL2"
|
|
(
|
|
menuitem "SIUL2_0" "per , ""SIUL2,SIUL2_0"""
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menuitem "SIUL2_1" "per , ""SIUL2,SIUL2_1"""
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)
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popup "SPI"
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(
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menuitem "SPI_0" "per , ""SPI,SPI_0"""
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menuitem "SPI_1" "per , ""SPI,SPI_1"""
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|
menuitem "SPI_2" "per , ""SPI,SPI_2"""
|
|
menuitem "SPI_3" "per , ""SPI,SPI_3"""
|
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menuitem "SPI_4" "per , ""SPI,SPI_4"""
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menuitem "SPI_5" "per , ""SPI,SPI_5"""
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)
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popup "SRAMC"
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|
(
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menuitem "SRAMC" "per , ""SRAMC,SRAMC"""
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menuitem "SRAMC_1" "per , ""SRAMC,SRAMC_1"""
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|
menuitem "SRAMC_2" "per , ""SRAMC,SRAMC_2"""
|
|
menuitem "SRAMC_3" "per , ""SRAMC,SRAMC_3"""
|
|
menuitem "STDBY_SRAM_CFG" "per , ""SRAMC,STDBY_SRAM_CFG"""
|
|
)
|
|
menuitem "SRC" "per , ""SRC (System Reset Controller)"""
|
|
menuitem "SRC_GPR;SRC_GPR_TOP" "per , ""SRC_GPR (SRC_GPR_TOP)"""
|
|
menuitem "STCU2" "per , ""STCU2"""
|
|
popup "STM;System Timer"
|
|
(
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menuitem "STM_0" "per , ""STM (System Timer),STM_0"""
|
|
menuitem "STM_1" "per , ""STM (System Timer),STM_1"""
|
|
menuitem "STM_2" "per , ""STM (System Timer),STM_2"""
|
|
menuitem "STM_3" "per , ""STM (System Timer),STM_3"""
|
|
menuitem "STM_4" "per , ""STM (System Timer),STM_4"""
|
|
menuitem "STM_5" "per , ""STM (System Timer),STM_5"""
|
|
menuitem "STM_6" "per , ""STM (System Timer),STM_6"""
|
|
menuitem "STM_7" "per , ""STM (System Timer),STM_7"""
|
|
menuitem "STM_8" "per , ""STM (System Timer),STM_8"""
|
|
menuitem "STM_9" "per , ""STM (System Timer),STM_9"""
|
|
menuitem "STM_10" "per , ""STM (System Timer),STM_10"""
|
|
menuitem "STM_11" "per , ""STM (System Timer),STM_11"""
|
|
menuitem "STM_TS" "per , ""STM (System Timer),STM_TS"""
|
|
)
|
|
popup "SWT"
|
|
(
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menuitem "SWT_0" "per , ""SWT,SWT_0"""
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|
menuitem "SWT_1" "per , ""SWT,SWT_1"""
|
|
menuitem "SWT_2" "per , ""SWT,SWT_2"""
|
|
menuitem "SWT_3" "per , ""SWT,SWT_3"""
|
|
menuitem "SWT_4" "per , ""SWT,SWT_4"""
|
|
menuitem "SWT_5" "per , ""SWT,SWT_5"""
|
|
menuitem "SWT_6" "per , ""SWT,SWT_6"""
|
|
menuitem "SWT_7" "per , ""SWT,SWT_7"""
|
|
menuitem "SWT_8" "per , ""SWT,SWT_8"""
|
|
menuitem "SWT_9" "per , ""SWT,SWT_9"""
|
|
menuitem "SWT_10" "per , ""SWT,SWT_10"""
|
|
menuitem "SWT_11" "per , ""SWT,SWT_11"""
|
|
)
|
|
menuitem "TMU" "per , ""TMU (Thermal Monitoring Unit)"""
|
|
menuitem "UMCTL2_MP" "per , ""UMCTL2_MP"""
|
|
menuitem "UMCTL2_REGS" "per , ""UMCTL2_REGS"""
|
|
menuitem "UOTG;Core" "per , ""UOTG (Core)"""
|
|
menuitem "UOTGNC;Non-core" "per , ""UOTGNC (Non-core)"""
|
|
menuitem "USDHC;uSDHC" "per , ""USDHC (Ultra Secured Digital Host Controller)"""
|
|
menuitem "WKPU" "per , ""WKPU"""
|
|
menuitem "XRDC_0" "per , ""XRDC_0"""
|
|
menuitem "XRDC_1" "per , ""XRDC_1"""
|
|
)
|
|
)
|