424 lines
16 KiB
Plaintext
424 lines
16 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RZ11 Specific Menu
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; @Props: Released
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; @Author: PID, ROK
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; @Changelog: 2019-01-31 PID
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Core: Cortex-R4, Cortex-M3
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menrzt1.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (corename()=="CORTEXM3")
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(
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popup "[:chip]Core Registers (Cortex-M3)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M3),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M3),Memory Protection Unit"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M3),Nested Vectored Interrupt Controller"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M3),Debug,Core Debug"""
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menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M3),Debug,Flash Patch and Breakpoint Unit (FPB)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M3),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else if (corename()=="CORTEXR4F")
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(
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popup "[:chip]Core Registers (Cortex-R4F)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R4F),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R4F),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R4F),MPU Control and Configuration"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R4F),Cache Control and Configuration"""
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menuitem "[:chip]TCM Control and Configuration" "per , ""Core Registers (Cortex-R4F),TCM Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R4F),System Performance Monitor"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R4F),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R4F),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-R4F),Watchpoint Control Registers"""
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)
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)
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menuitem "CPU Registers" " per , ""CPU-R (CPU Registers)"""
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menuitem "Operating Modes Registers" " per , ""OMR (Operating Modes Registers)"""
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menuitem "Reset Registers" " per , ""RST (Reset Registers)"""
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menuitem "Clock Generation Circuit Registers" " per , ""CGC (Clock Generation Circuit Registers)"""
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popup "Clock Monitor Circuit"
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(
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menuitem "CLMA0" " per , ""CLMA (Clock Monitor Circuit),CLMA0"""
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menuitem "CLMA1" " per , ""CLMA (Clock Monitor Circuit),CLMA1"""
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menuitem "CLMA2" " per , ""CLMA (Clock Monitor Circuit),CLMA2"""
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)
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menuitem "Low-Power Consumption Function" " per , ""LPCF (Low-Power Consumption Function)"""
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menuitem "Debugging Interface" " per , ""DI (Debugging Interface)"""
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menuitem "Register Write Protection Function" " per , ""RWPF (Register Write Protection Function)"""
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if cpuis("R7S910015-CR4")||cpuis("R7S910016-CR4")||cpuis("R7S910017-CR4")||cpuis("R7S910018-CR4")||cpuis("R7S910115-CR4")||cpuis("R7S910116-CR4")||cpuis("R7S910117-CR4")||cpuis("R7S910118-CR4")
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(
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popup "ICUA"
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(
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menuitem "ICUA" " per , ""ICUA (Interrupt Controller"""
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menuitem "R4VIC" " per , ""ICUA (Interrupt Controller,R4VIC (Cortex-R4 Vector Interrupt Controller)"""
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)
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)
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else
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(
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menuitem "ICUA" " per , ""ICUA (Interrupt Controller"""
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)
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menuitem "Bus State Controller" " per , ""BSC (Bus State Controller)"""
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popup "DMAC"
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(
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menuitem "DMAC0" " per , ""DMAC (Direct Memory Address Controller),DMAC 0"""
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menuitem "DMAC1" " per , ""DMAC (Direct Memory Address Controller),DMAC 1"""
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menuitem "Common" " per , ""DMAC (Direct Memory Address Controller),Common"""
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)
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menuitem "ELC" " per , ""ELC (Event Link Controller"""
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menuitem "I/O Ports Registers" " per , ""I/O (Input/Output Ports Registers)"""
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menuitem "MPC" " per , ""MPC (Multi-Function Pin Controller"""
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popup "MTU3a"
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(
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menuitem "Channel 0" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 0"""
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menuitem "Channel 1" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 1"""
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menuitem "Channel 2" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 2"""
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menuitem "Channel 3" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 3"""
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menuitem "Channel 4" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 4"""
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menuitem "Channel 5" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 5"""
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menuitem "Channel 6" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 6"""
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menuitem "Channel 7" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 7"""
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menuitem "Channel 8" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 8"""
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menuitem "Channel 9" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Channel 9"""
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menuitem "Common" " per , ""MTU3a (Multi-Function Timer Pulse Unit),Common"""
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)
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menuitem "POE3" " per , ""POE3 (Port Output Enable 3)"""
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menuitem "GPTa" " per , ""GPTa (General PWM Timer)"""
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popup "TPU"
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(
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menuitem "Unit 0" " per , ""TPU (16-bit Timer Pulse Unit),Unit 0"""
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if !cpuis("R7S910001")&&!cpuis("R7S910101")
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(
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menuitem "Unit 1" " per , ""TPU (16-bit Timer Pulse Unit),Unit 1"""
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)
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menuitem "Common Registers" " per , ""TPU (16-bit Timer Pulse Unit),Common Registers"""
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)
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popup "PPG"
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(
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menuitem "PPG0" " per , ""PPG (Programmable Pulse Generator),PPG0"""
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menuitem "PPG1" " per , ""PPG (Programmable Pulse Generator),PPG1"""
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)
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popup "CMT"
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(
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menuitem "Unit 0" " per , ""CMT (Compare Match Timer),Unit 0"""
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menuitem "Unit 1" " per , ""CMT (Compare Match Timer),Unit 1"""
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menuitem "Unit 2" " per , ""CMT (Compare Match Timer),Unit 2"""
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)
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popup "CMTW"
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(
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menuitem "CMTW0" " per , ""CMTW (Compare Match Timer W),CMTW0"""
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menuitem "CMTW1" " per , ""CMTW (Compare Match Timer W),CMTW1"""
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menuitem "Common" " per , ""CMTW (Compare Match Timer W),Common"""
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)
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popup "WDT"
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(
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menuitem "WDT 0" " per , ""WDT (Watchdog Timer),WDT 0"""
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menuitem "WDT 1" " per , ""WDT (Watchdog Timer),WDT 1"""
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)
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menuitem "IWDT" " per , ""IWDT (Independent Watchdog Timer)"""
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popup "ETHERC"
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(
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menuitem "Ethernet Interface Selection Registers" " per , ""ETHERC (Ethernet MAC),Ethernet Interface Selection Registers"""
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menuitem "Ethernet MAC Control Registers" " per , ""ETHERC (Ethernet MAC),Ethernet MAC Control Registers"""
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menuitem "Hardware Function Call Register" " per , ""ETHERC (Ethernet MAC),Hardware Function Call Register"""
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)
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popup "Ethernet Switch"
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(
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menuitem "Operating Mode Setting Register" " per , ""ETHSW (Ethernet Switch),Operating Mode Setting Register"""
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menuitem "Switch Configuration Registers" " per , ""ETHSW (Ethernet Switch),Switch Configuration Registers"""
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menuitem "Learning Interface Registers" " per , ""ETHSW (Ethernet Switch),Learning Interface Registers"""
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menuitem "MAC Port Registers" " per , ""ETHSW (Ethernet Switch),MAC Port Registers"""
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menuitem "Timer Module Registers" " per , ""ETHSW (Ethernet Switch),Timer Module Registers"""
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menuitem "DLR Module Registers" " per , ""ETHSW (Ethernet Switch),DLR Module Registers"""
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)
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if !cpuis("R7S91000?")&&!cpuis("R7S91010?")&&!cpuis("R7S910011")&&!cpuis("R7S910013")&&!cpuis("R7S910111")&&!cpuis("R7S910113")
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(
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menuitem "ESC" " per , ""ESC (EtherCAT Slave Controller"""
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)
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popup "USBh"
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(
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menuitem "OHCI" " per , ""USBh (USB 2.0 HS Host Module),OHCI Operational Registers"""
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menuitem "EHCI" " per , ""USBh (USB 2.0 HS Host Module),EHCI Operational Registers"""
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menuitem "PCI Configuration Registers For OHCI" " per , ""USBh (USB 2.0 HS Host Module),PCI Configuration Registers For OHCI"""
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menuitem "PCI Configuration Registers For EHC" " per , ""USBh (USB 2.0 HS Host Module),PCI Configuration Registers For EHCI"""
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menuitem "AHB-PCI 1" " per , ""USBh (USB 2.0 HS Host Module),AHB-PCI Bridge Configuration 1"""
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menuitem "AHB-PCI 2" " per , ""USBh (USB 2.0 HS Host Module),AHB-PCI Bridge Communication 2"""
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)
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menuitem "USBf" " per , ""USBf (USB 2.0 HS Function Module)"""
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menuitem "SCIFA" " per , ""SCIFA (Serial Communication Interface With FIFO)"""
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popup "RIICa"
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(
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menuitem "RIIC0" " per , ""RIICa (I2C Bus Interface),RIIC0"""
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menuitem "RIIC1" " per , ""RIICa (I2C Bus Interface),RIIC1"""
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)
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menuitem "RS-CAN" " per , ""RS-CAN (CAN Interface)"""
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popup "RSPIa"
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(
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menuitem "RSPI0" " per , ""RSPIa (Serial Peripheral Interface),RSPI0"""
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menuitem "RSPI1" " per , ""RSPIa (Serial Peripheral Interface),RSPI1"""
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menuitem "RSPI2" " per , ""RSPIa (Serial Peripheral Interface),RSPI2"""
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menuitem "RSPI3" " per , ""RSPIa (Serial Peripheral Interface),RSPI3"""
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)
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menuitem "SPIBSC" " per , ""SPIBSC (SPI Multi I/O Bus Controller)"""
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menuitem "CRC" " per , ""CRC (CRC Operation Units)"""
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menuitem "SSI" " per , ""SSI (Serial Sound Interface)"""
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menuitem "DSMIF" " per , ""DSMIF (Delta-Sigma Interface)"""
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menuitem "ECM" " per , ""ECM (Error Control Module)"""
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popup "S12ADC"
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(
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menuitem "S12ADC 0" " per , ""S12ADC (12-Bit A/D Converter),S12ADC 0"""
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menuitem "S12ADC 1" " per , ""S12ADC (12-Bit A/D Converter),S12ADC 1"""
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)
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menuitem "Temperature Sensor Registers" " per , ""Temperature Sensor Registers"""
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menuitem "DOC" " per , ""DOC (Data Operation Circuit)"""
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menuitem "RAM Registers" " per , ""RAM Registers"""
|
|
)
|
|
)
|