563 lines
26 KiB
Plaintext
563 lines
26 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RCARS4 Specific Menu
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; @Props: Confidential
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; @Author: RSA, DAB, PIW, KRZ
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; @Changelog: 2022-01-24 RSA
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; 2022-03-04 DAB
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; 2022-05-20 PIW
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; 2023-02-20 KRZ
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Core: Cortex-A55, Cortex-R52
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; @Chip: RCARS4, RCARS4-CR52
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menrcars4.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if (CORENAME()=="CORTEXA55")
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(
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popup "[:chip]Core Registers (Cortex-A55)"
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(
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menuitem "[:chip]ID Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration"""
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menuitem "[:chip]System Instructions[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration,System Instructions"""
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menuitem "[:chip]Memory Management Unit[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Debug Registers"""
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menuitem "[:chip]Activity Monitors Unit[AArch64]" "per , ""AArch64,Activity Monitors Unit"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,Watchpoint Registers"""
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separator
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menuitem "[:chip]LORegions Registers[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,LORegions Registers"""
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separator
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menuitem "[:chip]DynamIQ Shared Unit[AArch64]" "per , ""Core Registers (Cortex-A55),AArch64,DynamIQ Shared Unit"""
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separator
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menuitem "[:chip]ID Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,ID Registers"""
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menuitem "[:chip]System Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Memory Management Unit"""
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menuitem "[:chip]Virtualization Extensions[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Performance Monitor"""
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menuitem "[:chip]System Timer Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Generic Interrupt Controller System Registers"""
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separator
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menuitem "[:chip]Debug Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,Watchpoint Registers"""
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separator
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menuitem "[:chip]DynamIQ Shared Unit[AArch32]" "per , ""Core Registers (Cortex-A55),AArch32,DynamIQ Shared Unit"""
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separator
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menuitem "[:chip]Interrupt Controller" "per , ""Core Registers (Cortex-A55),Interrupt Controller"""
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)
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)
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if (CORENAME()=="CORTEXR52")
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(
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popup "[:chip]Core Registers (Cortex-R52)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-R52),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-R52),System Control and Configuration"""
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menuitem "[:chip]MPU Control and Configuration" "per , ""Core Registers (Cortex-R52),MPU Control and Configuration"""
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menuitem "[:chip]Memory Protection Unit PL1" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1"""
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menuitem "[:chip]Memory Protection Unit PL2" "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2"""
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menuitem "[:chip]Virtualization Extensions" "per , ""Core Registers (Cortex-R52),Virtualization Extensions"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-R52),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-R52),System Performance Monitor"""
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menuitem "[:chip]System Timer Registers" "per , ""Core Registers (Cortex-R52),System Timer Registers"""
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menuitem "[:chip]Generic Interrupt Controller CPU Interface" "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-R52),Debug Registers"""
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separator
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-R52),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Registers" "per , ""Core Registers (Cortex-R52),Watchpoint Registers"""
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)
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)
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separator
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menuitem "REALTIME_CORE" "per , ""REALTIME_CORE"""
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popup "PFC_GPIO"
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(
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menuitem "PFC_GPIO_FOR_GP0" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP0"""
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menuitem "PFC_GPIO_FOR_GP1" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP1"""
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menuitem "PFC_GPIO_FOR_GP2" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP2"""
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menuitem "PFC_GPIO_FOR_GP3" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP3"""
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menuitem "PFC_GPIO_FOR_GP4" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP4"""
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menuitem "PFC_GPIO_FOR_GP5" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP5"""
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menuitem "PFC_GPIO_FOR_GP6" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP6"""
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menuitem "PFC_GPIO_FOR_GP7" "per , ""PFC_GPIO,PFC_GPIO_FOR_GP7"""
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menuitem "PFC_GPIO_FOR_SYS0" "per , ""PFC_GPIO,PFC_GPIO_FOR_SYS0"""
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menuitem "PFC_GPIO_FOR_SYS1" "per , ""PFC_GPIO,PFC_GPIO_FOR_SYS1"""
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)
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popup "CLOCK_PULSE_GENERATOR"
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(
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_0" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_0"""
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_1" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_1"""
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_2" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_2"""
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_3" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_3"""
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_4" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_4"""
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menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_5" "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_5"""
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)
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menuitem "MODULE_STANDBY_SOFTWARE_RESET" "per , ""MODULE_STANDBY_SOFTWARE_RESET"""
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popup "APMU"
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(
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menuitem "APMU_INST_0" "per , ""APMU,APMU_INST_0"""
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menuitem "APMU_INST_1" "per , ""APMU,APMU_INST_1"""
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menuitem "APMU_INST_2" "per , ""APMU,APMU_INST_2"""
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menuitem "APMU_INST_3" "per , ""APMU,APMU_INST_3"""
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)
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popup "SYSC"
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(
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menuitem "SYSC_INST_0" "per , ""SYSC,SYSC_INST_0"""
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menuitem "SYSC_INST_1" "per , ""SYSC,SYSC_INST_1"""
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menuitem "SYSC_INST_2" "per , ""SYSC,SYSC_INST_2"""
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menuitem "SYSC_INST_3" "per , ""SYSC,SYSC_INST_3"""
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)
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popup "THS"
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(
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menuitem "THS_INST_0" "per , ""THS,THS_INST_0"""
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menuitem "THS_INST_1" "per , ""THS,THS_INST_1"""
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menuitem "THS_INST_2" "per , ""THS,THS_INST_2"""
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menuitem "THS_INST_3" "per , ""THS,THS_INST_3"""
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)
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popup "RESET_RST"
|
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(
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menuitem "RESET_RST_INST_0" "per , ""RESET_RST,RESET_RST_INST_0"""
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menuitem "RESET_RST_INST_1" "per , ""RESET_RST,RESET_RST_INST_1"""
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menuitem "RESET_RST_INST_2" "per , ""RESET_RST,RESET_RST_INST_2"""
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menuitem "RESET_RST_INST_3" "per , ""RESET_RST,RESET_RST_INST_3"""
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)
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popup "INTC"
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(
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menuitem "INTC_INST_0" "per , ""INTC,INTC_INST_0"""
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menuitem "INTC_INST_1" "per , ""INTC,INTC_INST_1"""
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menuitem "INTC_INST_2" "per , ""INTC,INTC_INST_2"""
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menuitem "INTC_INST_3" "per , ""INTC,INTC_INST_3"""
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menuitem "INTC_INST_4" "per , ""INTC,INTC_INST_4"""
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menuitem "INTC_INST_5" "per , ""INTC,INTC_INST_5"""
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)
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popup "MFIS"
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(
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menuitem "MFIS_INST_0" "per , ""MFIS,MFIS_INST_0"""
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menuitem "MFIS_INST_1" "per , ""MFIS,MFIS_INST_1"""
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)
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menuitem "ECM" "per , ""ECM"""
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popup "AXI_BUS"
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(
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menuitem "AXI_BUS_INST_0" "per , ""AXI_BUS,AXI_BUS_INST_0"""
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menuitem "AXI_BUS_INST_1" "per , ""AXI_BUS,AXI_BUS_INST_1"""
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menuitem "AXI_BUS_INST_2" "per , ""AXI_BUS,AXI_BUS_INST_2"""
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menuitem "AXI_BUS_INST_3" "per , ""AXI_BUS,AXI_BUS_INST_3"""
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)
|
|
popup "IPMMU"
|
|
(
|
|
menuitem "IPMMU_INST_0" "per , ""IPMMU,IPMMU_INST_0"""
|
|
menuitem "IPMMU_INST_1" "per , ""IPMMU,IPMMU_INST_1"""
|
|
)
|
|
popup "DMAC"
|
|
(
|
|
menuitem "DMAC_INST_0" "per , ""DMAC,DMAC_INST_0"""
|
|
menuitem "DMAC_INST_1" "per , ""DMAC,DMAC_INST_1"""
|
|
menuitem "DMAC_INST_2" "per , ""DMAC,DMAC_INST_2"""
|
|
menuitem "DMAC_INST_3" "per , ""DMAC,DMAC_INST_3"""
|
|
menuitem "DMAC_INST_4" "per , ""DMAC,DMAC_INST_4"""
|
|
menuitem "DMAC_INST_5" "per , ""DMAC,DMAC_INST_5"""
|
|
menuitem "DMAC_INST_6" "per , ""DMAC,DMAC_INST_6"""
|
|
menuitem "DMAC_INST_7" "per , ""DMAC,DMAC_INST_7"""
|
|
menuitem "DMAC_INST_8" "per , ""DMAC,DMAC_INST_8"""
|
|
menuitem "DMAC_INST_9" "per , ""DMAC,DMAC_INST_9"""
|
|
menuitem "DMAC_INST_10" "per , ""DMAC,DMAC_INST_10"""
|
|
menuitem "DMAC_INST_11" "per , ""DMAC,DMAC_INST_11"""
|
|
)
|
|
menuitem "DBSC4" "per , ""DBSC4"""
|
|
menuitem "RT_SRAM" "per , ""RT_SRAM"""
|
|
menuitem "RT_VRAM" "per , ""RT_VRAM"""
|
|
popup "GWCA"
|
|
(
|
|
menuitem "GWCA_INST_0" "per , ""GWCA,GWCA_INST_0"""
|
|
menuitem "GWCA_INST_1" "per , ""GWCA,GWCA_INST_1"""
|
|
)
|
|
menuitem "R_SWITCH_2" "per , ""R_SWITCH_2"""
|
|
menuitem "ETHERNET_SWITCH_SRAM" "per , ""ETHERNET_SWITCH_SRAM"""
|
|
menuitem "ETHERNET_SERDES_SRAM" "per , ""ETHERNET_SERDES_SRAM"""
|
|
popup "SCIF"
|
|
(
|
|
menuitem "SCIF_INST_0" "per , ""SCIF,SCIF_INST_0"""
|
|
menuitem "SCIF_INST_1" "per , ""SCIF,SCIF_INST_1"""
|
|
menuitem "SCIF_INST_2" "per , ""SCIF,SCIF_INST_2"""
|
|
menuitem "SCIF_INST_3" "per , ""SCIF,SCIF_INST_3"""
|
|
)
|
|
popup "HSCIF"
|
|
(
|
|
menuitem "HSCIF_INST_0" "per , ""HSCIF,HSCIF_INST_0"""
|
|
menuitem "HSCIF_INST_1" "per , ""HSCIF,HSCIF_INST_1"""
|
|
menuitem "HSCIF_INST_2" "per , ""HSCIF,HSCIF_INST_2"""
|
|
menuitem "HSCIF_INST_3" "per , ""HSCIF,HSCIF_INST_3"""
|
|
)
|
|
popup "I2C"
|
|
(
|
|
menuitem "I2C_INST_0" "per , ""I2C,I2C_INST_0"""
|
|
menuitem "I2C_INST_1" "per , ""I2C,I2C_INST_1"""
|
|
menuitem "I2C_INST_2" "per , ""I2C,I2C_INST_2"""
|
|
menuitem "I2C_INST_3" "per , ""I2C,I2C_INST_3"""
|
|
menuitem "I2C_INST_4" "per , ""I2C,I2C_INST_4"""
|
|
menuitem "I2C_INST_5" "per , ""I2C,I2C_INST_5"""
|
|
)
|
|
popup "MSIOF"
|
|
(
|
|
menuitem "MSIOF_INST_0" "per , ""MSIOF,MSIOF_INST_0"""
|
|
menuitem "MSIOF_INST_1" "per , ""MSIOF,MSIOF_INST_1"""
|
|
menuitem "MSIOF_INST_2" "per , ""MSIOF,MSIOF_INST_2"""
|
|
menuitem "MSIOF_INST_3" "per , ""MSIOF,MSIOF_INST_3"""
|
|
)
|
|
menuitem "RPC" "per , ""RPC"""
|
|
menuitem "LIFEC" "per , ""LIFEC"""
|
|
popup "CRC"
|
|
(
|
|
menuitem "CRC_INST_0" "per , ""CRC,CRC_INST_0"""
|
|
menuitem "CRC_INST_1" "per , ""CRC,CRC_INST_1"""
|
|
menuitem "CRC_INST_2" "per , ""CRC,CRC_INST_2"""
|
|
menuitem "CRC_INST_3" "per , ""CRC,CRC_INST_3"""
|
|
menuitem "CRC_INST_4" "per , ""CRC,CRC_INST_4"""
|
|
menuitem "CRC_INST_5" "per , ""CRC,CRC_INST_5"""
|
|
menuitem "CRC_INST_6" "per , ""CRC,CRC_INST_6"""
|
|
menuitem "CRC_INST_7" "per , ""CRC,CRC_INST_7"""
|
|
menuitem "CRC_INST_8" "per , ""CRC,CRC_INST_8"""
|
|
menuitem "CRC_INST_9" "per , ""CRC,CRC_INST_9"""
|
|
menuitem "CRC_INST_10" "per , ""CRC,CRC_INST_10"""
|
|
menuitem "CRC_INST_11" "per , ""CRC,CRC_INST_11"""
|
|
)
|
|
popup "RFSO"
|
|
(
|
|
menuitem "RFSO_INST_0" "per , ""RFSO,RFSO_INST_0"""
|
|
menuitem "RFSO_INST_1" "per , ""RFSO,RFSO_INST_1"""
|
|
menuitem "RFSO_INST_2" "per , ""RFSO,RFSO_INST_2"""
|
|
menuitem "RFSO_INST_3" "per , ""RFSO,RFSO_INST_3"""
|
|
menuitem "RFSO_INST_4" "per , ""RFSO,RFSO_INST_4"""
|
|
menuitem "RFSO_INST_5" "per , ""RFSO,RFSO_INST_5"""
|
|
menuitem "RFSO_INST_6" "per , ""RFSO,RFSO_INST_6"""
|
|
menuitem "RFSO_INST_7" "per , ""RFSO,RFSO_INST_7"""
|
|
menuitem "RFSO_INST_8" "per , ""RFSO,RFSO_INST_8"""
|
|
menuitem "RFSO_INST_9" "per , ""RFSO,RFSO_INST_9"""
|
|
menuitem "RFSO_INST_10" "per , ""RFSO,RFSO_INST_10"""
|
|
)
|
|
popup "SDHI_MMC"
|
|
(
|
|
menuitem "SDHI_MMC_INST_0" "per , ""SDHI_MMC,SDHI_MMC_INST_0"""
|
|
menuitem "SDHI_MMC_INST_1" "per , ""SDHI_MMC,SDHI_MMC_INST_1"""
|
|
)
|
|
menuitem "UFS" "per , ""UFS"""
|
|
menuitem "RWDT" "per , ""RWDT"""
|
|
popup "WWDT"
|
|
(
|
|
menuitem "WWDT_INST_0" "per , ""WWDT,WWDT_INST_0"""
|
|
menuitem "WWDT_INST_1" "per , ""WWDT,WWDT_INST_1"""
|
|
menuitem "WWDT_INST_2" "per , ""WWDT,WWDT_INST_2"""
|
|
menuitem "WWDT_INST_3" "per , ""WWDT,WWDT_INST_3"""
|
|
menuitem "WWDT_INST_4" "per , ""WWDT,WWDT_INST_4"""
|
|
menuitem "WWDT_INST_5" "per , ""WWDT,WWDT_INST_5"""
|
|
menuitem "WWDT_INST_6" "per , ""WWDT,WWDT_INST_6"""
|
|
menuitem "WWDT_INST_7" "per , ""WWDT,WWDT_INST_7"""
|
|
menuitem "WWDT_INST_8" "per , ""WWDT,WWDT_INST_8"""
|
|
menuitem "WWDT_INST_9" "per , ""WWDT,WWDT_INST_9"""
|
|
)
|
|
menuitem "SWDT" "per , ""SWDT"""
|
|
menuitem "CMT0" "per , ""CMT0"""
|
|
popup "CMT1"
|
|
(
|
|
menuitem "CMT1_INST_0" "per , ""CMT1,CMT1_INST_0"""
|
|
menuitem "CMT1_INST_1" "per , ""CMT1,CMT1_INST_1"""
|
|
menuitem "CMT1_INST_2" "per , ""CMT1,CMT1_INST_2"""
|
|
)
|
|
popup "TMU"
|
|
(
|
|
menuitem "TMU_INST_0" "per , ""TMU,TMU_INST_0"""
|
|
menuitem "TMU_INST_1" "per , ""TMU,TMU_INST_1"""
|
|
menuitem "TMU_INST_2" "per , ""TMU,TMU_INST_2"""
|
|
menuitem "TMU_INST_3" "per , ""TMU,TMU_INST_3"""
|
|
menuitem "TMU_INST_4" "per , ""TMU,TMU_INST_4"""
|
|
)
|
|
menuitem "SCMT" "per , ""SCMT"""
|
|
menuitem "SUCMT" "per , ""SUCMT"""
|
|
menuitem "HSSTP_CPU" "per , ""HSSTP_CPU"""
|
|
menuitem "HSSTP_DEBUGGER" "per , ""HSSTP_DEBUGGER"""
|
|
popup "DEBUG_AND_TRACE_CPU"
|
|
(
|
|
menuitem "DEBUG_AND_TRACE_CPU_INST_0" "per , ""DEBUG_AND_TRACE_CPU,DEBUG_AND_TRACE_CPU_INST_0"""
|
|
menuitem "DEBUG_AND_TRACE_CPU_INST_1" "per , ""DEBUG_AND_TRACE_CPU,DEBUG_AND_TRACE_CPU_INST_1"""
|
|
)
|
|
popup "FUNCTIONAL_SAFETY"
|
|
(
|
|
menuitem "FUNCTIONAL_SAFETY_INST_0" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_0"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_1" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_1"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_2" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_2"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_3" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_3"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_4" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_4"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_5" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_5"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_6" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_6"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_7" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_7"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_8" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_8"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_9" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_9"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_10" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_10"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_11" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_11"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_12" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_12"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_13" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_13"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_14" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_14"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_15" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_15"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_16" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_16"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_17" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_17"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_18" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_18"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_19" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_19"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_20" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_20"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_21" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_21"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_22" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_22"""
|
|
menuitem "FUNCTIONAL_SAFETY_INST_23" "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_23"""
|
|
)
|
|
menuitem "E-FUSE" "per , ""E-FUSE"""
|
|
menuitem "ROM" "per , ""ROM"""
|
|
)
|
|
)
|