; --------------------------------------------------------------------------------
; @Title: RCARS4 Specific Menu
; @Props: Confidential
; @Author: RSA, DAB, PIW, KRZ
; @Changelog: 2022-01-24 RSA
;             2022-03-04 DAB
;             2022-05-20 PIW
;             2023-02-20 KRZ
; @Manufacturer: RENESAS - Renesas Technology, Corp.
; @Core: Cortex-A55, Cortex-R52
; @Chip: RCARS4, RCARS4-CR52
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menrcars4.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXA55")
(
popup "[:chip]Core Registers (Cortex-A55)"
(
menuitem "[:chip]ID Registers[AArch64]"                                                     "per , ""Core Registers (Cortex-A55),AArch64,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch64]"                                 "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration"""
menuitem "[:chip]System Instructions[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,System Control and Configuration,System Instructions"""
menuitem "[:chip]Memory Management Unit[AArch64]"                                           "per , ""Core Registers (Cortex-A55),AArch64,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch64]"                                        "per , ""Core Registers (Cortex-A55),AArch64,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch64]"                                  "per , ""Core Registers (Cortex-A55),AArch64,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch64]"                                       "per , ""Core Registers (Cortex-A55),AArch64,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch64]"                                           "per , ""Core Registers (Cortex-A55),AArch64,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch64]"                    "per , ""Core Registers (Cortex-A55),AArch64,Generic Interrupt Controller System Registers"""
separator
menuitem "[:chip]Debug Registers[AArch64]"                                                  "per , ""Core Registers (Cortex-A55),AArch64,Debug Registers"""
menuitem "[:chip]Activity Monitors Unit[AArch64]"                                           "per , ""AArch64,Activity Monitors Unit"""
separator
menuitem "[:chip]Breakpoint Registers[AArch64]"                                             "per , ""Core Registers (Cortex-A55),AArch64,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch64]"                                             "per , ""Core Registers (Cortex-A55),AArch64,Watchpoint Registers"""
separator
menuitem "[:chip]LORegions Registers[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,LORegions Registers"""
separator
menuitem "[:chip]DynamIQ Shared Unit[AArch64]"                                              "per , ""Core Registers (Cortex-A55),AArch64,DynamIQ Shared Unit"""
separator
menuitem "[:chip]ID Registers[AArch32]"                                                     "per , ""Core Registers (Cortex-A55),AArch32,ID Registers"""
menuitem "[:chip]System Control and Configuration[AArch32]"                                 "per , ""Core Registers (Cortex-A55),AArch32,System Control and Configuration"""
menuitem "[:chip]Memory Management Unit[AArch32]"                                           "per , ""Core Registers (Cortex-A55),AArch32,Memory Management Unit"""
menuitem "[:chip]Virtualization Extensions[AArch32]"                                        "per , ""Core Registers (Cortex-A55),AArch32,Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration[AArch32]"                                  "per , ""Core Registers (Cortex-A55),AArch32,Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor[AArch32]"                                       "per , ""Core Registers (Cortex-A55),AArch32,System Performance Monitor"""
menuitem "[:chip]System Timer Registers[AArch32]"                                           "per , ""Core Registers (Cortex-A55),AArch32,System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller System Registers[AArch32]"                    "per , ""Core Registers (Cortex-A55),AArch32,Generic Interrupt Controller System Registers"""
separator
menuitem "[:chip]Debug Registers[AArch32]"                                                  "per , ""Core Registers (Cortex-A55),AArch32,Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers[AArch32]"                                             "per , ""Core Registers (Cortex-A55),AArch32,Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers[AArch32]"                                             "per , ""Core Registers (Cortex-A55),AArch32,Watchpoint Registers"""
separator
menuitem "[:chip]DynamIQ Shared Unit[AArch32]"                                              "per , ""Core Registers (Cortex-A55),AArch32,DynamIQ Shared Unit"""
separator
menuitem "[:chip]Interrupt Controller"                                                      "per , ""Core Registers (Cortex-A55),Interrupt Controller"""
)
)
if (CORENAME()=="CORTEXR52")
(
popup "[:chip]Core Registers (Cortex-R52)"
(
menuitem "[:chip]ID Registers"                                                    "per , ""Core Registers (Cortex-R52),ID Registers"""
menuitem "[:chip]System Control and Configuration"                                "per , ""Core Registers (Cortex-R52),System Control and Configuration"""
menuitem "[:chip]MPU Control and Configuration"                                   "per , ""Core Registers (Cortex-R52),MPU Control and Configuration"""
menuitem "[:chip]Memory Protection Unit PL1"                                      "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL1"""
menuitem "[:chip]Memory Protection Unit PL2"                                      "per , ""Core Registers (Cortex-R52),Memory Protection Unit PL2"""
menuitem "[:chip]Virtualization Extensions"                                       "per , ""Core Registers (Cortex-R52),Virtualization Extensions"""
menuitem "[:chip]Cache Control and Configuration"                                 "per , ""Core Registers (Cortex-R52),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"                                      "per , ""Core Registers (Cortex-R52),System Performance Monitor"""
menuitem "[:chip]System Timer Registers"                                          "per , ""Core Registers (Cortex-R52),System Timer Registers"""
menuitem "[:chip]Generic Interrupt Controller CPU Interface"                      "per , ""Core Registers (Cortex-R52),Generic Interrupt Controller CPU Interface"""
separator
menuitem "[:chip]Debug Registers"                                                 "per , ""Core Registers (Cortex-R52),Debug Registers"""
separator
menuitem "[:chip]Breakpoint Registers"                                            "per , ""Core Registers (Cortex-R52),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Registers"                                            "per , ""Core Registers (Cortex-R52),Watchpoint Registers"""
)
)
separator
menuitem "REALTIME_CORE"                            "per , ""REALTIME_CORE"""
popup "PFC_GPIO"
(
menuitem "PFC_GPIO_FOR_GP0"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP0"""
menuitem "PFC_GPIO_FOR_GP1"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP1"""
menuitem "PFC_GPIO_FOR_GP2"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP2"""
menuitem "PFC_GPIO_FOR_GP3"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP3"""
menuitem "PFC_GPIO_FOR_GP4"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP4"""
menuitem "PFC_GPIO_FOR_GP5"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP5"""
menuitem "PFC_GPIO_FOR_GP6"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP6"""
menuitem "PFC_GPIO_FOR_GP7"                     "per , ""PFC_GPIO,PFC_GPIO_FOR_GP7"""
menuitem "PFC_GPIO_FOR_SYS0"                    "per , ""PFC_GPIO,PFC_GPIO_FOR_SYS0"""
menuitem "PFC_GPIO_FOR_SYS1"                    "per , ""PFC_GPIO,PFC_GPIO_FOR_SYS1"""
)
popup "CLOCK_PULSE_GENERATOR"
(
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_0"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_0"""
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_1"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_1"""
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_2"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_2"""
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_3"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_3"""
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_4"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_4"""
menuitem "CLOCK_PULSE_GENERATOR_CPG_INST_5"     "per , ""CLOCK_PULSE_GENERATOR,CLOCK_PULSE_GENERATOR_CPG_INST_5"""
)
menuitem "MODULE_STANDBY_SOFTWARE_RESET"            "per , ""MODULE_STANDBY_SOFTWARE_RESET"""
popup "APMU"
(
menuitem "APMU_INST_0"                          "per , ""APMU,APMU_INST_0"""
menuitem "APMU_INST_1"                          "per , ""APMU,APMU_INST_1"""
menuitem "APMU_INST_2"                          "per , ""APMU,APMU_INST_2"""
menuitem "APMU_INST_3"                          "per , ""APMU,APMU_INST_3"""
)
popup "SYSC"
(
menuitem "SYSC_INST_0"                          "per , ""SYSC,SYSC_INST_0"""
menuitem "SYSC_INST_1"                          "per , ""SYSC,SYSC_INST_1"""
menuitem "SYSC_INST_2"                          "per , ""SYSC,SYSC_INST_2"""
menuitem "SYSC_INST_3"                          "per , ""SYSC,SYSC_INST_3"""
)
popup "THS"
(
menuitem "THS_INST_0"                           "per , ""THS,THS_INST_0"""
menuitem "THS_INST_1"                           "per , ""THS,THS_INST_1"""
menuitem "THS_INST_2"                           "per , ""THS,THS_INST_2"""
menuitem "THS_INST_3"                           "per , ""THS,THS_INST_3"""
)
popup "RESET_RST"
(
menuitem "RESET_RST_INST_0"                     "per , ""RESET_RST,RESET_RST_INST_0"""
menuitem "RESET_RST_INST_1"                     "per , ""RESET_RST,RESET_RST_INST_1"""
menuitem "RESET_RST_INST_2"                     "per , ""RESET_RST,RESET_RST_INST_2"""
menuitem "RESET_RST_INST_3"                     "per , ""RESET_RST,RESET_RST_INST_3"""
)
popup "INTC"
(
menuitem "INTC_INST_0"                          "per , ""INTC,INTC_INST_0"""
menuitem "INTC_INST_1"                          "per , ""INTC,INTC_INST_1"""
menuitem "INTC_INST_2"                          "per , ""INTC,INTC_INST_2"""
menuitem "INTC_INST_3"                          "per , ""INTC,INTC_INST_3"""
menuitem "INTC_INST_4"                          "per , ""INTC,INTC_INST_4"""
menuitem "INTC_INST_5"                          "per , ""INTC,INTC_INST_5"""
)
popup "MFIS"
(
menuitem "MFIS_INST_0"                          "per , ""MFIS,MFIS_INST_0"""
menuitem "MFIS_INST_1"                          "per , ""MFIS,MFIS_INST_1"""
)
menuitem "ECM"                                      "per , ""ECM"""
popup "AXI_BUS"
(
menuitem "AXI_BUS_INST_0"                       "per , ""AXI_BUS,AXI_BUS_INST_0"""
menuitem "AXI_BUS_INST_1"                       "per , ""AXI_BUS,AXI_BUS_INST_1"""
menuitem "AXI_BUS_INST_2"                       "per , ""AXI_BUS,AXI_BUS_INST_2"""
menuitem "AXI_BUS_INST_3"                       "per , ""AXI_BUS,AXI_BUS_INST_3"""
)
popup "IPMMU"
(
menuitem "IPMMU_INST_0"                         "per , ""IPMMU,IPMMU_INST_0"""
menuitem "IPMMU_INST_1"                         "per , ""IPMMU,IPMMU_INST_1"""
)
popup "DMAC"
(
menuitem "DMAC_INST_0"                          "per , ""DMAC,DMAC_INST_0"""
menuitem "DMAC_INST_1"                          "per , ""DMAC,DMAC_INST_1"""
menuitem "DMAC_INST_2"                          "per , ""DMAC,DMAC_INST_2"""
menuitem "DMAC_INST_3"                          "per , ""DMAC,DMAC_INST_3"""
menuitem "DMAC_INST_4"                          "per , ""DMAC,DMAC_INST_4"""
menuitem "DMAC_INST_5"                          "per , ""DMAC,DMAC_INST_5"""
menuitem "DMAC_INST_6"                          "per , ""DMAC,DMAC_INST_6"""
menuitem "DMAC_INST_7"                          "per , ""DMAC,DMAC_INST_7"""
menuitem "DMAC_INST_8"                          "per , ""DMAC,DMAC_INST_8"""
menuitem "DMAC_INST_9"                          "per , ""DMAC,DMAC_INST_9"""
menuitem "DMAC_INST_10"                         "per , ""DMAC,DMAC_INST_10"""
menuitem "DMAC_INST_11"                         "per , ""DMAC,DMAC_INST_11"""
)
menuitem "DBSC4"                                    "per , ""DBSC4"""
menuitem "RT_SRAM"                                  "per , ""RT_SRAM"""
menuitem "RT_VRAM"                                  "per , ""RT_VRAM"""
popup "GWCA"
(
menuitem "GWCA_INST_0"                          "per , ""GWCA,GWCA_INST_0"""
menuitem "GWCA_INST_1"                          "per , ""GWCA,GWCA_INST_1"""
)
menuitem "R_SWITCH_2"                               "per , ""R_SWITCH_2"""
menuitem "ETHERNET_SWITCH_SRAM"                     "per , ""ETHERNET_SWITCH_SRAM"""
menuitem "ETHERNET_SERDES_SRAM"                     "per , ""ETHERNET_SERDES_SRAM"""
popup "SCIF"
(
menuitem "SCIF_INST_0"                          "per , ""SCIF,SCIF_INST_0"""
menuitem "SCIF_INST_1"                          "per , ""SCIF,SCIF_INST_1"""
menuitem "SCIF_INST_2"                          "per , ""SCIF,SCIF_INST_2"""
menuitem "SCIF_INST_3"                          "per , ""SCIF,SCIF_INST_3"""
)
popup "HSCIF"
(
menuitem "HSCIF_INST_0"                         "per , ""HSCIF,HSCIF_INST_0"""
menuitem "HSCIF_INST_1"                         "per , ""HSCIF,HSCIF_INST_1"""
menuitem "HSCIF_INST_2"                         "per , ""HSCIF,HSCIF_INST_2"""
menuitem "HSCIF_INST_3"                         "per , ""HSCIF,HSCIF_INST_3"""
)
popup "I2C"
(
menuitem "I2C_INST_0"                           "per , ""I2C,I2C_INST_0"""
menuitem "I2C_INST_1"                           "per , ""I2C,I2C_INST_1"""
menuitem "I2C_INST_2"                           "per , ""I2C,I2C_INST_2"""
menuitem "I2C_INST_3"                           "per , ""I2C,I2C_INST_3"""
menuitem "I2C_INST_4"                           "per , ""I2C,I2C_INST_4"""
menuitem "I2C_INST_5"                           "per , ""I2C,I2C_INST_5"""
)
popup "MSIOF"
(
menuitem "MSIOF_INST_0"                         "per , ""MSIOF,MSIOF_INST_0"""
menuitem "MSIOF_INST_1"                         "per , ""MSIOF,MSIOF_INST_1"""
menuitem "MSIOF_INST_2"                         "per , ""MSIOF,MSIOF_INST_2"""
menuitem "MSIOF_INST_3"                         "per , ""MSIOF,MSIOF_INST_3"""
)
menuitem "RPC"                                      "per , ""RPC"""
menuitem "LIFEC"                                    "per , ""LIFEC"""
popup "CRC"
(
menuitem "CRC_INST_0"                           "per , ""CRC,CRC_INST_0"""
menuitem "CRC_INST_1"                           "per , ""CRC,CRC_INST_1"""
menuitem "CRC_INST_2"                           "per , ""CRC,CRC_INST_2"""
menuitem "CRC_INST_3"                           "per , ""CRC,CRC_INST_3"""
menuitem "CRC_INST_4"                           "per , ""CRC,CRC_INST_4"""
menuitem "CRC_INST_5"                           "per , ""CRC,CRC_INST_5"""
menuitem "CRC_INST_6"                           "per , ""CRC,CRC_INST_6"""
menuitem "CRC_INST_7"                           "per , ""CRC,CRC_INST_7"""
menuitem "CRC_INST_8"                           "per , ""CRC,CRC_INST_8"""
menuitem "CRC_INST_9"                           "per , ""CRC,CRC_INST_9"""
menuitem "CRC_INST_10"                          "per , ""CRC,CRC_INST_10"""
menuitem "CRC_INST_11"                          "per , ""CRC,CRC_INST_11"""
)
popup "RFSO"
(
menuitem "RFSO_INST_0"                          "per , ""RFSO,RFSO_INST_0"""
menuitem "RFSO_INST_1"                          "per , ""RFSO,RFSO_INST_1"""
menuitem "RFSO_INST_2"                          "per , ""RFSO,RFSO_INST_2"""
menuitem "RFSO_INST_3"                          "per , ""RFSO,RFSO_INST_3"""
menuitem "RFSO_INST_4"                          "per , ""RFSO,RFSO_INST_4"""
menuitem "RFSO_INST_5"                          "per , ""RFSO,RFSO_INST_5"""
menuitem "RFSO_INST_6"                          "per , ""RFSO,RFSO_INST_6"""
menuitem "RFSO_INST_7"                          "per , ""RFSO,RFSO_INST_7"""
menuitem "RFSO_INST_8"                          "per , ""RFSO,RFSO_INST_8"""
menuitem "RFSO_INST_9"                          "per , ""RFSO,RFSO_INST_9"""
menuitem "RFSO_INST_10"                         "per , ""RFSO,RFSO_INST_10"""
)
popup "SDHI_MMC"
(
menuitem "SDHI_MMC_INST_0"                      "per , ""SDHI_MMC,SDHI_MMC_INST_0"""
menuitem "SDHI_MMC_INST_1"                      "per , ""SDHI_MMC,SDHI_MMC_INST_1"""
)
menuitem "UFS"                                      "per , ""UFS"""
menuitem "RWDT"                                     "per , ""RWDT"""
popup "WWDT"
(
menuitem "WWDT_INST_0"                          "per , ""WWDT,WWDT_INST_0"""
menuitem "WWDT_INST_1"                          "per , ""WWDT,WWDT_INST_1"""
menuitem "WWDT_INST_2"                          "per , ""WWDT,WWDT_INST_2"""
menuitem "WWDT_INST_3"                          "per , ""WWDT,WWDT_INST_3"""
menuitem "WWDT_INST_4"                          "per , ""WWDT,WWDT_INST_4"""
menuitem "WWDT_INST_5"                          "per , ""WWDT,WWDT_INST_5"""
menuitem "WWDT_INST_6"                          "per , ""WWDT,WWDT_INST_6"""
menuitem "WWDT_INST_7"                          "per , ""WWDT,WWDT_INST_7"""
menuitem "WWDT_INST_8"                          "per , ""WWDT,WWDT_INST_8"""
menuitem "WWDT_INST_9"                          "per , ""WWDT,WWDT_INST_9"""
)
menuitem "SWDT"                                     "per , ""SWDT"""
menuitem "CMT0"                                     "per , ""CMT0"""
popup "CMT1"
(
menuitem "CMT1_INST_0"                          "per , ""CMT1,CMT1_INST_0"""
menuitem "CMT1_INST_1"                          "per , ""CMT1,CMT1_INST_1"""
menuitem "CMT1_INST_2"                          "per , ""CMT1,CMT1_INST_2"""
)
popup "TMU"
(
menuitem "TMU_INST_0"                           "per , ""TMU,TMU_INST_0"""
menuitem "TMU_INST_1"                           "per , ""TMU,TMU_INST_1"""
menuitem "TMU_INST_2"                           "per , ""TMU,TMU_INST_2"""
menuitem "TMU_INST_3"                           "per , ""TMU,TMU_INST_3"""
menuitem "TMU_INST_4"                           "per , ""TMU,TMU_INST_4"""
)
menuitem "SCMT"                                     "per , ""SCMT"""
menuitem "SUCMT"                                    "per , ""SUCMT"""
menuitem "HSSTP_CPU"                                "per , ""HSSTP_CPU"""
menuitem "HSSTP_DEBUGGER"                           "per , ""HSSTP_DEBUGGER"""
popup "DEBUG_AND_TRACE_CPU"
(
menuitem "DEBUG_AND_TRACE_CPU_INST_0"           "per , ""DEBUG_AND_TRACE_CPU,DEBUG_AND_TRACE_CPU_INST_0"""
menuitem "DEBUG_AND_TRACE_CPU_INST_1"           "per , ""DEBUG_AND_TRACE_CPU,DEBUG_AND_TRACE_CPU_INST_1"""
)
popup "FUNCTIONAL_SAFETY"
(
menuitem "FUNCTIONAL_SAFETY_INST_0"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_0"""
menuitem "FUNCTIONAL_SAFETY_INST_1"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_1"""
menuitem "FUNCTIONAL_SAFETY_INST_2"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_2"""
menuitem "FUNCTIONAL_SAFETY_INST_3"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_3"""
menuitem "FUNCTIONAL_SAFETY_INST_4"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_4"""
menuitem "FUNCTIONAL_SAFETY_INST_5"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_5"""
menuitem "FUNCTIONAL_SAFETY_INST_6"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_6"""
menuitem "FUNCTIONAL_SAFETY_INST_7"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_7"""
menuitem "FUNCTIONAL_SAFETY_INST_8"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_8"""
menuitem "FUNCTIONAL_SAFETY_INST_9"             "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_9"""
menuitem "FUNCTIONAL_SAFETY_INST_10"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_10"""
menuitem "FUNCTIONAL_SAFETY_INST_11"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_11"""
menuitem "FUNCTIONAL_SAFETY_INST_12"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_12"""
menuitem "FUNCTIONAL_SAFETY_INST_13"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_13"""
menuitem "FUNCTIONAL_SAFETY_INST_14"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_14"""
menuitem "FUNCTIONAL_SAFETY_INST_15"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_15"""
menuitem "FUNCTIONAL_SAFETY_INST_16"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_16"""
menuitem "FUNCTIONAL_SAFETY_INST_17"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_17"""
menuitem "FUNCTIONAL_SAFETY_INST_18"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_18"""
menuitem "FUNCTIONAL_SAFETY_INST_19"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_19"""
menuitem "FUNCTIONAL_SAFETY_INST_20"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_20"""
menuitem "FUNCTIONAL_SAFETY_INST_21"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_21"""
menuitem "FUNCTIONAL_SAFETY_INST_22"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_22"""
menuitem "FUNCTIONAL_SAFETY_INST_23"            "per , ""FUNCTIONAL_SAFETY,FUNCTIONAL_SAFETY_INST_23"""
)
menuitem "E-FUSE"                                   "per , ""E-FUSE"""
menuitem "ROM"                                      "per , ""ROM"""
)
)