433 lines
15 KiB
Plaintext
433 lines
15 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: netX4000app Specific Menu
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; @Props: Released
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; @Author: KOL, KRZ
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; @Changelog: 2019-12-30 KOL
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; 2022-02-03 KRZ
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; @Manufacturer: HILSCHER - Hilscher GmbH
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; @Core: Cortex-A9
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; @Chip: NETX4000-APP
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; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R)
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; $Id: mennetx4000app.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A9MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
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menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
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menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
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menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
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menuitem "[:chip]Interrupt Controller (GIC-400)" "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (GIC-400)"""
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)
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separator
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menuitem "ASIC_CTRL" "per , ""ASIC_CTRL"""
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menuitem "ECC_CTRL" "per , ""ECC_CTRL"""
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menuitem "DPM" "per , ""DPM"""
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popup "IDPM"
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(
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menuitem "IDPM0" "per , ""IDPM,IDPM0"""
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menuitem "IDPM1" "per , ""IDPM,IDPM1"""
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)
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popup "HANDSHAKE_CTRL"
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(
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menuitem "HANDSHAKE_CTRL0" "per , ""HANDSHAKE_CTRL,HANDSHAKE_CTRL0"""
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menuitem "HANDSHAKE_CTRL1" "per , ""HANDSHAKE_CTRL,HANDSHAKE_CTRL1"""
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)
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popup "CA9_MULTI_CPU_PING_IRQ"
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(
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menuitem "CA9_MULTI_CPU_PING_IRQ0" "per , ""CA9_MULTI_CPU_PING_IRQ,CA9_MULTI_CPU_PING_IRQ0"""
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menuitem "CA9_MULTI_CPU_PING_IRQ1" "per , ""CA9_MULTI_CPU_PING_IRQ,CA9_MULTI_CPU_PING_IRQ1"""
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)
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menuitem "SYSTIME_RAP" "per , ""SYSTIME_RAP"""
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popup "ADC_CTRL"
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(
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menuitem "ADC_CTRL0" "per , ""ADC_CTRL,ADC_CTRL0"""
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menuitem "ADC_CTRL1" "per , ""ADC_CTRL,ADC_CTRL1"""
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)
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popup "INTLOGIC_SYSTIME_LT"
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(
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menuitem "INTLOGIC_SYSTIME_LT0" "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT0"""
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menuitem "INTLOGIC_SYSTIME_LT1" "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT1"""
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menuitem "INTLOGIC_SYSTIME_LT2" "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT2"""
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)
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menuitem "ARM_TIMER" "per , ""ARM_TIMER"""
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menuitem "XPIC0_DRAM" "per , ""XPIC0_DRAM"""
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menuitem "XPIC1_DRAM" "per , ""XPIC1_DRAM"""
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menuitem "XPIC2_DRAM" "per , ""XPIC2_DRAM"""
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menuitem "XPIC3_DRAM" "per , ""XPIC3_DRAM"""
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menuitem "XPIC0_PRAM" "per , ""XPIC0_PRAM"""
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menuitem "XPIC1_PRAM" "per , ""XPIC1_PRAM"""
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menuitem "XPIC2_PRAM" "per , ""XPIC2_PRAM"""
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menuitem "XPIC3_PRAM" "per , ""XPIC3_PRAM"""
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menuitem "XPIC0_REGS" "per , ""XPIC0_REGS"""
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menuitem "XPIC0_DEBUG" "per , ""XPIC0_DEBUG"""
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menuitem "XPIC1_REGS" "per , ""XPIC1_REGS"""
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menuitem "XPIC1_DEBUG" "per , ""XPIC1_DEBUG"""
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menuitem "XPIC2_REGS" "per , ""XPIC2_REGS"""
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menuitem "XPIC2_DEBUG" "per , ""XPIC2_DEBUG"""
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menuitem "XPIC3_REGS" "per , ""XPIC3_REGS"""
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menuitem "XPIC3_DEBUG" "per , ""XPIC3_DEBUG"""
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menuitem "XPIC_VIC0" "per , ""XPIC_VIC0"""
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menuitem "XPIC_TIMER0" "per , ""XPIC_TIMER0"""
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menuitem "XPIC_WDG0" "per , ""XPIC_WDG0"""
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menuitem "XPIC_MULTI_CPU_PING_IRQ0" "per , ""XPIC_MULTI_CPU_PING_IRQ0"""
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menuitem "XPIC_SYSTIME_LT0" "per , ""XPIC_SYSTIME_LT0"""
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menuitem "SIGMA_DELTA_TRIGGER" "per , ""SIGMA_DELTA_TRIGGER"""
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menuitem "ADC_CTRL0_MOTION" "per , ""ADC_CTRL0_MOTION"""
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menuitem "ADC_CTRL1_MOTION" "per , ""ADC_CTRL1_MOTION"""
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menuitem "XPIC_VIC1" "per , ""XPIC_VIC1"""
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menuitem "XPIC_TIMER1" "per , ""XPIC_TIMER1"""
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menuitem "XPIC_WDG1" "per , ""XPIC_WDG1"""
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menuitem "XPIC_MULTI_CPU_PING_IRQ1" "per , ""XPIC_MULTI_CPU_PING_IRQ1"""
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menuitem "XPIC_SYSTIME_LT1" "per , ""XPIC_SYSTIME_LT1"""
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menuitem "XPIC_VIC2" "per , ""XPIC_VIC2"""
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menuitem "XPIC_TIMER2" "per , ""XPIC_TIMER2"""
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menuitem "XPIC_WDG2" "per , ""XPIC_WDG2"""
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menuitem "XPIC_MULTI_CPU_PING_IRQ2" "per , ""XPIC_MULTI_CPU_PING_IRQ2"""
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menuitem "XPIC_SYSTIME_LT2" "per , ""XPIC_SYSTIME_LT2"""
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menuitem "XPIC_VIC3" "per , ""XPIC_VIC3"""
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menuitem "XPIC_TIMER3" "per , ""XPIC_TIMER3"""
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menuitem "XPIC_WDG3" "per , ""XPIC_WDG3"""
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menuitem "XPIC_MULTI_CPU_PING_IRQ3" "per , ""XPIC_MULTI_CPU_PING_IRQ3"""
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menuitem "XPIC_SYSTIME_LT3" "per , ""XPIC_SYSTIME_LT3"""
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menuitem "RAP_SYSCTRL" "per , ""RAP_SYSCTRL"""
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menuitem "DDR_CTRL" "per , ""DDR_CTRL"""
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menuitem "DDR_PHY" "per , ""DDR_PHY"""
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menuitem "PL353" "per , ""PL353"""
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menuitem "USB_FUNC" "per , ""USB_FUNC"""
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popup "GMAC"
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(
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menuitem "GMAC0" "per , ""GMAC,GMAC0"""
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menuitem "GMAC1" "per , ""GMAC,GMAC1"""
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)
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popup "RAP_DMAC0_CH"
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(
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menuitem "RAP_DMAC0_CH0" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH0"""
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menuitem "RAP_DMAC0_CH1" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH1"""
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menuitem "RAP_DMAC0_CH2" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH2"""
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menuitem "RAP_DMAC0_CH3" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH3"""
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menuitem "RAP_DMAC0_CH4" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH4"""
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menuitem "RAP_DMAC0_CH5" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH5"""
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menuitem "RAP_DMAC0_CH6" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH6"""
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menuitem "RAP_DMAC0_CH7" "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH7"""
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)
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menuitem "RAP_DMAC0_REG" "per , ""RAP_DMAC0_REG"""
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popup "RAP_DMAC1_CH"
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(
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menuitem "RAP_DMAC1_CH0" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH0"""
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menuitem "RAP_DMAC1_CH1" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH1"""
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menuitem "RAP_DMAC1_CH2" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH2"""
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menuitem "RAP_DMAC1_CH3" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH3"""
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menuitem "RAP_DMAC1_CH4" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH4"""
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menuitem "RAP_DMAC1_CH5" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH5"""
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menuitem "RAP_DMAC1_CH6" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH6"""
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menuitem "RAP_DMAC1_CH7" "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH7"""
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)
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menuitem "RAP_DMAC1_REG" "per , ""RAP_DMAC1_REG"""
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popup "RAP_I2C"
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(
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menuitem "RAP_I2C0" "per , ""RAP_I2C,RAP_I2C0"""
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menuitem "RAP_I2C1" "per , ""RAP_I2C,RAP_I2C1"""
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menuitem "RAP_I2C2" "per , ""RAP_I2C,RAP_I2C2"""
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menuitem "RAP_I2C3" "per , ""RAP_I2C,RAP_I2C3"""
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menuitem "RAP_I2C4" "per , ""RAP_I2C,RAP_I2C4"""
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menuitem "RAP_I2C5" "per , ""RAP_I2C,RAP_I2C5"""
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)
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popup "IIS"
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(
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menuitem "IIS0" "per , ""IIS,IIS0"""
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menuitem "IIS1" "per , ""IIS,IIS1"""
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menuitem "IIS2" "per , ""IIS,IIS2"""
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)
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menuitem "IISCLK_CTL" "per , ""IISCLK_CTL"""
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menuitem "RTC" "per , ""RTC"""
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popup "RAP_ECC_CTRL"
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(
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menuitem "RAP_ECC_CTRL0" "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL0"""
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menuitem "RAP_ECC_CTRL1" "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL1"""
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menuitem "RAP_ECC_CTRL2" "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL2"""
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)
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menuitem "SQI1" "per , ""SQI1"""
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menuitem "SIGMA_DELTA" "per , ""SIGMA_DELTA"""
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popup "RAP_GPIO"
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(
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menuitem "RAP_GPIO0" "per , ""RAP_GPIO,RAP_GPIO0"""
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menuitem "RAP_GPIO1" "per , ""RAP_GPIO,RAP_GPIO1"""
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menuitem "RAP_GPIO2" "per , ""RAP_GPIO,RAP_GPIO2"""
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menuitem "RAP_GPIO3" "per , ""RAP_GPIO,RAP_GPIO3"""
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menuitem "RAP_GPIO4" "per , ""RAP_GPIO,RAP_GPIO4"""
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)
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menuitem "RSCAN" "per , ""RSCAN"""
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popup "SSP"
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(
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menuitem "SSP0" "per , ""SSP,SSP0"""
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menuitem "SSP1" "per , ""SSP,SSP1"""
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)
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popup "RAP_UART"
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(
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menuitem "RAP_UART0" "per , ""RAP_UART,RAP_UART0"""
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menuitem "RAP_UART1" "per , ""RAP_UART,RAP_UART1"""
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menuitem "RAP_UART2" "per , ""RAP_UART,RAP_UART2"""
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menuitem "RAP_UART3" "per , ""RAP_UART,RAP_UART3"""
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)
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menuitem "SDIO" "per , ""SDIO"""
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|
menuitem "PVO" "per , ""PVO"""
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|
menuitem "DAVEHD" "per , ""DAVEHD"""
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menuitem "SWITCH_3P" "per , ""SWITCH_3P"""
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|
menuitem "PCIE" "per , ""PCIE"""
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|
menuitem "USB_HOST" "per , ""USB_HOST"""
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menuitem "INTRAMHS0_DPM_MIRROR_P" "per , ""INTRAMHS0_DPM_MIRROR_P"""
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menuitem "INTRAMHS1_DPM_MIRROR_P" "per , ""INTRAMHS1_DPM_MIRROR_P"""
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menuitem "NOC" "per , ""NOC"""
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)
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)
|