; --------------------------------------------------------------------------------
; @Title: netX4000app Specific Menu
; @Props: Released
; @Author: KOL, KRZ
; @Changelog: 2019-12-30 KOL
;             2022-02-03 KRZ
; @Manufacturer: HILSCHER - Hilscher GmbH
; @Core: Cortex-A9
; @Chip: NETX4000-APP
; @Copyright: (C) 1989-2021 Lauterbach GmbH, licensed for use with TRACE32(R)
; $Id: mennetx4000app.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A9MPCore)"
(
menuitem "[:chip]ID Registers"                        "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"    "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"              "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
menuitem "[:chip]Cache Control and Configuration"     "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"          "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
menuitem "[:chip]Preload Engine"                      "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
menuitem "[:chip]NEON"                                "per , ""Core Registers (Cortex-A9MPCore),NEON"""
separator
menuitem "[:chip]Debug Registers"                     "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"                "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"        "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Snoop Control Unit (SCU)"            "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
menuitem "[:chip]Timer and Watchdog Blocks"           "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
menuitem "[:chip]Interrupt Controller (GIC-400)"       "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (GIC-400)"""
)
separator
menuitem "ASIC_CTRL"                        "per , ""ASIC_CTRL"""
menuitem "ECC_CTRL"                         "per , ""ECC_CTRL"""
menuitem "DPM"                              "per , ""DPM"""
popup "IDPM"
(
menuitem "IDPM0"                        "per , ""IDPM,IDPM0"""
menuitem "IDPM1"                        "per , ""IDPM,IDPM1"""
)
popup "HANDSHAKE_CTRL"
(
menuitem "HANDSHAKE_CTRL0"              "per , ""HANDSHAKE_CTRL,HANDSHAKE_CTRL0"""
menuitem "HANDSHAKE_CTRL1"              "per , ""HANDSHAKE_CTRL,HANDSHAKE_CTRL1"""
)
popup "CA9_MULTI_CPU_PING_IRQ"
(
menuitem "CA9_MULTI_CPU_PING_IRQ0"      "per , ""CA9_MULTI_CPU_PING_IRQ,CA9_MULTI_CPU_PING_IRQ0"""
menuitem "CA9_MULTI_CPU_PING_IRQ1"      "per , ""CA9_MULTI_CPU_PING_IRQ,CA9_MULTI_CPU_PING_IRQ1"""
)
menuitem "SYSTIME_RAP"                      "per , ""SYSTIME_RAP"""
popup "ADC_CTRL"
(
menuitem "ADC_CTRL0"                    "per , ""ADC_CTRL,ADC_CTRL0"""
menuitem "ADC_CTRL1"                    "per , ""ADC_CTRL,ADC_CTRL1"""
)
popup "INTLOGIC_SYSTIME_LT"
(
menuitem "INTLOGIC_SYSTIME_LT0"         "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT0"""
menuitem "INTLOGIC_SYSTIME_LT1"         "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT1"""
menuitem "INTLOGIC_SYSTIME_LT2"         "per , ""INTLOGIC_SYSTIME_LT,INTLOGIC_SYSTIME_LT2"""
)
menuitem "ARM_TIMER"                        "per , ""ARM_TIMER"""
menuitem "XPIC0_DRAM"                       "per , ""XPIC0_DRAM"""
menuitem "XPIC1_DRAM"                       "per , ""XPIC1_DRAM"""
menuitem "XPIC2_DRAM"                       "per , ""XPIC2_DRAM"""
menuitem "XPIC3_DRAM"                       "per , ""XPIC3_DRAM"""
menuitem "XPIC0_PRAM"                       "per , ""XPIC0_PRAM"""
menuitem "XPIC1_PRAM"                       "per , ""XPIC1_PRAM"""
menuitem "XPIC2_PRAM"                       "per , ""XPIC2_PRAM"""
menuitem "XPIC3_PRAM"                       "per , ""XPIC3_PRAM"""
menuitem "XPIC0_REGS"                       "per , ""XPIC0_REGS"""
menuitem "XPIC0_DEBUG"                      "per , ""XPIC0_DEBUG"""
menuitem "XPIC1_REGS"                       "per , ""XPIC1_REGS"""
menuitem "XPIC1_DEBUG"                      "per , ""XPIC1_DEBUG"""
menuitem "XPIC2_REGS"                       "per , ""XPIC2_REGS"""
menuitem "XPIC2_DEBUG"                      "per , ""XPIC2_DEBUG"""
menuitem "XPIC3_REGS"                       "per , ""XPIC3_REGS"""
menuitem "XPIC3_DEBUG"                      "per , ""XPIC3_DEBUG"""
menuitem "XPIC_VIC0"                        "per , ""XPIC_VIC0"""
menuitem "XPIC_TIMER0"                      "per , ""XPIC_TIMER0"""
menuitem "XPIC_WDG0"                        "per , ""XPIC_WDG0"""
menuitem "XPIC_MULTI_CPU_PING_IRQ0"         "per , ""XPIC_MULTI_CPU_PING_IRQ0"""
menuitem "XPIC_SYSTIME_LT0"                 "per , ""XPIC_SYSTIME_LT0"""
menuitem "SIGMA_DELTA_TRIGGER"              "per , ""SIGMA_DELTA_TRIGGER"""
menuitem "ADC_CTRL0_MOTION"                 "per , ""ADC_CTRL0_MOTION"""
menuitem "ADC_CTRL1_MOTION"                 "per , ""ADC_CTRL1_MOTION"""
menuitem "XPIC_VIC1"                        "per , ""XPIC_VIC1"""
menuitem "XPIC_TIMER1"                      "per , ""XPIC_TIMER1"""
menuitem "XPIC_WDG1"                        "per , ""XPIC_WDG1"""
menuitem "XPIC_MULTI_CPU_PING_IRQ1"         "per , ""XPIC_MULTI_CPU_PING_IRQ1"""
menuitem "XPIC_SYSTIME_LT1"                 "per , ""XPIC_SYSTIME_LT1"""
menuitem "XPIC_VIC2"                        "per , ""XPIC_VIC2"""
menuitem "XPIC_TIMER2"                      "per , ""XPIC_TIMER2"""
menuitem "XPIC_WDG2"                        "per , ""XPIC_WDG2"""
menuitem "XPIC_MULTI_CPU_PING_IRQ2"         "per , ""XPIC_MULTI_CPU_PING_IRQ2"""
menuitem "XPIC_SYSTIME_LT2"                 "per , ""XPIC_SYSTIME_LT2"""
menuitem "XPIC_VIC3"                        "per , ""XPIC_VIC3"""
menuitem "XPIC_TIMER3"                      "per , ""XPIC_TIMER3"""
menuitem "XPIC_WDG3"                        "per , ""XPIC_WDG3"""
menuitem "XPIC_MULTI_CPU_PING_IRQ3"         "per , ""XPIC_MULTI_CPU_PING_IRQ3"""
menuitem "XPIC_SYSTIME_LT3"                 "per , ""XPIC_SYSTIME_LT3"""
menuitem "RAP_SYSCTRL"                      "per , ""RAP_SYSCTRL"""
menuitem "DDR_CTRL"                         "per , ""DDR_CTRL"""
menuitem "DDR_PHY"                          "per , ""DDR_PHY"""
menuitem "PL353"                            "per , ""PL353"""
menuitem "USB_FUNC"                         "per , ""USB_FUNC"""
popup "GMAC"
(
menuitem "GMAC0"                        "per , ""GMAC,GMAC0"""
menuitem "GMAC1"                        "per , ""GMAC,GMAC1"""
)
popup "RAP_DMAC0_CH"
(
menuitem "RAP_DMAC0_CH0"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH0"""
menuitem "RAP_DMAC0_CH1"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH1"""
menuitem "RAP_DMAC0_CH2"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH2"""
menuitem "RAP_DMAC0_CH3"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH3"""
menuitem "RAP_DMAC0_CH4"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH4"""
menuitem "RAP_DMAC0_CH5"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH5"""
menuitem "RAP_DMAC0_CH6"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH6"""
menuitem "RAP_DMAC0_CH7"                "per , ""RAP_DMAC0_CH,RAP_DMAC0_CH7"""
)
menuitem "RAP_DMAC0_REG"                    "per , ""RAP_DMAC0_REG"""
popup "RAP_DMAC1_CH"
(
menuitem "RAP_DMAC1_CH0"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH0"""
menuitem "RAP_DMAC1_CH1"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH1"""
menuitem "RAP_DMAC1_CH2"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH2"""
menuitem "RAP_DMAC1_CH3"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH3"""
menuitem "RAP_DMAC1_CH4"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH4"""
menuitem "RAP_DMAC1_CH5"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH5"""
menuitem "RAP_DMAC1_CH6"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH6"""
menuitem "RAP_DMAC1_CH7"                "per , ""RAP_DMAC1_CH,RAP_DMAC1_CH7"""
)
menuitem "RAP_DMAC1_REG"                    "per , ""RAP_DMAC1_REG"""
popup "RAP_I2C"
(
menuitem "RAP_I2C0"                     "per , ""RAP_I2C,RAP_I2C0"""
menuitem "RAP_I2C1"                     "per , ""RAP_I2C,RAP_I2C1"""
menuitem "RAP_I2C2"                     "per , ""RAP_I2C,RAP_I2C2"""
menuitem "RAP_I2C3"                     "per , ""RAP_I2C,RAP_I2C3"""
menuitem "RAP_I2C4"                     "per , ""RAP_I2C,RAP_I2C4"""
menuitem "RAP_I2C5"                     "per , ""RAP_I2C,RAP_I2C5"""
)
popup "IIS"
(
menuitem "IIS0"                         "per , ""IIS,IIS0"""
menuitem "IIS1"                         "per , ""IIS,IIS1"""
menuitem "IIS2"                         "per , ""IIS,IIS2"""
)
menuitem "IISCLK_CTL"                       "per , ""IISCLK_CTL"""
menuitem "RTC"                              "per , ""RTC"""
popup "RAP_ECC_CTRL"
(
menuitem "RAP_ECC_CTRL0"                "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL0"""
menuitem "RAP_ECC_CTRL1"                "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL1"""
menuitem "RAP_ECC_CTRL2"                "per , ""RAP_ECC_CTRL,RAP_ECC_CTRL2"""
)
menuitem "SQI1"                             "per , ""SQI1"""
menuitem "SIGMA_DELTA"                      "per , ""SIGMA_DELTA"""
popup "RAP_GPIO"
(
menuitem "RAP_GPIO0"                    "per , ""RAP_GPIO,RAP_GPIO0"""
menuitem "RAP_GPIO1"                    "per , ""RAP_GPIO,RAP_GPIO1"""
menuitem "RAP_GPIO2"                    "per , ""RAP_GPIO,RAP_GPIO2"""
menuitem "RAP_GPIO3"                    "per , ""RAP_GPIO,RAP_GPIO3"""
menuitem "RAP_GPIO4"                    "per , ""RAP_GPIO,RAP_GPIO4"""
)
menuitem "RSCAN"                            "per , ""RSCAN"""
popup "SSP"
(
menuitem "SSP0"                         "per , ""SSP,SSP0"""
menuitem "SSP1"                         "per , ""SSP,SSP1"""
)
popup "RAP_UART"
(
menuitem "RAP_UART0"                    "per , ""RAP_UART,RAP_UART0"""
menuitem "RAP_UART1"                    "per , ""RAP_UART,RAP_UART1"""
menuitem "RAP_UART2"                    "per , ""RAP_UART,RAP_UART2"""
menuitem "RAP_UART3"                    "per , ""RAP_UART,RAP_UART3"""
)
menuitem "SDIO"                             "per , ""SDIO"""
menuitem "PVO"                              "per , ""PVO"""
menuitem "DAVEHD"                           "per , ""DAVEHD"""
menuitem "SWITCH_3P"                        "per , ""SWITCH_3P"""
menuitem "PCIE"                             "per , ""PCIE"""
menuitem "USB_HOST"                         "per , ""USB_HOST"""
menuitem "INTRAMHS0_DPM_MIRROR_P"           "per , ""INTRAMHS0_DPM_MIRROR_P"""
menuitem "INTRAMHS1_DPM_MIRROR_P"           "per , ""INTRAMHS1_DPM_MIRROR_P"""
menuitem "NOC"                              "per , ""NOC"""
)
)