365 lines
9.7 KiB
Plaintext
365 lines
9.7 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC11Exx Specific Menu
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; @Props: Released
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; @Author: DST, TOH, LUK
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; @Changelog: 2019-02-05 TOH
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; @Manufacturer: NXP - NXP Semiconductors
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; @Core: Cortex-M0P, Cortex-M0
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; @Chip:LPC11E11, LPC11E12, LPC11E13, LPC11E14, LPC11E35FHI33, LPC11E36, LPC11E37,
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; LPC11E37H, LPC11E66JBD48, LPC11E67JBD100, LPC11E67JBD48, LPC11E67JBD64,
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; LPC11E68JBD100, LPC11E68JBD48, LPC11E68JBD64
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menlpc11exx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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if corename()=="CORTEXM0"
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(
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popup "[:chip]Core Registers (Cortex-M0)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control"""
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menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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else
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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)
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separator
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menuitem "SYSCON" "per , ""SYSCON (System Configuration)"""
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menuitem "PMU" "per , ""PMU (Power Management Unit)"""
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menuitem "IOCON" "per , ""IOCON (I/O Control)"""
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menuitem "GPIO_PORT" "per , ""GPIO_PORT (General-Purpose I/O)"""
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popup "GINT0/1"
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(
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menuitem "GINT0" "per , ""GINT0/1 (Grouped GPIO Input Interrupt),GINT0"""
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menuitem "GINT1" "per , ""GINT0/1 (Grouped GPIO Input Interrupt),GINT1"""
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)
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menuitem "PINT" "per , ""PINT (Pin Interrupt And Pattern Match Engine)"""
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if cpuis("LPC11E6*")
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(
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menuitem "DMAC" "per , ""DMAC (DMA Controller)"""
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)
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if cpuis("LPC11E11*")||cpuis("LPC11E12*")||cpuis("LPC11E13*")||cpuis("LPC11E14*")||cpuis("LPC11E35FHI33*")||cpuis("LPC11E36*")||cpuis("LPC11E37*")
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(
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menuitem "USART" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"""
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)
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if (cpu()=="LPC11E66JBD48"||cpu()=="LPC11E67JBD100"||cpu()=="LPC11E67JBD48"||cpu()=="LPC11E67JBD64"||cpu()=="LPC11E68JBD100"||cpu()=="LPC11E68JBD48"||cpu()=="LPC11E68JBD64")
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(
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popup "USART"
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(
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menuitem "USART0" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART0"""
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menuitem "USART1" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART1"""
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menuitem "USART2" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART2"""
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menuitem "USART3" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART3"""
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if (cpu()=="LPC11E67JBD100"||cpu()=="LPC11E68JBD100")
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(
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menuitem "USART4" "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART4"""
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)
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)
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)
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popup "I2C"
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(
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menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0"""
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if cpuis("LPC11E6*")
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(
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menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1"""
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)
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)
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popup "SSP0/1"
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(
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menuitem "SSP0" "per , ""SSP0/1 (Synchronous Serial Port),SSP0"""
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menuitem "SSP1" "per , ""SSP0/1 (Synchronous Serial Port),SSP1"""
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)
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if cpuis("LPC11E6*")
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(
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menuitem "USB2.0" "per , ""USB2.0 (Full-Speed Device Controller)"""
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)
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menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)"""
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if cpuis("LPC11E6*")
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(
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popup "SCT0/1"
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(
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menuitem "SCT0" "per , ""SCT0/1 (State Configurable Timer),SCT0"""
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menuitem "SCT1" "per , ""SCT0/1 (State Configurable Timer),SCT1"""
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)
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)
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popup "CT16B0/1"
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(
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menuitem "CT16B0" "per , ""CT16B0/1 (16-bit Counter/Timers),CT16B0"""
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menuitem "CT16B1" "per , ""CT16B0/1 (16-bit Counter/Timers),CT16B1"""
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)
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popup "CT32B0/1"
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(
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menuitem "CT32B0" "per , ""CT32B0/1 (32-bit Counter/Timers),CT32B0"""
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menuitem "CT32B1" "per , ""CT32B0/1 (32-bit Counter/Timers),CT32B1"""
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)
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if cpuis("LPC11E6*")
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(
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menuitem "RTC" "per , ""RTC (Real Time Clock)"""
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)
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menuitem "WWDT" "per , ""WWDT (Windowed Watchdog Timer)"""
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if cpuis("LPC11E6*")
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(
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menuitem "CRC" "per , ""CRC"""
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)
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menuitem "FLASHCTRL" "per , ""FLASHCTRL (Flash Controller)"""
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)
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)
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