; --------------------------------------------------------------------------------
; @Title: LPC11Exx Specific Menu
; @Props: Released
; @Author: DST, TOH, LUK
; @Changelog: 2019-02-05 TOH
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-M0P, Cortex-M0
; @Chip:LPC11E11, LPC11E12, LPC11E13, LPC11E14, LPC11E35FHI33, LPC11E36, LPC11E37,
;       LPC11E37H, LPC11E66JBD48, LPC11E67JBD100, LPC11E67JBD48, LPC11E67JBD64,
;       LPC11E68JBD100, LPC11E68JBD48, LPC11E68JBD64
; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menlpc11exx.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if corename()=="CORTEXM0"
(
popup "[:chip]Core Registers (Cortex-M0)"
(
menuitem "[:chip]System Control"                                 "per , ""Core Registers (Cortex-M0),System Control"""
menuitem "[:chip]Nested Vectored Interrupt Controller"           "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control"                                  "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                      "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"       "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
menuitem "SYSCON"               "per , ""SYSCON (System Configuration)"""
menuitem "PMU"                  "per , ""PMU (Power Management Unit)"""
menuitem "IOCON"                "per , ""IOCON (I/O Control)"""
menuitem "GPIO_PORT"            "per , ""GPIO_PORT (General-Purpose I/O)"""
popup "GINT0/1"
(
menuitem "GINT0"            "per , ""GINT0/1 (Grouped GPIO Input Interrupt),GINT0"""
menuitem "GINT1"            "per , ""GINT0/1 (Grouped GPIO Input Interrupt),GINT1"""
)
menuitem "PINT"                 "per , ""PINT (Pin Interrupt And Pattern Match Engine)"""
if cpuis("LPC11E6*")
(
menuitem "DMAC"             "per , ""DMAC (DMA Controller)"""
)
if cpuis("LPC11E11*")||cpuis("LPC11E12*")||cpuis("LPC11E13*")||cpuis("LPC11E14*")||cpuis("LPC11E35FHI33*")||cpuis("LPC11E36*")||cpuis("LPC11E37*")
(
menuitem "USART"            "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter)"""
)
if (cpu()=="LPC11E66JBD48"||cpu()=="LPC11E67JBD100"||cpu()=="LPC11E67JBD48"||cpu()=="LPC11E67JBD64"||cpu()=="LPC11E68JBD100"||cpu()=="LPC11E68JBD48"||cpu()=="LPC11E68JBD64")
(
popup "USART"
(
menuitem "USART0"       "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART0"""
menuitem "USART1"       "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART1"""
menuitem "USART2"       "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART2"""
menuitem "USART3"       "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART3"""
if (cpu()=="LPC11E67JBD100"||cpu()=="LPC11E68JBD100")
(
menuitem "USART4"   "per , ""USART (Universal Synchronous/Asynchronous Receiver/Transmitter),USART4"""
)
)
)
popup "I2C"
(
menuitem "I2C0"             "per , ""I2C (Inter-Integrated Circuit),I2C0"""
if cpuis("LPC11E6*")
(
menuitem "I2C1"         "per , ""I2C (Inter-Integrated Circuit),I2C1"""
)
)
popup "SSP0/1"
(
menuitem "SSP0"             "per , ""SSP0/1 (Synchronous Serial Port),SSP0"""
menuitem "SSP1"             "per , ""SSP0/1 (Synchronous Serial Port),SSP1"""
)
if cpuis("LPC11E6*")
(
menuitem "USB2.0"           "per , ""USB2.0 (Full-Speed Device Controller)"""
)
menuitem "ADC"                  "per , ""ADC (Analog-to-Digital Converter)"""
if cpuis("LPC11E6*")
(
popup "SCT0/1"
(
menuitem "SCT0"         "per , ""SCT0/1 (State Configurable Timer),SCT0"""
menuitem "SCT1"         "per , ""SCT0/1 (State Configurable Timer),SCT1"""
)
)
popup "CT16B0/1"
(
menuitem "CT16B0"           "per , ""CT16B0/1 (16-bit Counter/Timers),CT16B0"""
menuitem "CT16B1"           "per , ""CT16B0/1 (16-bit Counter/Timers),CT16B1"""
)
popup "CT32B0/1"
(
menuitem "CT32B0"           "per , ""CT32B0/1 (32-bit Counter/Timers),CT32B0"""
menuitem "CT32B1"           "per , ""CT32B0/1 (32-bit Counter/Timers),CT32B1"""
)
if cpuis("LPC11E6*")
(
menuitem "RTC"              "per , ""RTC (Real Time Clock)"""
)
menuitem "WWDT"                 "per , ""WWDT (Windowed Watchdog Timer)"""
if cpuis("LPC11E6*")
(
menuitem "CRC"              "per , ""CRC"""
)
menuitem "FLASHCTRL"            "per , ""FLASHCTRL (Flash Controller)"""
)
)