313 lines
8.5 KiB
Plaintext
313 lines
8.5 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: EFM32HGxxx Specific Menu
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; @Props: Released
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; @Author: DPR, MJE, BCA, RMG
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; @Changelog: 2018-05-09 DPR
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; @Manufacturer: SiliconLabs - Silicon Laboratories Inc.
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; @Core: Cortex-M0+
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; @Chip: EFM32HG108F32, EFM32HG108F64, EFM32HG110F32, EFM32HG110F64,
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; EFM32HG210F32, EFM32HG210F64, EFM32HG222F32, EFM32HG222F64,
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; EFM32HG308F32, EFM32HG308F64, EFM32HG309F32, EFM32HG309F64,
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; EFM32HG310F32 ,EFM32HG310F64, EFM32HG321F32, EFM32HG321F64,
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; EFM32HG322F32, EFM32HG322F64, EFM32HG350F32, EFM32HG350F64
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; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menefm32hgxxx.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-M0+)"
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(
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menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control"""
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menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
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menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
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popup "[:chip]Debug"
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(
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menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
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menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
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menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
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)
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)
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separator
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menuitem "MSC" "per , ""MSC (Memory System Controller)"""
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menuitem "DMA" "per , ""DMA (DMA Controller)"""
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menuitem "RMU" "per , ""RMU (Reset Management Unit)"""
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menuitem "EMU" "per , ""EMU (Energy Management Unit)"""
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menuitem "CMU" "per , ""CMU (Clock Management Unit)"""
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menuitem "WDOG" "per , ""WDOG (Watchdog Timer)"""
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menuitem "PRS" "per , ""PRS (Peripheral Reflex System)"""
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if (cpu()!="EFM32HG108"&&cpu()!="EFM32HG310"&&cpu()!="EFM32HG210"&&cpu()!="EFM32HG222")
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(
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menuitem "USB" "per , ""USB (Universal Serial Bus Controller)"""
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)
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menuitem "I2C" "per , ""I2C (Inter-Integrated Circuit Interface)"""
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popup "USART"
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(
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menuitem "USART 0" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),USART 0"""
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menuitem "USART 1" "per , ""USART (Universal Synchronous Asynchronous Receiver/Transmitter),USART 1"""
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)
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menuitem "LEUART" "per , ""LEUART (Low Energy Universal Asynchronous Receiver/Transmitter)"""
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popup "TIMER"
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(
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menuitem "TIMER0" "per , ""TIMER (Timer/Counter),TIMER0"""
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menuitem "TIMER1" "per , ""TIMER (Timer/Counter),TIMER1"""
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menuitem "TIMER2" "per , ""TIMER (Timer/Counter),TIMER2"""
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)
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menuitem "RTC" "per , ""RTC (Real Time Counter)"""
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menuitem "PCNT" "per , ""PCNT (Pulse Counter)"""
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menuitem "ACMP" "per , ""ACMP (Analog Comparator)"""
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menuitem "VCMP" "per , ""VCMP (Voltage Comparator)"""
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menuitem "ADC" "per , ""ADC (Analog to Digital Converter)"""
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menuitem "IDAC" "per , ""IDAC (Current Digital to Analog Converter)"""
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menuitem "AES" "per , ""AES (Advanced Encryption Standard)"""
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popup "GPIO"
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(
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menuitem "PORT A" "per , ""GPIO (General Purpose Input/Output),PORT A"""
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menuitem "PORT B" "per , ""GPIO (General Purpose Input/Output),PORT B"""
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menuitem "PORT C" "per , ""GPIO (General Purpose Input/Output),PORT C"""
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menuitem "PORT D" "per , ""GPIO (General Purpose Input/Output),PORT D"""
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menuitem "PORT E" "per , ""GPIO (General Purpose Input/Output),PORT E"""
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menuitem "PORT F" "per , ""GPIO (General Purpose Input/Output),PORT F"""
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menuitem "COMMON REGISTERS" "per , ""GPIO (General Purpose Input/Output),COMMON REGISTERS"""
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)
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)
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)
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