442 lines
19 KiB
Plaintext
442 lines
19 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: Menu for ArriaVSOC
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; @Props: Released
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; @Author: PBU
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; @Changelog: 2015-06-30 PBU
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; @Manufacturer: ALTERA - Altera Corporation
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; @Chip: ARRIAVSOC
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: menarriavsoc.men 16339 2023-07-03 13:30:14Z pegold $
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add
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menu
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(
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IF SOFTWARE.BUILD.BASE()>=69655.
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(
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popup "&CPU"
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(
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separator
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IF CPU.FEATURE(MMU)
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(
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popup "[:mmu]MMU"
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(
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menuitem "[:mmureg]MMU Control" "MMU.view"
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separator
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menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
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menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
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separator
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IF CPU.FEATURE(ITLBDUMP)
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(
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menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
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)
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IF CPU.FEATURE(DTLBDUMP)
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(
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menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
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)
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IF CPU.FEATURE(TLB0DUMP)
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(
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menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
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)
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IF CPU.FEATURE(TLB1DUMP)
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(
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menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
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)
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)
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)
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IF COMPonent.AVAILable("SMMU")
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(
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popup "[:mmu]SMMU"
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(
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menuitem "[:chip]SMMU1 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU1 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
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SMMU.StreamMapTable &(name)
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)
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IF COMPonent.AVAILable("SMMU2")
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(
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separator
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menuitem "[:chip]SMMU2 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU2 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU3")
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(
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separator
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menuitem "[:chip]SMMU3 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU3 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU4")
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(
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separator
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menuitem "[:chip]SMMU4 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU4 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU5")
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(
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separator
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menuitem "[:chip]SMMU5 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU5 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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IF COMPonent.AVAILable("SMMU6")
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(
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separator
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menuitem "[:chip]SMMU6 Registers"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.Register.Global &(name)
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)
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menuitem "[:mmureg]SMMU6 StreamMapTable"
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(
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PRIVATE &name
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&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
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SMMU.StreamMapTable &(name)
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)
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)
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)
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)
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IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
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(
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popup "[:cache]Cache"
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(
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IF CPU.FEATURE(L1ICACHEDUMP)
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(
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menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
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menuitem "[:cache]ICACHE List" "CACHE.List IC"
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menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
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)
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IF CPU.FEATURE(L1DCACHEDUMP)
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(
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separator
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menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
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menuitem "[:cache]DCACHE List" "CACHE.List DC"
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menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
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)
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IF CPU.FEATURE(L2CACHEDUMP)
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(
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separator
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menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
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menuitem "[:cache]L2CACHE List" "CACHE.List L2"
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menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
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)
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)
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)
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)
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popup "&Trace"
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(
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separator
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IF COMPonent.AVAILable("ITM")
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(
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popup "ITM"
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(
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default
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menuitem "[:oconfig]ITM settings..." "ITM.state"
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separator
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menuitem "[:alist]ITMTrace List" "ITMTrace.List"
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)
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)
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IF COMPonent.AVAILable("STM")
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(
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popup "STM"
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(
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default
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menuitem "[:oconfig]STM settings..." "STM.state"
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separator
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menuitem "[:alist]STMTrace List" "STMTrace.List"
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)
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)
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IF COMPonent.AVAILable("HTM")
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(
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popup "HTM"
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(
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default
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menuitem "[:oconfig]HTM settings..." "HTM.state"
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separator
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menuitem "[:alist]HTMTrace List" "HTMTrace.List"
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)
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)
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IF COMPonent.AVAILable("TPIU")
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(
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menuitem "[:oconfig]TPIU settings..." "TPIU.state"
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)
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IF COMPonent.AVAILable("ETR")
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(
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menuitem "[:oconfig]ETR settings..."
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(
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PRIVATE &pdd
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&pdd=OS.PDD()
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DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
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)
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)
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)
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popup "&Misc"
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(
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popup "Tools"
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(
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IF CPUIS64BIT()||CPU.FEATURE("SPR")
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(
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menuitem "ARM System Register Converter"
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(
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DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
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)
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)
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IF CPU.FEATURE("C15")
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(
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menuitem "ARM Coprocessor Converter"
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(
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DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
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)
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)
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)
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)
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popup "&Perf"
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(
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IF CPU.FEATURE(BMC)
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(
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before "Reset"
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menuitem "[:bmc]Benchmark Counters" "BMC.state"
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before "Reset"
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separator
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)
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)
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)
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popup "Peripherals"
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(
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popup "[:chip]Core Registers (Cortex-A9MPCore)"
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(
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menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
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menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
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menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
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menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
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menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
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menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
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menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON"""
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separator
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menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
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menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
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menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
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separator
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menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
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menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
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menuitem "[:chip]Interrupt Controller (PL-390)" "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
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)
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separator
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menuitem "STM;CoreSight System Trace Macrocell" "per , ""STM (CoreSight System Trace Macrocell)"""
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popup "DAP;Debug Access Port"
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(
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menuitem "DAP ROM" "per , ""DAP (Debug Access Port),DAP ROM"""
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menuitem "ETF;Embedded Trace FIFO" "per , ""DAP (Debug Access Port),ETF (Embedded Trace FIFO)"""
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menuitem "CTI;Cross-Trigger Interface" "per , ""DAP (Debug Access Port),CTI (Cross-Trigger Interface)"""
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menuitem "TPIU;Trace Port Interface Unit" "per , ""DAP (Debug Access Port),TPIU (Trace Port Interface Unit)"""
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menuitem "Trace Funnel" "per , ""DAP (Debug Access Port),Trace Funnel"""
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menuitem "STM;System Trace Macrocell" "per , ""DAP (Debug Access Port),STM (System Trace Macrocell)"""
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menuitem "ETR;Embedded Trace Router" "per , ""DAP (Debug Access Port),ETR (Embedded Trace Router)"""
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menuitem "CTI FPGA;Cross-Trigger Interface of FPGA" "per , ""DAP (Debug Access Port),CTI FPGA (Cross-Trigger Interface of FPGA)"""
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menuitem "FPGA ROM" "per , ""DAP (Debug Access Port),FPGA ROM"""
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menuitem "Cortex-A9 ROM" "per , ""DAP (Debug Access Port),Cortex-A9 ROM"""
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menuitem "CPU 0 Debug" "per , ""DAP (Debug Access Port),CPU 0 Debug"""
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menuitem "CPU 0 PMU;CPU 0 Performance Monitor Unit" "per , ""DAP (Debug Access Port),CPU 0 PMU (CPU 0 Performance Monitor Unit)"""
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menuitem "CPU 1 Debug" "per , ""DAP (Debug Access Port),CPU 1 Debug"""
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menuitem "CPU 1 PMU;CPU 1 Performance Monitor Unit" "per , ""DAP (Debug Access Port),CPU 1 PMU (CPU 1 Performance Monitor Unit)"""
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menuitem "CTI 0;Cross-Trigger Interface 0" "per , ""DAP (Debug Access Port),CTI 0 (Cross-Trigger Interface 0)"""
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menuitem "CTI 1;Cross-Trigger Interface 1" "per , ""DAP (Debug Access Port),CTI 1 (Cross-Trigger Interface 1)"""
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menuitem "PTM 0;Program Trace Macrocell 0" "per , ""DAP (Debug Access Port),PTM 0 (Program Trace Macrocell 0)"""
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menuitem "PTM 1;Program Trace Macrocell 1" "per , ""DAP (Debug Access Port),PTM 1 (Program Trace Macrocell 1)"""
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)
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separator
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popup "LWHPS to FPGAREGS;LWHPS2FPGA AXI Bridge Module"
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(
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menuitem "ID Register Group" "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),ID Register Group"""
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menuitem "Master Register Group" "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),Master Register Group"""
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menuitem "Slave Register Group" "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),Slave Register Group"""
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)
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popup "HPS to FPGAREGS;HPS2FPGA AXI Bridge Module"
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(
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menuitem "ID Register Group" "per , ""HPS2FPGAREGS (HPS2FPGA AXI Bridge Module),ID Register Group"""
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menuitem "Master Register Group" "per , ""HPS2FPGAREGS (HPS2FPGA AXI Bridge Module),Master Register Group"""
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)
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popup "FPGA to HPSREGS;FPGA2HPS AXI Bridge Module"
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(
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menuitem "ID Register Group" "per , ""FPGA2HPSREGS (FPGA2HPS AXI Bridge Module),ID Register Group"""
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menuitem "Slave Register Group" "per , ""FPGA2HPSREGS (FPGA2HPS AXI Bridge Module),Slave Register Group"""
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)
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separator
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popup "EMAC;Ethernet Media Access Controller"
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(
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menuitem "EMAC 0" "per , ""EMAC (Ethernet Media Access Controller),EMAC0"""
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menuitem "EMAC 1" "per , ""EMAC (Ethernet Media Access Controller),EMAC1"""
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)
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menuitem "SDMMC;Secure Digital/MultiMediaCard" "per , ""SDMMC (Secure Digital/MultiMediaCard)"""
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menuitem "QSPI;Quad SPI Flash Controller" "per , ""QSPI (Quad SPI Flash Controller)"""
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popup "FPGAM;FPGA Manager"
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(
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menuitem "FPGAM" "per , ""FPGAM (FPGA Manager),FPGAM"""
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menuitem "FPGA Data" "per , ""FPGAM (FPGA Manager),FPGA Data"""
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)
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menuitem "ACPIDMAP;ACP ID Mapper" "per , ""ACPIDMAP (ACP ID Mapper)"""
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popup "GPIO;General Purpouse Input Output"
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(
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menuitem "GPIO 0" "per , ""GPIO (General Purpouse Input Output),GPIO 0"""
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menuitem "GPIO 1" "per , ""GPIO (General Purpouse Input Output),GPIO 1"""
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menuitem "GPIO 2" "per , ""GPIO (General Purpouse Input Output),GPIO 2"""
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)
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popup "L3 REGS;L3 GPV Registers"
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(
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menuitem "Remap" "per , ""L3REGS (L3 GPV Registers)"""
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menuitem "SECGRP;Security Register Group" "per , ""L3REGS (L3 GPV Registers),SECGRP (Security Register Group)"""
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menuitem "IDGRP;ID Register Group" "per , ""L3REGS (L3 GPV Registers),IDGRP (ID Register Group)"""
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menuitem "MASTERGRP;Master Register Group" "per , ""L3REGS (L3 GPV Registers),MASTERGRP (Master Register Group)"""
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menuitem "SLAVEGRP;Slave Register Group" "per , ""L3REGS (L3 GPV Registers),SLAVEGRP (Slave Register Group)"""
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)
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popup "USB;USB OTG Controller"
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(
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popup "USB 0"
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(
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menuitem "Global Registers" "per , ""USB (USB OTG Controller),USB 0,Global Registers"""
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menuitem "Host Mode Registers" "per , ""USB (USB OTG Controller),USB 0,Host Mode Registers"""
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menuitem "Device Mode Registers" "per , ""USB (USB OTG Controller),USB 0,Device Mode Registers"""
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menuitem "Power and Clock Gating Register" "per , ""USB (USB OTG Controller),USB 0,Power and Clock Gating Register"""
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)
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popup "USB 1"
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(
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menuitem "Global Registers" "per , ""USB (USB OTG Controller),USB 1,Global Registers"""
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menuitem "Host Mode Registers" "per , ""USB (USB OTG Controller),USB 1,Host Mode Registers"""
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menuitem "Device Mode Registers" "per , ""USB (USB OTG Controller),USB 1,Device Mode Registers"""
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menuitem "Power and Clock Gating Register" "per , ""USB (USB OTG Controller),USB 1,Power and Clock Gating Register"""
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)
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)
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popup "NANDREGS;NAND Flash Controller Module Registers"
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(
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menuitem "Configuration Registers" "per , ""NANDREGS (NAND Flash Controller Module Registers),Configuration Registers"""
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menuitem "Device Parameters" "per , ""NANDREGS (NAND Flash Controller Module Registers),Device Parameters"""
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menuitem "Interrupt and Status Registers" "per , ""NANDREGS (NAND Flash Controller Module Registers),Interrupt and Status Registers"""
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menuitem "ECC Registers" "per , ""NANDREGS (NAND Flash Controller Module Registers),ECC Registers"""
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menuitem "DMA Registers" "per , ""NANDREGS (NAND Flash Controller Module Registers),DMA Registers"""
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)
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popup "UART;UART Module"
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(
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menuitem "UART 0" "per , ""UART (UART Module),UART 0"""
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menuitem "UART 1" "per , ""UART (UART Module),UART 1"""
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)
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popup "I2C;I2C Module"
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(
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menuitem "I2C 0" "per , ""I2C (I2C Module),I2C 0"""
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menuitem "I2C 1" "per , ""I2C (I2C Module),I2C 1"""
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menuitem "I2C 2" "per , ""I2C (I2C Module),I2C 2"""
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menuitem "I2C 3" "per , ""I2C (I2C Module),I2C 3"""
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)
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popup "SPTIMER;SP Timer Module"
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(
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menuitem "SPTIMER 0" "per , ""SPTIMER (SP Timer Module),SPTIMER 0"""
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menuitem "SPTIMER 1" "per , ""SPTIMER (SP Timer Module),SPTIMER 1"""
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)
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menuitem "SDR;SDRAM Controller" "per , ""SDR (SDRAM Controller)"""
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popup "OSCTIMER;OSC Timer Module"
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(
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menuitem "OSC Timer 0" "per , ""OSCTIMER (OSC Timer Module),OSC Timer 0"""
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menuitem "OSC Timer 1" "per , ""OSCTIMER (OSC Timer Module),OSC Timer 1"""
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)
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popup "L4 WD;L4 Watchdog Module"
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(
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menuitem "Watchdog 0" "per , ""L4WD (L4 Watchdog Module),Watchdog 0"""
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menuitem "Watchdog 1" "per , ""L4WD (L4 Watchdog Module),Watchdog 1"""
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)
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popup "CLKMGR;Clock Manager Module"
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(
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menuitem "General Registers" "per , ""CLKMGR (Clock Manager Module),General Registers"""
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menuitem "Main PLL Group" "per , ""CLKMGR (Clock Manager Module),Main PLL Group"""
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menuitem "Peripheral PLL Group" "per , ""CLKMGR (Clock Manager Module),Peripheral PLL Group"""
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menuitem "SDRAM PLL Group" "per , ""CLKMGR (Clock Manager Module),SDRAM PLL Group"""
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)
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menuitem "RSTMGR;Reset Manager Module" "per , ""RSTMGR (Reset Manager Module)"""
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popup "SYSMGR;System Manager Module"
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(
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menuitem "SYSMGR;System Manager Module" "per , ""SYSMGR (System Manager Module)"""
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menuitem "FPGA Interface" "per , ""SYSMGR (System Manager Module),FPGA Interface"""
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menuitem "Scan Manager" "per , ""SYSMGR (System Manager Module),Scan Manager"""
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menuitem "Freeze Control" "per , ""SYSMGR (System Manager Module),Freeze Control"""
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menuitem "EMAC" "per , ""SYSMGR (System Manager Module),EMAC"""
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menuitem "DMA Controller" "per , ""SYSMGR (System Manager Module),DMA Controller"""
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menuitem "Preloader (initial software)" "per , ""SYSMGR (System Manager Module),Preloader (initial software)"""
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menuitem "Boot ROM Code Register" "per , ""SYSMGR (System Manager Module),Boot ROM Code Register"""
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menuitem "Boot ROM Hardware Register" "per , ""SYSMGR (System Manager Module),Boot ROM Hardware Register"""
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menuitem "SDMMC Controller Group" "per , ""SYSMGR (System Manager Module),SDMMC Controller Group"""
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menuitem "NAND Flash Controller Register" "per , ""SYSMGR (System Manager Module),NAND Flash Controller Register"""
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menuitem "USB Controller" "per , ""SYSMGR (System Manager Module),USB Controller"""
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menuitem "ECC Management Register" "per , ""SYSMGR (System Manager Module),ECC Management Register"""
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popup "Pin Mux Control"
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(
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menuitem "EMAC IO" "per , ""SYSMGR (System Manager Module),Pin Mux Control,EMAC IO"""
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menuitem "FLASH IO" "per , ""SYSMGR (System Manager Module),Pin Mux Control,FLASH IO"""
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menuitem "GENERAL IO" "per , ""SYSMGR (System Manager Module),Pin Mux Control,GENERAL IO"""
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menuitem "MIXED_1 IO" "per , ""SYSMGR (System Manager Module),Pin Mux Control,MIXED_1 IO"""
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menuitem "MIXED_2 IO" "per , ""SYSMGR (System Manager Module),Pin Mux Control,MIXED_2 IO"""
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menuitem "GPLINMUX (GPIO/LoanIO Input Mux)" "per , ""SYSMGR (System Manager Module),Pin Mux Control,GPLINMUX (GPIO/LoanIO Input Mux)"""
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menuitem "GPLMUX (GPIO/LoanIO Output/Output Mux)" "per , ""SYSMGR (System Manager Module),Pin Mux Control,GPLMUX (GPIO/LoanIO Output/Output Mux)"""
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menuitem "Source Select" "per , ""SYSMGR (System Manager Module),Pin Mux Control,Source Select"""
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)
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)
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menuitem "DMANONSECURE;Nonsecure DMA Module Address Space" "per , ""DMANONSECURE (Nonsecure DMA Module Address Space)"""
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menuitem "DMASECURE;Secure DMA Module Address Space" "per , ""DMASECURE (Secure DMA Module Address Space)"""
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popup "SPIS;SPI Slave Module"
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(
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menuitem "SPIS 0" "per , ""SPIS (SPI Slave Module),SPIS 0"""
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menuitem "SPIS 1" "per , ""SPIS (SPI Slave Module),SPIS 1"""
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)
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popup "SPI;SPI Master Module"
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(
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menuitem "SPIM 0" "per , ""SPI (SPI Master Module),SPIM 0"""
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menuitem "SPIM 1" "per , ""SPI (SPI Master Module),SPIM 1"""
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)
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menuitem "SCANMGR;Scan Manager Module" "per , ""SCANMGR (Scan Manager Module)"""
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menuitem "MPUL2;MPU L2 cache controller" "per , ""MPUL2 (MPU L2 cache controller)"""
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)
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)
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