; --------------------------------------------------------------------------------
; @Title: Menu for ArriaVSOC
; @Props: Released
; @Author: PBU
; @Changelog: 2015-06-30 PBU
; @Manufacturer: ALTERA - Altera Corporation
; @Chip: ARRIAVSOC
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menarriavsoc.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-A9MPCore)"
(
menuitem "[:chip]ID Registers"                        "per , ""Core Registers (Cortex-A9MPCore),ID Registers"""
menuitem "[:chip]System Control and Configuration"    "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration"""
menuitem "[:chip]Memory Management Unit"              "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit"""
menuitem "[:chip]Cache Control and Configuration"     "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration"""
menuitem "[:chip]System Performance Monitor"          "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor"""
menuitem "[:chip]Preload Engine"                      "per , ""Core Registers (Cortex-A9MPCore),Preload Engine"""
menuitem "[:chip]NEON"                                "per , ""Core Registers (Cortex-A9MPCore),NEON"""
separator
menuitem "[:chip]Debug Registers"                     "per , ""Core Registers (Cortex-A9MPCore),Debug Registers"""
menuitem "[:chip]Breakpoint Registers"                "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers"""
menuitem "[:chip]Watchpoint Control Registers"        "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers"""
separator
menuitem "[:chip]Snoop Control Unit (SCU)"            "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)"""
menuitem "[:chip]Timer and Watchdog Blocks"           "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks"""
menuitem "[:chip]Interrupt Controller (PL-390)"       "per , ""Core Registers (Cortex-A9MPCore),Interrupt Controller (PL-390)"""
)
separator
menuitem "STM;CoreSight System Trace Macrocell"              "per , ""STM (CoreSight System Trace Macrocell)"""
popup "DAP;Debug Access Port"
(
menuitem "DAP ROM"                                       "per , ""DAP (Debug Access Port),DAP ROM"""
menuitem "ETF;Embedded Trace FIFO"                       "per , ""DAP (Debug Access Port),ETF (Embedded Trace FIFO)"""
menuitem "CTI;Cross-Trigger Interface"                   "per , ""DAP (Debug Access Port),CTI (Cross-Trigger Interface)"""
menuitem "TPIU;Trace Port Interface Unit"                "per , ""DAP (Debug Access Port),TPIU (Trace Port Interface Unit)"""
menuitem "Trace Funnel"                                  "per , ""DAP (Debug Access Port),Trace Funnel"""
menuitem "STM;System Trace Macrocell"                    "per , ""DAP (Debug Access Port),STM (System Trace Macrocell)"""
menuitem "ETR;Embedded Trace Router"                     "per , ""DAP (Debug Access Port),ETR (Embedded Trace Router)"""
menuitem "CTI FPGA;Cross-Trigger Interface of FPGA"      "per , ""DAP (Debug Access Port),CTI FPGA (Cross-Trigger Interface of FPGA)"""
menuitem "FPGA ROM"                                      "per , ""DAP (Debug Access Port),FPGA ROM"""
menuitem "Cortex-A9 ROM"                                 "per , ""DAP (Debug Access Port),Cortex-A9 ROM"""
menuitem "CPU 0 Debug"                                   "per , ""DAP (Debug Access Port),CPU 0 Debug"""
menuitem "CPU 0 PMU;CPU 0 Performance Monitor Unit"      "per , ""DAP (Debug Access Port),CPU 0 PMU (CPU 0 Performance Monitor Unit)"""
menuitem "CPU 1 Debug"                                   "per , ""DAP (Debug Access Port),CPU 1 Debug"""
menuitem "CPU 1 PMU;CPU 1 Performance Monitor Unit"      "per , ""DAP (Debug Access Port),CPU 1 PMU (CPU 1 Performance Monitor Unit)"""
menuitem "CTI 0;Cross-Trigger Interface 0"               "per , ""DAP (Debug Access Port),CTI 0 (Cross-Trigger Interface 0)"""
menuitem "CTI 1;Cross-Trigger Interface 1"               "per , ""DAP (Debug Access Port),CTI 1 (Cross-Trigger Interface 1)"""
menuitem "PTM 0;Program Trace Macrocell 0"               "per , ""DAP (Debug Access Port),PTM 0 (Program Trace Macrocell 0)"""
menuitem "PTM 1;Program Trace Macrocell 1"               "per , ""DAP (Debug Access Port),PTM 1 (Program Trace Macrocell 1)"""
)
separator
popup "LWHPS to FPGAREGS;LWHPS2FPGA AXI Bridge Module"
(
menuitem "ID Register Group"                             "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),ID Register Group"""
menuitem "Master Register Group"                         "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),Master Register Group"""
menuitem "Slave Register Group"                          "per , ""LWHPS2FPGAREGS (LWHPS2FPGA AXI Bridge Module),Slave Register Group"""
)
popup "HPS to FPGAREGS;HPS2FPGA AXI Bridge Module"
(
menuitem "ID Register Group"                             "per , ""HPS2FPGAREGS (HPS2FPGA AXI Bridge Module),ID Register Group"""
menuitem "Master Register Group"                         "per , ""HPS2FPGAREGS (HPS2FPGA AXI Bridge Module),Master Register Group"""
)
popup "FPGA to HPSREGS;FPGA2HPS AXI Bridge Module"
(
menuitem "ID Register Group"                             "per , ""FPGA2HPSREGS (FPGA2HPS AXI Bridge Module),ID Register Group"""
menuitem "Slave Register Group"                          "per , ""FPGA2HPSREGS (FPGA2HPS AXI Bridge Module),Slave Register Group"""
)
separator
popup "EMAC;Ethernet Media Access Controller"
(
menuitem "EMAC 0"                                        "per , ""EMAC (Ethernet Media Access Controller),EMAC0"""
menuitem "EMAC 1"                                        "per , ""EMAC (Ethernet Media Access Controller),EMAC1"""
)
menuitem "SDMMC;Secure Digital/MultiMediaCard"               "per , ""SDMMC (Secure Digital/MultiMediaCard)"""
menuitem "QSPI;Quad SPI Flash Controller"                    "per , ""QSPI (Quad SPI Flash Controller)"""
popup "FPGAM;FPGA Manager"
(
menuitem "FPGAM"                                         "per , ""FPGAM (FPGA Manager),FPGAM"""
menuitem "FPGA Data"                                     "per , ""FPGAM (FPGA Manager),FPGA Data"""
)
menuitem "ACPIDMAP;ACP ID Mapper"                            "per , ""ACPIDMAP (ACP ID Mapper)"""
popup "GPIO;General Purpouse Input Output"
(
menuitem "GPIO 0"                                        "per , ""GPIO (General Purpouse Input Output),GPIO 0"""
menuitem "GPIO 1"                                        "per , ""GPIO (General Purpouse Input Output),GPIO 1"""
menuitem "GPIO 2"                                        "per , ""GPIO (General Purpouse Input Output),GPIO 2"""
)
popup "L3 REGS;L3 GPV Registers"
(
menuitem "Remap"                                         "per , ""L3REGS (L3 GPV Registers)"""
menuitem "SECGRP;Security Register Group"                "per , ""L3REGS (L3 GPV Registers),SECGRP (Security Register Group)"""
menuitem "IDGRP;ID Register Group"                       "per , ""L3REGS (L3 GPV Registers),IDGRP (ID Register Group)"""
menuitem "MASTERGRP;Master Register Group"               "per , ""L3REGS (L3 GPV Registers),MASTERGRP (Master Register Group)"""
menuitem "SLAVEGRP;Slave Register Group"                 "per , ""L3REGS (L3 GPV Registers),SLAVEGRP (Slave Register Group)"""
)
popup "USB;USB OTG Controller"
(
popup "USB 0"
(
menuitem "Global Registers"                          "per , ""USB (USB OTG Controller),USB 0,Global Registers"""
menuitem "Host Mode Registers"                       "per , ""USB (USB OTG Controller),USB 0,Host Mode Registers"""
menuitem "Device Mode Registers"                     "per , ""USB (USB OTG Controller),USB 0,Device Mode Registers"""
menuitem "Power and Clock Gating Register"           "per , ""USB (USB OTG Controller),USB 0,Power and Clock Gating Register"""
)
popup "USB 1"
(
menuitem "Global Registers"                          "per , ""USB (USB OTG Controller),USB 1,Global Registers"""
menuitem "Host Mode Registers"                       "per , ""USB (USB OTG Controller),USB 1,Host Mode Registers"""
menuitem "Device Mode Registers"                     "per , ""USB (USB OTG Controller),USB 1,Device Mode Registers"""
menuitem "Power and Clock Gating Register"           "per , ""USB (USB OTG Controller),USB 1,Power and Clock Gating Register"""
)
)
popup "NANDREGS;NAND Flash Controller Module Registers"
(
menuitem "Configuration Registers"                       "per , ""NANDREGS (NAND Flash Controller Module Registers),Configuration Registers"""
menuitem "Device Parameters"                             "per , ""NANDREGS (NAND Flash Controller Module Registers),Device Parameters"""
menuitem "Interrupt and Status Registers"                "per , ""NANDREGS (NAND Flash Controller Module Registers),Interrupt and Status Registers"""
menuitem "ECC Registers"                                 "per , ""NANDREGS (NAND Flash Controller Module Registers),ECC Registers"""
menuitem "DMA Registers"                                 "per , ""NANDREGS (NAND Flash Controller Module Registers),DMA Registers"""
)
popup "UART;UART Module"
(
menuitem "UART 0"                                        "per , ""UART (UART Module),UART 0"""
menuitem "UART 1"                                        "per , ""UART (UART Module),UART 1"""
)
popup "I2C;I2C Module"
(
menuitem "I2C 0"                                         "per , ""I2C (I2C Module),I2C 0"""
menuitem "I2C 1"                                         "per , ""I2C (I2C Module),I2C 1"""
menuitem "I2C 2"                                         "per , ""I2C (I2C Module),I2C 2"""
menuitem "I2C 3"                                         "per , ""I2C (I2C Module),I2C 3"""
)
popup "SPTIMER;SP Timer Module"
(
menuitem "SPTIMER 0"                                     "per , ""SPTIMER (SP Timer Module),SPTIMER 0"""
menuitem "SPTIMER 1"                                     "per , ""SPTIMER (SP Timer Module),SPTIMER 1"""
)
menuitem "SDR;SDRAM Controller"                              "per , ""SDR (SDRAM Controller)"""
popup "OSCTIMER;OSC Timer Module"
(
menuitem "OSC Timer 0"                                   "per , ""OSCTIMER (OSC Timer Module),OSC Timer 0"""
menuitem "OSC Timer 1"                                   "per , ""OSCTIMER (OSC Timer Module),OSC Timer 1"""
)
popup "L4 WD;L4 Watchdog Module"
(
menuitem "Watchdog 0"                                    "per , ""L4WD (L4 Watchdog Module),Watchdog 0"""
menuitem "Watchdog 1"                                    "per , ""L4WD (L4 Watchdog Module),Watchdog 1"""
)
popup "CLKMGR;Clock Manager Module"
(
menuitem "General Registers"                             "per , ""CLKMGR (Clock Manager Module),General Registers"""
menuitem "Main PLL Group"                                "per , ""CLKMGR (Clock Manager Module),Main PLL Group"""
menuitem "Peripheral PLL Group"                          "per , ""CLKMGR (Clock Manager Module),Peripheral PLL Group"""
menuitem "SDRAM PLL Group"                               "per , ""CLKMGR (Clock Manager Module),SDRAM PLL Group"""
)
menuitem "RSTMGR;Reset Manager Module"                       "per , ""RSTMGR (Reset Manager Module)"""
popup "SYSMGR;System Manager Module"
(
menuitem "SYSMGR;System Manager Module"                  "per , ""SYSMGR (System Manager Module)"""
menuitem "FPGA Interface"                                "per , ""SYSMGR (System Manager Module),FPGA Interface"""
menuitem "Scan Manager"                                  "per , ""SYSMGR (System Manager Module),Scan Manager"""
menuitem "Freeze Control"                                "per , ""SYSMGR (System Manager Module),Freeze Control"""
menuitem "EMAC"                                          "per , ""SYSMGR (System Manager Module),EMAC"""
menuitem "DMA Controller"                                "per , ""SYSMGR (System Manager Module),DMA Controller"""
menuitem "Preloader (initial software)"                  "per , ""SYSMGR (System Manager Module),Preloader (initial software)"""
menuitem "Boot ROM Code Register"                        "per , ""SYSMGR (System Manager Module),Boot ROM Code Register"""
menuitem "Boot ROM Hardware Register"                    "per , ""SYSMGR (System Manager Module),Boot ROM Hardware Register"""
menuitem "SDMMC Controller Group"                        "per , ""SYSMGR (System Manager Module),SDMMC Controller Group"""
menuitem "NAND Flash Controller Register"                "per , ""SYSMGR (System Manager Module),NAND Flash Controller Register"""
menuitem "USB Controller"                                "per , ""SYSMGR (System Manager Module),USB Controller"""
menuitem "ECC Management Register"                       "per , ""SYSMGR (System Manager Module),ECC Management Register"""
popup "Pin Mux Control"
(
menuitem "EMAC IO"                                   "per , ""SYSMGR (System Manager Module),Pin Mux Control,EMAC IO"""
menuitem "FLASH IO"                                  "per , ""SYSMGR (System Manager Module),Pin Mux Control,FLASH IO"""
menuitem "GENERAL IO"                                "per , ""SYSMGR (System Manager Module),Pin Mux Control,GENERAL IO"""
menuitem "MIXED_1 IO"                                "per , ""SYSMGR (System Manager Module),Pin Mux Control,MIXED_1 IO"""
menuitem "MIXED_2 IO"                                "per , ""SYSMGR (System Manager Module),Pin Mux Control,MIXED_2 IO"""
menuitem "GPLINMUX (GPIO/LoanIO Input Mux)"          "per , ""SYSMGR (System Manager Module),Pin Mux Control,GPLINMUX (GPIO/LoanIO Input Mux)"""
menuitem "GPLMUX (GPIO/LoanIO Output/Output Mux)"    "per , ""SYSMGR (System Manager Module),Pin Mux Control,GPLMUX (GPIO/LoanIO Output/Output Mux)"""
menuitem "Source Select"                             "per , ""SYSMGR (System Manager Module),Pin Mux Control,Source Select"""
)
)
menuitem "DMANONSECURE;Nonsecure DMA Module Address Space"   "per , ""DMANONSECURE (Nonsecure DMA Module Address Space)"""
menuitem "DMASECURE;Secure DMA Module Address Space"         "per , ""DMASECURE (Secure DMA Module Address Space)"""
popup "SPIS;SPI Slave Module"
(
menuitem "SPIS 0"                                        "per , ""SPIS (SPI Slave Module),SPIS 0"""
menuitem "SPIS 1"                                        "per , ""SPIS (SPI Slave Module),SPIS 1"""
)
popup "SPI;SPI Master Module"
(
menuitem "SPIM 0"                                        "per , ""SPI (SPI Master Module),SPIM 0"""
menuitem "SPIM 1"                                        "per , ""SPI (SPI Master Module),SPIM 1"""
)
menuitem "SCANMGR;Scan Manager Module"                       "per , ""SCANMGR (Scan Manager Module)"""
menuitem "MPUL2;MPU L2 cache controller"                     "per , ""MPUL2 (MPU L2 cache controller)"""
)
)