103599 lines
7.0 MiB
103599 lines
7.0 MiB
; --------------------------------------------------------------------------------
|
|
; @Title: S6J311 On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: DRD, AMM, WIL, MMK
|
|
; @Changelog: 2014-12-19 DRD
|
|
; 2016-03-14 MMK
|
|
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
|
|
; @Doc: S6J3110_MN708-00004-E.pdf
|
|
; @Core: Cortex-R5
|
|
; @Chip: S6J311*JAA, S6J311*HAA, S6J312*HAA
|
|
; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: pers6j311.per 12662 2020-12-17 08:09:59Z pegold $
|
|
|
|
; Known problems
|
|
; MODULE REGISTER DESCRIPTION
|
|
; RTC DEBUG register doesn't exist in I/O map
|
|
; CLOCK SYSTEM CKOTCNTR register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVSOCFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVPLL1CFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVPLL2CFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVPLL3CFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVSP1CFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVSP2CFGR0/1 register doesn't exist in I/O map
|
|
; CLOCK SUPERVISOR CSVSP3CFGR0/1 register doesn't exist in I/O map
|
|
; AXI module doesn't exist in I/O map
|
|
; TCM MK_* registers don't exist in I/O map
|
|
; EAM module doesn't exist in provided xml and headers
|
|
; TCM module doesn't exist in provided xml and headers
|
|
config 16. 8.
|
|
base ad:0x00
|
|
tree "Core Registers (Cortex-R5)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
width 0x8
|
|
; --------------------------------------------------------------------------------
|
|
; Identification registers
|
|
; --------------------------------------------------------------------------------
|
|
tree "ID Registers"
|
|
rgroup.long c15:0x00++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
|
|
textline " "
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
|
|
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long c15:0x100++0x00
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
|
|
rgroup.long c15:0x400--0x400
|
|
line.long 0x0 "MPUIR,MPU type register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
|
|
bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
|
|
rgroup.long c15:0x500++0x00
|
|
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
|
|
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
|
|
textline " "
|
|
rgroup.long c15:0x0410++0x00
|
|
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..."
|
|
bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0510++0x00
|
|
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c15:0x0610++0x00
|
|
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c15:0x0710++0x00
|
|
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x020++0x00
|
|
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x120++0x00
|
|
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x220++0x00
|
|
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x320++0x00
|
|
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x420++0x00
|
|
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c15:0x0520++0x00
|
|
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
|
|
rgroup.long c15:0x0620++0x00
|
|
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
|
|
rgroup.long c15:0x0720++0x00
|
|
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
|
|
rgroup.long c15:0x010++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c15:0x110++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
rgroup.long c15:0x210++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c15:0x310++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c15:0x02f++0x00
|
|
line.long 0x00 "BO1R,Build Options 1 Register"
|
|
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM"
|
|
bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
|
|
group.long c15:0x12f++0x00
|
|
line.long 0x00 "BO2R,Build Options 2 Register"
|
|
bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2"
|
|
bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No"
|
|
bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
|
|
bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No"
|
|
bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
|
|
bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
|
|
bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
|
|
bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
|
|
bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
|
|
bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
|
|
bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes"
|
|
group.long c15:0x72f++0x00
|
|
line.long 0x00 "POR,Pin Options Register"
|
|
bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High"
|
|
bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High"
|
|
bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High"
|
|
tree.end
|
|
width 0x8
|
|
tree "System Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x101++0x00
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
|
|
bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
|
|
bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable"
|
|
bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
|
|
bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
|
|
bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
|
|
bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
|
|
bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
|
|
bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0f++0x00
|
|
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x201++0x00
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x000b++0x00
|
|
line.long 0x00 "SPCR,Slave Port Control Register"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group.long c15:0x01++0x00
|
|
line.long 0x00 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x05++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x15++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x06++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable"
|
|
bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register"
|
|
group.long c15:0x206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group.long c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group.long c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group.long c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group.long c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
width 0x08
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RBAR12,Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RSER12,Region Size and Enable Register 12"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xC
|
|
line.long 0x00 "RACR12,Region Access Control Register 12"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RBAR13,Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RSER13,Region Size and Enable Register 13"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xD
|
|
line.long 0x00 "RACR13,Region Access Control Register 13"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RBAR14,Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RSER14,Region Size and Enable Register 14"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xE
|
|
line.long 0x00 "RACR14,Region Access Control Register 14"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RBAR15,Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RSER15,Region Size and Enable Register 15"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xF
|
|
line.long 0x00 "RACR15,Region Access Control Register 15"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
textline " "
|
|
group.long c15:0x10f++0x00
|
|
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x20f++0x00
|
|
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
group.long c15:0x30f++0x00
|
|
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
|
|
bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x00
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1700++0x00
|
|
line.long 0x00 "AIDR,Auxiliary ID Register"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000++0x00
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
group.long c15:0x5f++0x00
|
|
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
|
|
bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3"
|
|
hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean"
|
|
group.long c15:0xef++0x00
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xc9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled"
|
|
group.long c15:0x1c9++0x00
|
|
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x2c9++0x00
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group.long c15:0x3c9++0x00
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group.long c15:0x4c9++0x00
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
group.long c15:0x5c9++0x00
|
|
line.long 0x00 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
|
|
group.long c15:0xd9++0x00
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group.long c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group.long c15:0xe9++0x00
|
|
line.long 0x00 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
|
|
group.long c15:0x1e9++0x00
|
|
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group.long c15:0x2e9++0x00
|
|
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree "Validation Registers"
|
|
group.long c15:0x01f++0x00
|
|
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x11f++0x00
|
|
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x21f++0x00
|
|
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x31f++0x00
|
|
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
group.long c15:0x41f++0x00
|
|
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
|
|
group.long c15:0x51f++0x00
|
|
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
|
|
group.long c15:0x61f++0x00
|
|
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
|
|
group.long c15:0x71f++0x00
|
|
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
|
|
eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
|
|
tree.end
|
|
tree.end
|
|
width 11.
|
|
width 18.
|
|
tree "Debug Registers"
|
|
tree "Processor Identifier Registers"
|
|
rgroup.long c14:832.++0x00
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup.long c14:833.++0x00
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup.long c14:834.++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
group.long c14:835.++0x00
|
|
line.long 0x00 "AMIDR,Alias of MIDR"
|
|
rgroup.long c14:836.++0x00
|
|
line.long 0x00 "MPUTR,MPU Type Register"
|
|
rgroup.long c14:837.++0x00
|
|
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
|
|
group.long c14:838.++0x00
|
|
line.long 0x00 "AMIDR0,Alias of MIDR"
|
|
group.long c14:839.++0x00
|
|
line.long 0x00 "AMIDR1,Alias of MIDR"
|
|
rgroup.long c14:840.++0x00
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:841.++0x00
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:842.++0x00
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup.long c14:843.++0x00
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long c14:844.++0x00
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:845.++0x00
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup.long c14:846.++0x00
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup.long c14:847.++0x00
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:848.++0x00
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:849.++0x00
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:850.++0x00
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:851.++0x00
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup.long c14:852.++0x00
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup.long c14:853.++0x00
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 15.
|
|
tree "Coresight Management Registers"
|
|
group.long c14:960.++0x00
|
|
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration"
|
|
group.long c14:1000.++0x00
|
|
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set"
|
|
group.long c14:1001.++0x00
|
|
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear"
|
|
wgroup.long c14:1004.++0x00
|
|
line.long 0x00 "DBGLAR,Lock Access Register"
|
|
rgroup.long c14:1005.++0x00
|
|
line.long 0x00 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked"
|
|
rgroup.long c14:1006.++0x00
|
|
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled"
|
|
rgroup.long c14:1011.++0x00
|
|
line.long 0x00 "DBGDEVTYPE,Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
tree.end
|
|
textline " "
|
|
width 12.
|
|
rgroup.long c14:0.++0x0
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version"
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High"
|
|
bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number"
|
|
group.long c14:34.++0x0
|
|
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
|
|
bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full"
|
|
bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle"
|
|
bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
|
|
bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes"
|
|
bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes"
|
|
bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited"
|
|
bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug"
|
|
group.long c14:0x7++0x0
|
|
line.long 0x00 "DBGVCR,Debug Vector Catch register"
|
|
bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled"
|
|
hgroup.long c14:32.++0x0
|
|
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group.long c14:35.++0x00
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group.long c14:10.++0x0
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes"
|
|
bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes"
|
|
wgroup.long c14:33.++0x0
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup.long c14:36.++0x0
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt"
|
|
textline " "
|
|
rgroup.long c14:193.++0x0
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
|
|
group.long c14:196.++0x0
|
|
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
|
|
rgroup.long c14:197.++0x0
|
|
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
|
|
bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset"
|
|
bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset"
|
|
bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up"
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group.long c14:64.++0x0
|
|
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group.long c14:80.++0x0
|
|
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:65.++0x0
|
|
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group.long c14:81.++0x0
|
|
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:66.++0x0
|
|
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group.long c14:82.++0x0
|
|
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:67.++0x0
|
|
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group.long c14:83.++0x0
|
|
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:68.++0x0
|
|
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group.long c14:84.++0x0
|
|
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:69.++0x0
|
|
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group.long c14:85.++0x0
|
|
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:70.++0x0
|
|
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group.long c14:86.++0x0
|
|
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group.long c14:71.++0x0
|
|
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group.long c14:87.++0x0
|
|
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group.long c14:96.++0x0
|
|
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:112.++0x0
|
|
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:97.++0x0
|
|
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:113.++0x0
|
|
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:98.++0x0
|
|
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:114.++0x0
|
|
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:99.++0x0
|
|
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:115.++0x0
|
|
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:100.++0x0
|
|
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:116.++0x0
|
|
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:101.++0x0
|
|
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:117.++0x0
|
|
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:102.++0x0
|
|
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:118.++0x0
|
|
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:103.++0x0
|
|
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group.long c14:119.++0x0
|
|
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group.long c14:6.++0x0
|
|
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 11.
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "MODEC (Operation Mode)"
|
|
base ad:0xB0600800
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "MODER,Mode Register"
|
|
bitfld.long 0x00 31. " USERMODE ,User mode bit" "Board,User"
|
|
bitfld.long 0x00 12. " MD ,Mode bit" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RESET"
|
|
base ad:0xB0600380
|
|
width 17.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "RSTCNTR,Reset Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DBGR ,Software debugger reset register bit"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWHRST ,Software trigger hard reset register bit"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWRST ,Software reset register bit"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "RSTCAUSEUR,User Factor Register"
|
|
bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
sif cpuis("S6J342*")||cpuis("S6J351*")
|
|
newline
|
|
bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected"
|
|
endif
|
|
bitfld.long 0x00 27. " CSVSR0 ,Clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " LVDH1R ,External power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " INITX ,INITX detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected"
|
|
line.long 0x04 "EXCSVRSTCAUSEUR,User Extended SCV Reset Factor Register"
|
|
bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected"
|
|
line.long 0x08 "PDRSTCAUSEUR,User PowerDomain Reset Factor Register"
|
|
bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "RSTCAUSEBT,BootROM Reset Factor Register"
|
|
bitfld.long 0x00 31. " LVDL2R ,Extended internal power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " LVDL1R ,Internal power supply low-voltage reset detection bit" "Not detected,Detected"
|
|
sif cpuis("S6J342*")||cpuis("S6J351*")
|
|
newline
|
|
bitfld.long 0x00 29. " CSVSCRR ,Slow CR clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " CSVFCRR ,Fast CR clock supervisor reset detection bit" "Not detected,Detected"
|
|
endif
|
|
bitfld.long 0x00 27. " CSVSR0 ,SSCG0 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " CSVPR0 ,PLL0 clock supervisor reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 25. " CSVSOR ,Sub clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " CSVMOR ,Main clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " SHRST ,Software trigger hard reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " SRST ,Software reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 12. " SWDR ,Software watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " HWDR ,Hardware watchdog reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " PRFERR ,Profile error reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " SRSTX ,NSRST pin input reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 8. " IMR ,Illegal mode reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " LVDH2R ,Extended external power supply low-voltage detection reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " LVDH1R ,External power supply low-voltage reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " RSTX ,RSTX pin input reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 3. " CKTOR ,Clock stop wait timeout reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " INITX ,INITX reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " RVD ,RAM retention low-voltage reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " PONR ,Power-on reset detection bit" "Not detected,Detected"
|
|
line.long 0x04 "EXCSVRSTCAUSEBT,BootROM Extended CSV Reset Factor Register"
|
|
bitfld.long 0x04 7. " CSVSR3 ,SSCG3 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 6. " CSVSR2 ,SSCG2 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 5. " CSVSR1 ,SSCG1 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 3. " CSVPR3 ,PLL3 clock supervisor reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x04 2. " CSVPR2 ,PLL2 clock supervisor reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " CSVPR1 ,PLL1 clock supervisor reset detection bit" "Not detected,Detected"
|
|
line.long 0x08 "PDRSTCAUSEBT,BootROM PowerDomain Reset Factor Register"
|
|
bitfld.long 0x08 17. " PD6R1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 16. " PD6R0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 15. " PD5R3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 14. " PD5R2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 13. " PD5R1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 12. " PD5R0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 9. " PD4R1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 8. " PD4R0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 4. " PD3R0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " PD2R0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "PDRSTATUS,PowerDomain Reset Status Register"
|
|
bitfld.long 0x00 17. " PD6RS1 ,PowerDomain6_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " PD6RS0 ,PowerDomain6_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " PD5RS3 ,PowerDomain5_3 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " PD5RS2 ,PowerDomain5_2 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 13. " PD5RS1 ,PowerDomain5_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " PD5RS0 ,PowerDomain5_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " PD4RS1 ,PowerDomain4_1 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " PD4RS0 ,PowerDomain4_0 reset detection bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 4. " PD3RS0 ,PowerDomain3_0 reset detection bit" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " PD2RS0 ,PowerDomain2_0 reset detection bit" "Not detected,Detected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CLOCK SYSTEM"
|
|
base ad:0xB0600600
|
|
width 15.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "CRCNTR,CR clock control register"
|
|
bitfld.long 0x00 8.--12. " TRC ,Coarse trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " TRF ,Fine trimming bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "MOSCCNTR,Main oscillator control register"
|
|
bitfld.long 0x00 31. " MCMODE ,Main clock amplifier oscillation mode bit" "Oscillation mode,Stop mode"
|
|
bitfld.long 0x00 26.--27. " MCGAIN ,Main Clock GAIN bit" "4(3.6)MHz,8MHz,16MHz,25MHz"
|
|
bitfld.long 0x00 8. " DIV2SEL ,Select bit" "Main clock,Main clk/2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCIMEN ,Fast Main Clock Input Enable Control bit" "Disabled,Enabled"
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "PLLSSCGSTCNTR,PLL/SSCG stabilization time control register"
|
|
bitfld.long 0x00 4.--7. " SSCGSTABS ,SSCGSTABS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PLLSTABS ,Stabilization time for PLL0/1/2/3 clock" ",,,,,,,,2^9 cycle,2^10 cycle,2^11 cycle,2^12 cycle,2^13 cycle,2^14 cycle,2^15 cycle,2^16 cycle"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "PLL0CGCNTR,PLL0 clock gear control register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLLCGLP ,PLL clock gear loop configuration bit"
|
|
bitfld.long 0x00 14.--15. " PLLCGSTP ,PLL clock gear step configuration bit" "1 step,2 steps,3steps,4steps"
|
|
bitfld.long 0x00 8.--13. " PLLCGSSN ,PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rbitfld.long 0x00 6.--7. " PLLCGSTS ,PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down"
|
|
bitfld.long 0x00 1. " PLLCGSTR ,PLL clock gear start bit" "No operation,Start clk. operation"
|
|
bitfld.long 0x00 0. " PLLCGEN ,PLL clock gear enable bit" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "SSCG0CGCNTR,SSCG PPL0 clock gear control register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SSCGCGLP ,SSCG PLL clock gear loop configuration bit"
|
|
bitfld.long 0x00 14.--15. " SSCGCGSTP ,SSCG PLL clock gear step configuration bit" "1 step,2 steps,3steps,4steps"
|
|
bitfld.long 0x00 8.--13. " SSCGCGSSN ,SSCG PLL clock gear start step configuration bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
rbitfld.long 0x00 6.--7. " SSCGCGSTS ,SSCG PLL clock gear status bit" "Stop at min.,Gear up,Stop at max.,Gear down"
|
|
bitfld.long 0x00 1. " SSCGCGSTR ,SSCG PLL clock gear start bit" "No operation,Start clk. operation"
|
|
bitfld.long 0x00 0. " SSCGCGEN ,SSCG PLL clock gear enable bit" "Disabled,Enabled"
|
|
; group.long 0x30++0x3
|
|
; line.long 0x00 "CKOTCNTR,Clock output function control register"
|
|
; bitfld.long 0x00 24. " ENCLKO ,Enable/Disable clock output function" "Disabled,Enabled"
|
|
; bitfld.long 0x00 8.--10. " CKOUTDIV ,Clock Division bits" "Not divided,2,4,8,16,32,64,128"
|
|
; bitfld.long 0x00 0.--3. " CKSEL ,Clock Select bits" "Fast-CR,Slow-CR,Main,Sub,PLL0,PLL1,PLL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,Prohibit(Fast-CR),Prohibit(Fast-CR),Prohibit(Fast-CR),Tied to low"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "LOW POWER CONSUPTION"
|
|
tree "SYSC 0"
|
|
base ad:0xB0600000
|
|
width 15.
|
|
group.long 0x00++0x3 "Protection Register"
|
|
line.long 0x00 "PROTKEYR,Protection Key Setting Register"
|
|
group.long 0x80++0x3 "Run Profile Registers"
|
|
line.long 0x00 "RUNPDCFGR,RUN Power Domain Setting Register"
|
|
rbitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply" ",Supply"
|
|
rbitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply" ",Supply"
|
|
bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply" "Not supply,Supply"
|
|
bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply" "Not supply,Supply"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply" "Not supply,Supply"
|
|
bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply" "Not supply,Supply"
|
|
bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply" "Not supply,Supply"
|
|
bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply" "Not supply,Supply"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply" ",Supply"
|
|
rbitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply" ",Supply"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "RUNCKSRER,RUN Clock Source Enable Register"
|
|
bitfld.long 0x00 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3EN ,PPL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2EN ,PPL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1EN ,PPL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0EN ,PPL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" ",Enabled"
|
|
rbitfld.long 0x00 0. " CROSCEN ,High-speed CR clock oscillation enable bit" ",Enabled"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "RUNCKSELR,Run Clock Selection Register"
|
|
bitfld.long 0x00 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG PPL0,,Clock fixed al 'L'"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x00 "RUNCKER,RUN Clock Enable Register"
|
|
rbitfld.long 0x00 1. " ENCLKMCUCP ,MCUconfig APB clock oscillation enable bit" ",Enabled"
|
|
rbitfld.long 0x00 0. " ENCLKMCUCH ,MCUconfig AHB clock oscillation enable bit" ",Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "RUNCKDIVR,RUN Clock Divider Register"
|
|
bitfld.long 0x00 8.--11. " MCUCPDIV ,MCUconfig APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " MCUCHDIV ,MCUconfig AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "RUNPLL0CNTR,Run PLLx Control Register"
|
|
bitfld.long 0x00 31. " PLL0ISEL ,PLL input clock selection bit" "Main clock,High-speed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PPL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "RUNSSCG0CNTR0,RUN SSCG Control Register 0"
|
|
bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PPl input clock selection bit" "Main clock,High-speed CR"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PPL clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PPL M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PPL input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "RUNSSCG0CNTR1,RUN SSCG Control Register 1"
|
|
bitfld.long 0x00 24. " SSCG0SSEN ,SSCG PLL enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " SSCG0FREQ ,SSCG PLL clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096"
|
|
bitfld.long 0x00 16. " SSCG0MODE ,SSCG PLL modulation mode setting bit" "Down,Center"
|
|
hexmask.long.word 0x00 0.--9. 1. " SSCG0RATE ,SSCG PPL clock modulation ratio control bits"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "RUNLVDCFGR,RUN Low-voltage Detection Setting Register"
|
|
bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
rbitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 9.--12. " LVDH1V ,Extended internal low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
rbitfld.long 0x00 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
rbitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "RUNCSVCFGR,Run Clock Supervisor Setting Register"
|
|
bitfld.long 0x00 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "RUNREGCFGR,RUN Regular Setting Register"
|
|
rbitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main mode,"
|
|
bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bits" "1.20V,"
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "TRGRUNCNTR,RUN Update Trigger Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " APPLY_RUN ,RUN profile update trigger setting bit"
|
|
group.long 0x100++0x3 "PSS Profile Group Registers"
|
|
line.long 0x00 "PSSPDCFGR,PSS Domain Setting Register"
|
|
bitfld.long 0x00 25. " PD6_1EN ,Power domain 6_1 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 24. " PD6_0EN ,Power domain 6_0 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 23. " PD5_3EN ,Power domain 5_3 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 22. " PD5_2EN ,Power domain 5_2 power supply control bit" "Not supply,Supply"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PD5_1EN ,Power domain 5_1 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 20. " PD5_0EN ,Power domain 5_0 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 17. " PD4_1EN ,Power domain 4_1 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 16. " PD4_0EN ,Power domain 4_0 power supply control bit" "Not supply,Supply"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PD3EN ,Power domain 3 power supply control bit" "Not supply,Supply"
|
|
bitfld.long 0x00 8. " PD2EN ,Power domain 2 power supply control bit" "Not supply,Supply"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "PSSCKSRER,PSS Clock Source Enable Register"
|
|
bitfld.long 0x00 19. " SSCG3EN ,SSCG PPL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2EN ,SSCG PPL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1EN ,SSCG PPL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0EN ,SSCG PPL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3EN ,PPL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2EN ,PPL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1EN ,PPL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0EN ,PPL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "PSSCKSELR,PSS Clock Selection Register"
|
|
bitfld.long 0x00 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG PPL0,,Fixed at 'L'"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "PSSCKER,PSS Clock Enable Register"
|
|
bitfld.long 0x00 1. " ENCLKMCUCP ,MCUconfig APB clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCLKMCUCH ,MCUconfig AHB clock oscillation enable bit" "Disabled,Enabled"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "PSSCKDIVR,PSS Clock Divider Register"
|
|
bitfld.long 0x00 8.--11. " MCUCPDIV ,MCUconfig APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " MCUCHDIV ,MCUconfig AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "PSSPLL0CNTR,PSS PPL0 Control Register"
|
|
bitfld.long 0x00 31. " PLL0ISEL ,PLL0 input clock selection bit" "Main clock,High-speed CR"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PLL0 clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " PLL0DIVM ,PLL0 M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "PSSSSCG0CNTR0,PSS SSCG0 Control Register 0"
|
|
bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PLL0 input clock selection bit" "Main clock,High-speed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PLL0 N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PLL0 M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PLL0 input clock divider setting bits" "No division,/2,/4,/6"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "PSSSSCG0CNTR1,PSS SSCG0 Control Register 1"
|
|
bitfld.long 0x00 24. " SSCG0SSEN ,SSCG PLL0 modulation enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " SSCG0FREQ ,SSCG PLL0 modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096"
|
|
bitfld.long 0x00 16. " SSCG0MODE ,SSCG PLL0 modulation mode setting bit" "Down,Center"
|
|
hexmask.long.word 0x00 0.--9. 1. " SSCG0RATE ,SSCG PLL0 clock modulation ratio control bits"
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "PSSLVDCFGR,PSS Low-voltage Detection setting register"
|
|
bitfld.long 0x00 30. " LVDL1S ,Internal Low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 24. " LVDL1E ,Low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage operation selection bit" "Reset,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
rbitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
rbitfld.long 0x00 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
rbitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "PSSCSVCFGR,PSS Clock Supervisor Setting Register"
|
|
bitfld.long 0x00 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "PSSREGCFGR,PSS Regulator Setting Register"
|
|
bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby"
|
|
rbitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bit" "1.20v,"
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "PSSENR,PSS Profile Update Enable Register"
|
|
hexmask.byte 0x00 0.--7. 1. " PSSEN0 ,PSS profile update enable setting bits"
|
|
rgroup.long 0x180++0x3 "APP Profile Group Registers"
|
|
line.long 0x00 "APPPDCFGR,APP Power Domain Setting Register"
|
|
bitfld.long 0x00 25. " PD6_1EN ,Power control bit for power domain 6_1" "Off,On"
|
|
bitfld.long 0x00 24. " PD6_0EN ,Power control bit for power domain 6_0" "Off,On"
|
|
bitfld.long 0x00 23. " PD5_3EN ,Power control bit for power domain 5_3" "Off,On"
|
|
bitfld.long 0x00 22. " PD5_2EN ,Power control bit for power domain 5_2" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PD5_1EN ,Power control bit for power domain 5_1" "Off,On"
|
|
bitfld.long 0x00 20. " PD5_0EN ,Power control bit for power domain 5_0" "Off,On"
|
|
bitfld.long 0x00 17. " PD4_1EN ,Power control bit for power domain 4_1" "Off,On"
|
|
bitfld.long 0x00 16. " PD4_0EN ,Power control bit for power domain 4_0" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PD3EN ,Power control bit for power domain 3" "Off,On"
|
|
bitfld.long 0x00 8. " PD2EN ,Power control bit for power domain 2" "Off,On"
|
|
rgroup.long 0x184++0x3
|
|
line.long 0x00 "APPCKSRER,APP Clock Source Enable Register"
|
|
bitfld.long 0x00 19. " SSCG3EN ,SSCG PLL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2EN ,SSCG PLL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1EN ,SSCG PLL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0EN ,SSCG PLL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3EN ,PLL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2EN ,PLL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1EN ,PLL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0EN ,PLL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x00 "APPCKSELR,APP Clock Selection Register"
|
|
bitfld.long 0x00 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed CR,Low-speed CR,Main clock,Sub clock,PPL0,SSCG PPL0,,Fixed to 'L'"
|
|
rgroup.long 0x18C++0x3
|
|
line.long 0x00 "APPCKER,APP Clock Enable Register"
|
|
bitfld.long 0x00 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x190++0x3
|
|
line.long 0x00 "APPCKDIVR,APP Clock Divider Register"
|
|
bitfld.long 0x00 8.--11. " MCUCPDIV ,MCU config APB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " MCUCHDIV ,MCU config AHB clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
rgroup.long 0x194++0x3
|
|
line.long 0x00 "APPPLL0CNTR,APP PPL 0 Control Register"
|
|
bitfld.long 0x00 31. " PLL0ISEL ,PPL0 input clock selection bit" "Main,High-speed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,NPPL0 clock N-multiplier ratio setting bits"
|
|
bitfld.long 0x00 8.--11. " PLL0DIVM ,PP0 clock M-divider setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " PLL0DIVL ,PLL0 input clock divider setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x1A4++0x3
|
|
line.long 0x00 "APPSSCG0CNTR0,APP SSCG0 Control Register 0"
|
|
bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PPL PPL0 input clock selection bit" "Main clock,High-speed CR"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PPL0 clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PPL0 Clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PPL0 input clock divider setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x1A8++0x3
|
|
line.long 0x00 "APPSSCG0CNTR1,APP SSCG0 Control Register 1"
|
|
bitfld.long 0x00 24. " SSCG0SSEN ,SSCG PP0 modulation enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " SSCG0FREQ ,SSCG PPL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096"
|
|
bitfld.long 0x00 16. " SSCG0MODE ,SSCG PPL0 modulation mode setting bit" "Down,Center"
|
|
hexmask.long.word 0x00 0.--9. 1. " SSCG0RATE ,PPL0 clock modulation ratio control bits"
|
|
rgroup.long 0x1C4++0x3
|
|
line.long 0x00 "APPLVDCFGR,APP Low-voltage Detection Setting Register"
|
|
bitfld.long 0x00 30. " LVDL1S ,Internal Low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 24. " LVDL1E ,Internal Low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage operation selection bit" "Reset,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,?..."
|
|
bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x1C8++0x3
|
|
line.long 0x00 "APPCSVCFGR,APP Clock Supervisor Setting Register"
|
|
bitfld.long 0x00 19. " SSCG3CSVE ,SSCG PPL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2CSVE ,SSCG PPL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1CSVE ,SSCG PPL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0CSVE ,SSCG PPL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3CSVE ,PPL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2CSVE ,PPL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1CSVE ,PPL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0CSVE ,PPL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x1CC++0x3
|
|
line.long 0x00 "APPREGCFGR,APP Regulator Setting Register"
|
|
bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby"
|
|
bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bit" "1.20v,"
|
|
rgroup.long 0x200++0x3 "STS Profile Group Registers"
|
|
line.long 0x00 "STSPDCFGR,STS Power Domain Setting Register"
|
|
bitfld.long 0x00 25. " PD6_1EN ,Domain 6_1 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 24. " PD6_0EN ,Domain 6_0 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 23. " PD5_3EN ,Domain 5_3 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 22. " PD5_2EN ,Domain 5_2 power supply control bit" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PD5_1EN ,Domain 5_1 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 20. " PD5_0EN ,Domain 5_0 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 17. " PD4_1EN ,Domain 4_1 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 16. " PD4_0EN ,Domain 4_0 power supply control bit" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PD3EN ,Domain 3 power supply control bit" "Off,On"
|
|
bitfld.long 0x00 8. " PD2EN ,Domain 2 power supply control bit" "Off,On"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x00 "STSCKSRER,STS Source Enable Register"
|
|
bitfld.long 0x00 23. " SSCG3RDY ,SSCG PPL3 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 22. " SSCG2RDY ,SSCG PPL2 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 21. " SSCG1RDY ,SSCG PPL1 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 20. " SSCG0RDY ,SSCG PPL0 clock oscillation stabilization bit" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SSCG3EN ,SSCG PPL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2EN ,SSCG PPL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1EN ,SSCG PPL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0EN ,SSCG PPL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLL3RDY ,PPL3 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 14. " PLL2RDY ,PPL2 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 13. " PLL1RDY ,PPL1 clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 12. " PLL0RDY ,PPL0 clock oscillation stabilization bit" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3EN ,PPL3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2EN ,PPL2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1EN ,PPL1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0EN ,PPL0 clock oscillation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SOSCRDY ,Sub clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 6. " MOSCRDY ,Main clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 5. " SCROSCRDY ,Low-speed CR clock oscillation stabilization bit" "Not stable,Stable"
|
|
bitfld.long 0x00 4. " CROSCRDY ,High-speed CR clock oscillation stabilization bit" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOSCEN ,Sub clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MOSCEN ,Main clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCROSCEN ,Low-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CROSCEN ,High-speed CR clock oscillation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "STSCKSELR,STS Clock Selection Register"
|
|
bitfld.long 0x00 4.--6. " CDMCUCCM ,Clock domain MCUC clock selection status bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG PPL0,,Fixed to 'L'"
|
|
bitfld.long 0x00 0.--2. " CDMCUCCSL ,Clock domain MCUC clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG PPL0,,Fixed to 'L'"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x00 "STSCKER,STS Clock Enable Register"
|
|
bitfld.long 0x00 1. " ENCLKMCUCP ,MCU config APB clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCLKMCUCH ,MCU config AHB clock oscillation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "STSCKDIVR,STS Division Register"
|
|
bitfld.long 0x00 8.--11. " MCUCPDIV ,MCU config APB clock division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " MCUCHDIV ,MCU config AHB clock division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x00 "STSPLL0CNTR,STS PPL0 Control Register"
|
|
bitfld.long 0x00 31. " PLL0ISEL ,PPL0 input clock selection bit" "Main,High-speed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PLL0DIVN ,PPL0 clock N-multiplication rate setting bits"
|
|
bitfld.long 0x00 8.--11. " PLL0DIVM ,PPL0 output clock M-division ratio setting bits" "2,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30"
|
|
bitfld.long 0x00 0.--1. " PLL0DIVL ,PPL0 clock L-division ratio setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "STSSSCG0CNTR0,STS SSCG0 Control Register 0"
|
|
bitfld.long 0x00 31. " SSCG0ISEL ,SSCG PPL0 input clock selection bit" "Main,High-speed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SSCG0DIVN ,SSCG PPL0 clock N-multiplier setting bits"
|
|
bitfld.long 0x00 8.--11. " SSCG0DIVM ,SSCG PPL0 clock M-division setting bits" "/2,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
bitfld.long 0x00 0.--1. " SSCG0DIVL ,SSCG PPL0 input division setting bits" "No division,/2,/4,/6"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x00 "STSSSCG0CNTR1,STS SSCG0 control register 1"
|
|
bitfld.long 0x00 24. " SSCG0SSEN ,SSCG PPL0 modulation enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " SSCG0FREQ ,SSCG PPL0 clock modulation frequency selection bits" "1/1024,1/2048,1/4096,1/4096"
|
|
bitfld.long 0x00 16. " SSCG0MODE ,SSCG PPL0 modulation mode setting bit" "Down,Center"
|
|
hexmask.long.word 0x00 0.--9. 1. " SSCG0RATE ,SSCG PPL0 clock modulation ratio control bits"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x00 "STSLVDCFGR,STS Low-voltage Detection Setting Register"
|
|
bitfld.long 0x00 31. " LVDL1R ,Internal Low-voltage detection operation status bit" "Stopped,Performed"
|
|
bitfld.long 0x00 30. " LVDL1S ,Internal low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 25.--26. " LVDL1V ,Internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 24. " LVDL1E ,Internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LVDL2R ,Extended internal low-voltage detection operation status bit" "Stopped,Performed"
|
|
bitfld.long 0x00 22. " LVDL2S ,Extended internal low-voltage detection operation selection bit" "Reset,interrupt"
|
|
bitfld.long 0x00 17.--18. " LVDL2V ,Extended internal low-voltage detection voltage setting bits" ",,0.97,1.07"
|
|
bitfld.long 0x00 16. " LVDL2E ,Extended internal low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LVDH1R ,External low-voltage detection operation status bit" "Stopped,Performed"
|
|
bitfld.long 0x00 14. " LVDH1S ,External low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 9.--12. " LVDH1V ,External low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,,,,,,,,,"
|
|
bitfld.long 0x00 8. " LVDH1E ,External low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LVDH2R ,Extended external low-voltage detection operation status bit" "Stopped,Performed"
|
|
bitfld.long 0x00 6. " LVDH2S ,Extended external low-voltage detection operation selection bit" "Reset,Interrupt"
|
|
bitfld.long 0x00 1.--4. " LVDH2V ,Extended external low-voltage detection voltage setting bits" ",,,,3.8,4.0,4.2,,,,,,,,,"
|
|
bitfld.long 0x00 0. " LVDH2E ,Extended external low-voltage detection operation enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x248++0x3
|
|
line.long 0x00 "STSCSVCFGR,STS Clock Supervisor Setting Register"
|
|
bitfld.long 0x00 19. " SSCG3CSVE ,SSCG PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSCG2CSVE ,SSCG PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSCG1CSVE ,SSCG PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SSCG0CSVE ,SSCG PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3CSVE ,PLL3 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PLL2CSVE ,PLL2 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PLL1CSVE ,PLL1 clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PLL0CSVE ,PLL0 clock supervisor enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOCSVE ,Sub clock supervisor enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MOCSVE ,Main clock supervisor enable bit" "Disabled,Enabled"
|
|
rgroup.long 0x24C++0x3
|
|
line.long 0x00 "STSREGCFGR,APP Regulator Setting Register"
|
|
bitfld.long 0x00 7. " RMSEL ,Regulator mode setting bit" "Main,Standby"
|
|
bitfld.long 0x00 0. " RVSEL ,Regulator output voltage setting bits" "1.20v,"
|
|
rgroup.long 0x288++0x3 "System Registers"
|
|
line.long 0x00 "SYSSTSR,System Status Register"
|
|
bitfld.long 0x00 7. " PSSSTS0 ,PSS profile update status bit" "Not updated,Updated"
|
|
bitfld.long 0x00 6. " RUNSTS0 ,RUN profile update status bit" "Not updated,Updated"
|
|
bitfld.long 0x00 5. " PSSDF0 ,PSS profile update completion flag bit" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RUNDF0 ,RUN profile update completion (main status control)flag bit" "Not updated,Updated"
|
|
bitfld.long 0x00 1. " CPUSTS0 ,CPU0 Device status bit" "Operation,WFI"
|
|
bitfld.long 0x00 0. " DVSTS0 ,Device status bit" "PSS,RUN"
|
|
group.long 0x28C++0x3
|
|
line.long 0x00 "SYSINTER,System status interrupt enable register"
|
|
bitfld.long 0x00 4. " RUNDIE0 ,RUN profile update completion interrupt enable bit" "Disabled,Enabled"
|
|
group.long 0x290++0x3
|
|
line.long 0x00 "SYSICLR,System status flag and interrupt clear register"
|
|
bitfld.long 0x00 5. " PSSDFCLR0 ,PSS profile update completion flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RUNDFCLR0 ,RUN profile update completion flag clear bit" "No effect,Clear"
|
|
rgroup.long 0x294++0x3
|
|
line.long 0x00 "SYSERRIR0,System interrupt factor register 0"
|
|
bitfld.long 0x00 29. " LVDH2IF ,Extended external low-voltage detection interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " LVDH1IF ,External low-voltage detection interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " LVDL2IF ,Extended internal low-voltage detection interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " LVDL1IF ,Internal low-voltage detection interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SSCG3IF ,SSCG PPL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " SSCG2IF ,SSCG PPL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " SSCG1IF ,SSCG PPL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " SSCG0IF ,SSCG PPL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3IF ,PPL3 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " PLL2IF ,PPL2 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " PLL1IF ,PPL1 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " PLL0IF ,PPL0 abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOSCIF ,Sub oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MOSCIF ,Main oscillation abnormality detection error interrupt request bit" "No interrupt,Interrupt"
|
|
rgroup.long 0x298++0x3
|
|
line.long 0x00 "SYSERRIR1,System error interrupt factor register 1"
|
|
bitfld.long 0x00 6. " PSSERRIF0 ,PSS profile error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RUNWKERRIF0 ,RUN profile (PSS recovery time) error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RUNERRIF0 ,RUN profile error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PSSENERRIF0 ,PSS profile update enable write error interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PSSTRGCIF0 ,PSS trigger cancel interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RUNTRGERRIF ,RUN profile update enable write error interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TRGERRIF ,Trigger error interrupt request bit" "No interrupt,Interrupt"
|
|
wgroup.long 0x29C++0x3
|
|
line.long 0x00 "SYSERRICLR0,System error interrupt factor clear register 0"
|
|
bitfld.long 0x00 29. " LVDH2ICLR ,Extended external low-voltage detection interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 28. " LVDH1ICLR ,External external low-voltage detection interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 25. " LVDL2ICLR ,Extended internal low-voltage detection interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 24. " LVDL1ICLR ,Internal low-voltage detection interrupt factor clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SSCG3ICLR ,SSCG PPL3 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 18. " SSCG2ICLR ,SSCG PPL2 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 17. " SSCG1ICLR ,SSCG PPL1 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 16. " SSCG0ICLR ,SSCG PPL0 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLL3ICLR ,PPL3 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 10. " PLL2ICLR ,PPL2 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " PLL1ICLR ,PPL1 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 8. " PLL0ICLR ,PPL0 abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOSCICLR ,Sub oscillation abnormality detection error interrupt factor clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MOSCICLR ,Main oscillation abnormality detection error interrupt detection error interrupt factor clear bit" "No effect,Clear"
|
|
wgroup.long 0x2A0++0x3
|
|
line.long 0x00 "SYSERRICLR1,System error interrupt factor clear register 1"
|
|
bitfld.long 0x00 6. " PSSERRICLR0 ,PSS profile error interrupt request bit" "No effect,Clear"
|
|
bitfld.long 0x00 5. " RUNWKERRICLR0 ,RUN profile (PSS recovery time) error interrupt request bit" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RUNERRICLR0 ,Run profile error interrupt request bit" "No effect,Clear"
|
|
bitfld.long 0x00 3. " PSSENERRICLR0 ,PSS profile update enable write error interrupt request bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PSSTRGCICLR0 ,PSS trigger cancel interrupt request bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " RUNTRGERRICLR ,RUN profile update enable write error interrupt request bit" "No effect,Clear"
|
|
bitfld.long 0x00 0. " TRGERRICLR ,Trigger error interrupt request bit" "No effect,Clear"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x00 "SYSPROSTSR,Profile status register"
|
|
bitfld.long 0x00 2. " PSSPSTS ,PSS profile setting status bit" "No error,Error"
|
|
bitfld.long 0x00 1. " RUNWKPSTS ,RUN profile (PSS recovery tine)setting status bit" "No error,Error"
|
|
bitfld.long 0x00 0. " RUNPSTS ,RUN profile setting status bit" "No error,Error"
|
|
rgroup.long 0x2A8++0x3
|
|
line.long 0x00 "SYSRUNPEFR,RUN profile error flag register"
|
|
bitfld.long 0x00 6. " PEF6 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 5. " PEF5 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 4. " PEF4 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 3. " PEF3 ,Profile error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEF2 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 1. " PEF1 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 0. " PEF0 ,Profile error flag bit" "No error,Error"
|
|
rgroup.long 0x2AC++0x3
|
|
line.long 0x00 "SYSPSSPEFR,PSS profile error flag register"
|
|
bitfld.long 0x00 10. " PEF10 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 9. " PEF9 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 8. " PEF8 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 7. " PEF7 ,Profile error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PEF6 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 5. " PEF5 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 4. " PEF4 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 3. " PEF3 ,Profile error flag bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PEF1 ,Profile error flag bit" "No error,Error"
|
|
bitfld.long 0x00 0. " PEF0 ,Profile error flag bit" "No error,Error"
|
|
base ad:0xB0600680
|
|
width 18.
|
|
group.long 0x0++0x3 "Special Setting Register"
|
|
line.long 0x00 "SPECFGR,System Special Setting Register"
|
|
bitfld.long 0x00 31. " HOLDIO_PD6_1 ,Setting bit for power domain 6_1 HOLD data latch" "No retain,Retain"
|
|
bitfld.long 0x00 30. " HOLDIO_PD6_0 ,Setting bit for power domain 6_0 HOLD data latch" "No retain,Retain"
|
|
bitfld.long 0x00 29. " HOLDIO_PD5_3 ,Setting bit for power domain 5_3 HOLD data latch" "No retain,Retain"
|
|
bitfld.long 0x00 28. " HOLDIO_PD5_2 ,Setting bit for power domain 5_2 HOLD data latch" "No retain,Retain"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HOLDIO_PD5_1 ,Setting bit for power domain 5_1 HOLD data latch" "No retain,Retain"
|
|
bitfld.long 0x00 26. " HOLDIO_PD5_0 ,Setting bit for power domain 5_0 HOLD data latch" "No retain,Retain"
|
|
bitfld.long 0x00 24. " HOLDIO_PD2 ,Power domain 2 HOLD data latch setting bit" "No retain,Retain"
|
|
bitfld.long 0x00 23. " PSSPADCTRL ,PPS-time port configuring bit" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IO3RSTC ,I/O3V reset configuring bit" "No reset,Reset"
|
|
bitfld.long 0x00 8. " BRAMSC ,BackupRAM standby setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EXSTBCNT ,1.2 External power supply stabilization time setting bits" "1.0/0.5,2.0/1.0,3.0/1.5,4.0/2.0,5.0/2.5,6.0/3.0,7.0/3.5,8.0/4.0,9.0/4.5,10.0/5.0,12.0/6.0,14.0/7.0,16.0/8.0,18.0/9.0,20.0/10.0,30.0/15.0"
|
|
rgroup.long 0x80++0x3 "Debug Registers"
|
|
line.long 0x00 "JTAGDETECT,JTAG Detection Register"
|
|
bitfld.long 0x00 0. " DBGCON ,Debugger connection status bit" "Not connected,Connected"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "JTAGCNFG,JTAG Setting Register"
|
|
bitfld.long 0x00 0. " DBGDONE ,Debugger status bit" "Connected,Not connected"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "JTAGWAKEUP,JTAG Recovery Register"
|
|
bitfld.long 0x00 0. " DBGWKEN ,Debugger wakeup enable bit" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "MCU Config Group"
|
|
base ad:0xB0688800
|
|
width 8.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "IRSR0,MCU Config Interrupt Request Status Register 0"
|
|
bitfld.long 0x00 24. " IRQ_PW ,Partial wakeup interrupt " "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " IRQ_SCT_SUB ,Sub source clock timer interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " IRQ_SCT_MAIN ,Main source clock timer interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQ_SCT_SCR ,Low-speed source clock timer interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. " IRQ_SCT_CR ,High-speed source clock timer interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " IRQ_RTC ,RTC 0.5 seconds interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQ_SCU ,RUN profile update complete interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQ_HWDG ,Hardware watchdog timer advance warning interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*")
|
|
bitfld.long 0x00 4. " NMI_WAKE ,NMI_WAKE" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 3. " NMI_EXTINT ,NMI detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " NMI_HWDG ,Hardware watchdog timer detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " NMI_SCU ,Profile error detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " NMI_LVD ,Low power detection interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRSR1,MCU Config Interrupt Request Status Register 1"
|
|
sif !cpuis("S6J336*")&&!cpuis("S6J337*")
|
|
bitfld.long 0x04 31. " IRQ_EXTINT_[31] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " [30] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " [29] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " [28] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " [26] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " [25] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " [24] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x04 23. " IRQ_EXTINT_[23] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
endif
|
|
bitfld.long 0x04 22. " [22] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " [21] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " [20] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " [18] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " [17] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " [16] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " [12] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " [9] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,External interrupt detection status" "No interrupt,Interrupt"
|
|
line.long 0x08 "IRSR2,MCU Config Interrupt Request Register 2"
|
|
bitfld.long 0x08 18. " IRQ_RLT2 ,Reload timer ch2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 17. " IRQ_RLT1 ,Reload timer ch1 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " IRQ_RLT0 ,Reload timer ch0 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " IRQ_CRCAL ,CR calibration complete interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 8. " IRQ_EICU ,EICU complete interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 4. " IRQ_RAMIC ,BackUP-RAM initialization end interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 3. " IRQ_RAMTE ,BackUP-RAM diagnosis error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " IRQ_RAMTC ,BackUP-RAM diagnosis end interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x08 1. " IRQ_RAMSE ,BackUP-RAM single-bit error interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
bitfld.long 0x08 0. " NMI_RAMDE ,BackUP-RAM double-bit error interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 0. " IRQ_RAMDE ,BackUP-RAM double-bit error interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
sif (!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA"))
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "IRSR3,MCU Config Interrupt Request Status Register 3"
|
|
bitfld.long 0x00 30. " IRQ_MCAN2_INT1 ,CAN-FD ch2 interrupt 1 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " IRQ_MCAN1_INT1 ,CAN-FD ch1 interrupt 1 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IRQ_MCAN0_INT1 ,CAN-FD ch0 interrupt 1 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " IRQ_MCAN2_INT0 ,CAN-FD ch2 interrupt 0 status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. " IRQ_MCAN1_INT0 ,CAN-FD ch1 interrupt 0 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " IRQ_MCAN0_INT0 ,CAN-FD ch0 interrupt 0 status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " IRQ_MCAN2_SE ,CAN-FB ch2 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " IRQ_MCAN1_SE ,CAN-FB ch1 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 20. " IRQ_MCAN0_SE ,CAN-FD ch0 RAM ECC single-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*")
|
|
bitfld.long 0x00 18. " IRQ_MCAN2_DE ,CAN-FD ch2 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " IRQ_MCAN1_DE ,CAN-FD ch1 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " IRQ_MCAN0_DE ,CAN-FD ch0 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18. " NMI_MCAN2_DE ,CAN-FD ch2 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " NMI_MCAN1_DE ,CAN-FD ch1 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " NMI_MCAN0_DE ,CAN-FD ch0 RAM ECC double-bit error detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 10. " IRQ_MFS2_SIRQ ,MFS ch2 sync field detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " IRQ_MFS1_SIRQ ,MFS ch1 sync field detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " IRQ_MFS0_SIRQ ,MFS ch0 sync field detection interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IRQ_MFS2_RIRQ ,MFS ch2 reception interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " IRQ_MFS1_RIRQ ,MFS ch1 reception interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQ_MFS0_RIRQ ,MFS ch0 reception interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQ_MFS2_TIRQ ,MFS ch2 transmission interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IRQ_MFS1_TIRQ ,MFS ch1 transmission interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. " IRQ_MFS0_TIRQ ,MFS ch0 transmission interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x04 "IRSR4,MCU Config Interrupt Request Status Register 4"
|
|
bitfld.long 0x04 6. " IRQ_MFS2_RIRQ ,MFS ch2 reception interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " IRQ_MFS1_RIRQ ,MFS ch1 reception interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " IRQ_MFS0_RIRQ ,MFS ch0 reception interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 2. " IRQ_MFS2_TIRQ ,MFS ch2 transmission interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " IRQ_MFS1_TIRQ ,MFS ch1 transmission interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " IRQ_MFS0_TIRQ ,MFS ch0 transmission interrupt status" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SYSC1"
|
|
base ad:0xB0300000
|
|
width 18.
|
|
group.long 0x00++0x03 "Protection Register"
|
|
line.long 0x00 "PROTKEYR,Protection Key Setting Register"
|
|
group.long 0x80++0x0B "RUN Profile Registers"
|
|
line.long 0x00 "SYSC1_RUNCKSELR0,RUN Clock Selection Register 0"
|
|
bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0"
|
|
newline
|
|
bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0,,Fixed at 'L'"
|
|
line.long 0x04 "SYSC1_RUNCKSELR1,RUN Clock Selection Register 1"
|
|
bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
line.long 0x08 "SYSC1_RUNCKSELR2,RUN Clock Selection Register 2"
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed at'L'"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,PPL1,Fixed at'L'"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PLL1,PPL2,PLL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed at'L'"
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")||cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0"
|
|
rbitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled"
|
|
elif cpuis("S6J336*")||cpuis("S6J337*")
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0"
|
|
bitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSTSC1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" ",Enabled"
|
|
else
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "SYSC1_RUNCKER0,RUN Clock Source Enable Register 0"
|
|
bitfld.long 0x00 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " ENCLKSYSC1 ,ENCLKSTSC1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x90++0x17
|
|
line.long 0x00 "SYSC1_RUNCKER1,RUN Clock Source Enable Register 1"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
bitfld.long 0x00 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled"
|
|
else
|
|
bitfld.long 0x00 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x00 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SYSC1_RUNCKER2,RUN Source Enable Register 2"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
bitfld.long 0x04 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x04 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" ",Enabled"
|
|
else
|
|
bitfld.long 0x04 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x08 "SYSC1_RUNCKDIVR0,RUN Clock Divider Register 0"
|
|
bitfld.long 0x08 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x08 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..."
|
|
bitfld.long 0x08 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8"
|
|
newline
|
|
bitfld.long 0x08 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x08 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x0C "SYSC1_RUNCKDIVR1,RUN Clock Divider Register 1"
|
|
bitfld.long 0x0C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--2. " EXTBUSDIV ,EXTBUT clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x10 "SYSC1_RUNCKDIVR2,RUN Clock Divider Register 2"
|
|
bitfld.long 0x10 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x10 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8"
|
|
line.long 0x14 "SYSC1_RUNCKDIVR3,RUN Clock Divider Register 3"
|
|
bitfld.long 0x14 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x14 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x14 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x14 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "SYSC1_RUNCKDIVR4,RUN Clock Divider Register 4"
|
|
bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
group.long 0xAC++0x13
|
|
line.long 0x00 "SYSC1_RUNCKDIVR5,RUN Clock Divider Register 5"
|
|
bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "SYSC1_RUNCKDIVR6,RUN Clock Divider Register 6"
|
|
bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC1_RUNCKDIVR7,RUN Clock Divider Register 7"
|
|
bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x0C "SYSC1_RUNCKDIVR8,RUN Clock Divider Register 8"
|
|
bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x10 "SYSC1_RUNCKDIVR9,RUN Clock Divider Register 9"
|
|
bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "SYSC1_RUNENR,RUN Profile Update Enable Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RUNEN1 ,RUN profile update enable"
|
|
else
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "SYSC1_RUNENR,RUN Profile Update Enable Register"
|
|
endif
|
|
group.long 0x100++0x27 "PSS Profile Registers"
|
|
line.long 0x00 "SYSC1_PSSCKSELR0,PSS Clock Selection Register 0"
|
|
bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,PPL1,PPL2,PPL3,SSCG PPL0,SSCG PPL1,SSCG PPL2,SSCG PPL3,,,,Fixed to 'L'"
|
|
bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PPL0"
|
|
newline
|
|
bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PPL0"
|
|
bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed,Low-speed,Main,Sub,PPL0,SSCG0 clock,,Fixed to 'L'"
|
|
line.long 0x04 "SYSC1_PSSCKSELR1,PSS Clock Selection Register 1"
|
|
bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x08 "SYSC1_PSSCKSELR2,PSS Clock Selection Register 2"
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,,Fixed to'L'"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed,Low-speed,Main,Sub,PLL0,SSCG0,PLL1,Fixed to'L'"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x0C "SYSC1_PSSCKER0,PSS Clock Source Enable Register 0"
|
|
bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " ENCLKTRC ,ECLKTRC clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
rbitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,"
|
|
else
|
|
bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x10 "SYSC1_PSSCKER1,PSS Clock Source Enable Register 1"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled"
|
|
else
|
|
bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" ",Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x14 "SYSC1_PSSCKER2,PSS Clock Source Enable Register 2"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" ",Enabled"
|
|
bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" ",Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" ",Enabled"
|
|
else
|
|
bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " ENCLKCD4B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x18 "SYSC1_PSSCKDIVR0,PSS Clock Divider Register 0"
|
|
bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
else
|
|
bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..."
|
|
endif
|
|
bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8"
|
|
newline
|
|
bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x1C "SYSC1_PSSCKDIVR1,PSS Clock Divider Register 1"
|
|
bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x20 "SYSC1_PSSCKDIVR2,PSS Clock Divider Register 2"
|
|
bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8"
|
|
line.long 0x24 "SYSC1_PSSCKDIVR3,PSS Clock Divider Register 3"
|
|
bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SYSC1_PSSCKDIVR4,PSS Clock Divider Register 4"
|
|
bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
group.long 0x12C++0x13
|
|
line.long 0x00 "SYSC1_PSSCKDIVR5,PSS Clock Divider Register 5"
|
|
bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "SYSC1_PSSCKDIVR6,PSS Clock Divider Register 6"
|
|
bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC1_PSSCKDIVR7,PSS Clock Divider Register 7"
|
|
bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x0C "SYSC1_PSSCKDIVR8,PSS Clock Divider Register 8"
|
|
bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x10 "SYSC1_PSSCKDIVR9,PSS Clock Divider Register 9"
|
|
bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "SYSC1_PSSENR,PSS Profile Update Enable Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSSEN1 ,PSS profile update enable bits"
|
|
else
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "SYSC1_PSSENR,PSS Profile Update Enable Register"
|
|
endif
|
|
rgroup.long 0x180++0x27 "APP Profile Registers"
|
|
line.long 0x00 "SYSC1_APPCKSELR0,APP Clock Selection Register 0"
|
|
bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PLL0"
|
|
newline
|
|
bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,,Fixed to 'L'"
|
|
line.long 0x04 "SYSC1_APPCKSELR1,APP Clock Selection Register 1"
|
|
bitfld.long 0x04 24.--27. " CD4CSL ,Clock domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 16.--19. " CD3CSL ,Clock domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 8.--11. " CD2CSL ,Clock domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
newline
|
|
bitfld.long 0x04 0.--3. " CD1CSL ,Clock domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x08 "SYSC1_APPCKSELR2,APP Clock Selection Register 2"
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,,Fixed to'L'"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,SSCG0,PPL1,Fixed to'L'"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 0.--3. " CD5CSL ,Clock domain 5 section bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x0C "SYSC1_APPCKER0,APP clock source enable register 0"
|
|
bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPMB2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " ENCLKTRC ,CNCLKTRC clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " ENCLKATB ,CNCLKATB clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x10 "SYSC1_APPCKER1,APP clock source enable register 1"
|
|
bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x14 "SYSC1_APPCKER2,APP clock source enable register 2"
|
|
bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " ENCLKCD4B0 ,CD4B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x18 "SYSC1_APPCKDIVR0,APP Clock Divider Register 0"
|
|
bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..."
|
|
bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8"
|
|
newline
|
|
bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x1C "SYSC1_APPCKDIVR1,APP Clock Divider Register 1"
|
|
bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x20 "SYSC1_APPCKDIVR2,APP Clock Divider Register 2"
|
|
bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8"
|
|
line.long 0x24 "SYSC1_APPCKDIVR3,APP Clock Divider Register 3"
|
|
bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "SYSC1_APPCKDIVR4,APP Clock Divider Register 4"
|
|
bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
rgroup.long 0x1AC++0x13
|
|
line.long 0x00 "SYSC1_APPCKDIVR5,APP Clock Divider Register 5"
|
|
bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " CD1B0DIV ,CB1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "SYSC1_APPCKDIVR6,APP Clock Divider Register 6"
|
|
bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC1_APPCKDIVR7,APP Clock Divider Register 7"
|
|
bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x0C "SYSC1_APPCKDIVR8,APP Clock Divider Register 8"
|
|
bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x10 "SYSC1_APPCKDIVR9,APP Clock Divider Register 9"
|
|
bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
rgroup.long 0x200++0x27 "STS Profile registers"
|
|
line.long 0x00 "SYSC1_STSCKSELR0,STS Clock Selection Register 0"
|
|
bitfld.long 0x00 28.--31. " HSSPICM ,HSSPI clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x00 24.--27. " HSSPICSL ,HSSPI clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x00 21. " LAPP1ACM ,LAPP1A clock selection status bit" "CD0,PLL0"
|
|
newline
|
|
bitfld.long 0x00 20. " LAPP1ACSL ,LAPP1A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 17. " LAPP0ACM ,LAPP0A clock selection status bit" "CD0,PLL0"
|
|
bitfld.long 0x00 16. " LAPP0ACSL ,LAPP0A clock selection bit" "CD0,PLL0"
|
|
newline
|
|
bitfld.long 0x00 13. " LCP1ACM ,LCP1A clock selection status bit" "CD0,PLL0"
|
|
bitfld.long 0x00 12. " LCP1ACSL ,LCP1A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 9. " LCP0ACM ,LCP0A clock selection status bit" "CD0,PLL0"
|
|
newline
|
|
bitfld.long 0x00 8. " LCP0ACSL ,LCP0A clock selection bit" "CD0,PLL0"
|
|
bitfld.long 0x00 4.--6. " CD0CM ,Clock domain 0 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'"
|
|
bitfld.long 0x00 0.--2. " CD0CSL ,Clock domain 0 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'"
|
|
line.long 0x04 "SYSC1_STSCKSELR1,STS Clock Selection Register 1"
|
|
bitfld.long 0x04 28.--31. " CD4CM ,Domain 4 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 24.--27. " CD4CSL ,Domain 4 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 20.--23. " CD3CM ,Domain 3 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
newline
|
|
bitfld.long 0x04 16.--19. " CD3CSL ,Domain 3 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 12.--15. " CD2CM ,Domain 2 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 8.--11. " CD2CSL ,Domain 2 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " CD1CM ,Domain 1 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
bitfld.long 0x04 0.--3. " CD1CSL ,Domain 1 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x08 "SYSC1_STSCKSELR2,STS Clock Selection Register 2"
|
|
sif (cpu()=="S6J311*")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x08 12.--14. " TRCCM ,TRC clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'"
|
|
newline
|
|
else
|
|
bitfld.long 0x08 12.--14. " TRCCM ,TRC clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,PPL1,Fixed to 'L'"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 8.--10. " TRCCSL ,TRC clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PPL0,SSCG0,,Fixed to 'L'"
|
|
bitfld.long 0x08 4.--7. " CD5CM ,Domain 5 clock selection status bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
newline
|
|
bitfld.long 0x08 0.--3. " CD5CSL ,Domain 5 clock selection bits" "High-speed CR,Low-speed CR,Main,Sub,PLL0,PPL1,PLL2,PLL3,SSCG PLL0,SSCG PLL1,SSCG PPL2,SSCG PPL3,,,,FIxed to'L'"
|
|
line.long 0x0C "SYSC1_STSCKER0,STS Clock Source Enable Register 0"
|
|
bitfld.long 0x0C 31. " ENCLKLAPP1A ,LAPP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ENCLKLAPP0A ,LAPP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " ENCLKLCP1A ,LCP1A clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 28. " ENCLKLCP0A ,LCP0A clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " ENCLKLAPP1 ,LAPP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " ENCLKLAPP0 ,LAPP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " ENCLKLCP1 ,LCP1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " ENCLKLCP0 ,LCP0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " ENCLKLCP ,LCP clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " ENCLKLLPBM2 ,LLPBM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " ENCLKLLPBM ,LLPBM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " ENCLKHAPP1B1 ,HAPP1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 18. " ENCLKHAPP1B0 ,HAPP1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " ENCLKHAPP0A1 ,HAPP0A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " ENCLKHAPP0A0 ,HAPP0A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " ENCLKSYSC1 ,ENCLKSYSC1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " ENCLKEXTBUS ,ENCLKEXTBUS clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " ENCLKMEMC ,ENCLKMEMC clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " ENCLKDMA ,ENCLKDMA clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ENCLKHPM ,ENCLKHPM clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " ENCLKHPM2 ,ENCLKHPM2 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " ENCLKTRC ,ENCLKTRC clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ENCLKDBG ,ENCLKDBG clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " ENCLKATB ,ENCLKATB clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 0. " ENCLKCPU0 ,ENCLKCPU0 clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x10 "SYSC1_STSCKER1,STS Clock Source Enable Register 1"
|
|
bitfld.long 0x10 28. " ENCLKCD3B1 ,CD3B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " ENCLKCD3B0 ,CD3B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " ENCLKCD3A1 ,CD3A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 25. " ENCLKCD3A0 ,CD3A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " ENCLKCD3 ,CD3 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ENCLKCD2B1 ,CD2B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 19. " ENCLKCD2B0 ,CD2B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " ENCLKCD2A1 ,CD2A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " ENCLKCD2A0 ,CD2A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 16. " ENCLKCD2 ,CD2 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " ENCLKCD1B1 ,CD1B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " ENCLKCD1B0 ,CD1B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 10. " ENCLKCD1A1 ,CD1A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " ENCLKCD1A0 ,CD1A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " ENCLKCD1 ,CD1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 0. " ENCLKHSSPI ,HSSPI clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x14 "SYSC1_STSCKER2,STS Clock Source Enable Register 2"
|
|
bitfld.long 0x14 12. " ENCLKCD5B1 ,CD5B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " ENCLKCD5B0 ,CD5B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " ENCLKCD5A1 ,CD5A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 9. " ENCLKCD5A0 ,CD5A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " ENCLKCD5 ,CD5 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " ENCLKCD4B1 ,CD4B1 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " ENCLKCD4B0 ,CD4B0 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ENCLKCD4A1 ,CD4A1 clock oscillation enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " ENCLKCD4A0 ,CD4A0 clock oscillation enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 0. " ENCLKCD4 ,CD4 clock oscillation enable bit" "Disabled,Enabled"
|
|
line.long 0x18 "SYSC1_STSCKDIVR0,STS Clock Divider Register 0"
|
|
bitfld.long 0x18 24.--26. " HPMDIV ,HPM clock frequency divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x18 16.--20. " TRCDIV ,TRC clock divider setting bits" "No division,/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,?..."
|
|
bitfld.long 0x18 12.--13. " DBGDIV ,DBG clock divider setting bits" "No division,/2,/4,/8"
|
|
newline
|
|
bitfld.long 0x18 8.--9. " ATBDIV ,ATB clock divider setting bits" "No division,/2,/4,/8"
|
|
bitfld.long 0x18 0.--4. " SYSDIV ,SYS clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x1C "SYSC1_STSCKDIVR1,STS Clock Divider Register 1"
|
|
bitfld.long 0x1C 28.--31. " HAPP1B1DIV ,HAPP1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 24.--27. " HAPP1B0DIV ,HAPP1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 20.--23. " HAPP0A1DIV ,HAPP0A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x1C 16.--19. " HAPP0A0DIV ,HAPP0A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 4.--7. " SYSC1DIV ,SYSC1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x1C 0.--2. " EXTBUSDIV ,EXTBUS clock divider setting bits" "No division,/2,/4,/8,/16,/32,/64,/128"
|
|
line.long 0x20 "SYSC1_STSCKDIVR2,STS Clock Divider Register 2"
|
|
bitfld.long 0x20 24.--27. " LAPP1DIV ,LAPP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 16.--19. " LAPP0DIV ,LAPP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 8.--11. " LCP1DIV ,LCP1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x20 4.--7. " LCP0DIV ,LCP0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x20 0.--1. " LCPDIV ,LCP clock divider setting bits" "No division,/2,/4,/8"
|
|
line.long 0x24 "SYSC1_STSCKDIVR3,STS Clock Divider Register 3"
|
|
bitfld.long 0x24 24.--28. " LAPP1ADIV ,LAPP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 16.--20. " LAPP0ADIV ,LAPP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
bitfld.long 0x24 8.--12. " LCP1ADIV ,LCP1A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
newline
|
|
bitfld.long 0x24 0.--4. " LCP0ADIV ,LCP0A clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "SYSC1_STSCKDIVR4,STS Clock Divider Register 4"
|
|
bitfld.long 0x00 0.--4. " HSSPIDIV ,HSSPI clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
rgroup.long 0x22C++0x13
|
|
line.long 0x00 "SYSC1_STSCKDIVR5,STS Clock Divider Register 5"
|
|
bitfld.long 0x00 20.--23. " CD1B1DIV ,CD1B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 16.--19. " CD1B0DIV ,CD1B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 12.--15. " CD1A1DIV ,CD1A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " CD1A0DIV ,CD1A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0.--4. " CD1DIV ,CD1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x04 "SYSC1_STSCKDIVR6,STS Clock Divider Register 6"
|
|
bitfld.long 0x04 20.--23. " CD2B1DIV ,CD2B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 16.--19. " CD2B0DIV ,CD2B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 12.--15. " CD2A1DIV ,CD2A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " CD2A0DIV ,CD2A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x04 0.--4. " CD2DIV ,CD2 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x08 "SYSC1_STSCKDIVR7,STS Clock Divider Register 7"
|
|
bitfld.long 0x08 20.--23. " CD3B1DIV ,CD3B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 16.--19. " CD3B0DIV ,CD3B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 12.--15. " CD3A1DIV ,CD3A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x08 8.--11. " CD3A0DIV ,CD3A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x08 0.--4. " CD3DIV ,CD3 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x0C "SYSC1_STSCKDIVR8,STS Clock Divider Register 8"
|
|
bitfld.long 0x0C 20.--23. " CD4B1DIV ,CD4B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 16.--19. " CD4B0DIV ,CD4B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 12.--15. " CD4A1DIV ,CD4A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. " CD4A0DIV ,CD4A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x0C 0.--4. " CD4DIV ,CD4 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
line.long 0x10 "SYSC1_STSCKDIVR9,STS Clock Divider Register 9"
|
|
bitfld.long 0x10 20.--23. " CD5B1DIV ,CD5B1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 16.--19. " CD5B0DIV ,CD5B0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 12.--15. " CD5A1DIV ,CD5A1 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
newline
|
|
bitfld.long 0x10 8.--11. " CD5A0DIV ,CD5A0 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x10 0.--4. " CD5DIV ,CD5 clock divider setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CLOCK SUPERVISOR"
|
|
base ad:0xB0600300
|
|
width 14.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CSVMOCFGR0,Main Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVMOCFGR1,Main Clock Supervisor Setting Register 1"
|
|
sif (!cpuis("S6J311*")&&!cpuis("S6J312?HAA"))
|
|
bitfld.long 0x04 24. " REFCLKSEL ,Reference lock selection bits" "Slow,Fast"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain"
|
|
newline
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
newline
|
|
else
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
endif
|
|
sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA")
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "CSVSOCFGR0,Sub Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVSOCFGR1,Sub clock supervisor setting register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain/Software,Domain"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CSVPLL0CFGR0,PLL0 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVPLL0CFGR1,PLL0 clock supervisor setting register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain,Domain"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA")
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "CSVPLL1CFGR0,PLL1 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVPLL1CFGR1,PLL1 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "CSVPLL2CFGR0,PLL2 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVPLL2CFGR1,PLL2 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "CSVPLL3CFGR0,PLL3 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVPLL3CFGR1,PLL3 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
endif
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "CSVSP0CFGR0,SSCG PLL0 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVSP0CFGR1,SSCG PLL0 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Domain,Domain"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
sif !cpuis("S6J311*")&&!cpuis("S6J312?HAA")
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "CSVSP1CFGR0,SSCG PLL1 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVSP1CFGR1,SSCG PLL1 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "CSVSP2CFGR0,SSCG PLL2 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVSP2CFGR1,SSCG PLL2 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "CSVSP3CFGR0,SSCG PLL3 Clock Supervisor Setting Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. " UPTHR ,Upper-limit threshold value bits"
|
|
hexmask.long.word 0x00 0.--9. 1. " LOWTHR ,Lower-limit threshold value bits"
|
|
line.long 0x04 "CSVSP3CFGR1,SSCG PLL3 Clock Supervisor Setting Register 1"
|
|
bitfld.long 0x04 16. " JDGSEL ,Judgment selection bit" "Reset,Interrupt"
|
|
hexmask.long.word 0x04 0.--9. 1. " REFCLKWND ,Reference clock count period bits"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&!cpuis("S6J312?HAA")
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "CSVFCRCFGR,Fast CR Clock Supervisor Setting Register"
|
|
bitfld.long 0x00 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128"
|
|
line.long 0x04 "CSVSCRCFGR,Slow CR Clock Supervisor Setting Register"
|
|
bitfld.long 0x04 0.--2. " REFCLKDIV ,Reference clock division setting bits" "/4,/8,/16,/32,/64,/128,/128,/128"
|
|
endif
|
|
sif (!cpuis("S6J33*"))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CSVOUTER,Clock Supervisor Output Enable Register"
|
|
bitfld.long 0x00 0. " OUTEN ,Clock supervisor output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CSVTESTR,Clock Supervisor Test Register"
|
|
sif (cpu()!="S6J311*")&&!cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 25. " SCRCLKGATE ,SCR CR clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 24. " FCRCLKGATE ,FCR CR clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 19. " SP3CLKGATE ,SSCG PLL3 clock supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 18. " SP2CLKGATE ,SSCG PLL2 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 17. " SP1CLKGATE ,SSCG PLL1 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 16. " SP0CLKGATE ,SSCG PLL0 clock supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 11. " PLL3CLKGATE ,PLL3 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 10. " PLL2CLKGATE ,PLL2 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 9. " PLL1CLKGATE ,PLL1 clock supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 8. " PLL0CLKGATE ,PLL0 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 3. " SO1CLKGATE ,Sub clock 1 supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 2. " MO1CLKGATE ,Main clock 1 supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 1. " SO0CLKGATE ,Sub clock 0 supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 0. " MO0CLKGATE ,Main clock 0 supervisor test bit" "Normal,Gating"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 19. " SP3CLKGATE ,SSCG PLL3 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 18. " SP2CLKGATE ,SSCG PLL2 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 17. " SP1CLKGATE ,SSCG PLL1 clock supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 16. " SP0CLKGATE ,SSCG PLL0 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 11. " PLL3CLKGATE ,PLL3 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 10. " PLL2CLKGATE ,PLL2 clock supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 9. " PLL1CLKGATE ,PLL1 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 8. " PLL0CLKGATE ,PLL0 clock supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 3. " SO1CLKGATE ,Sub clock 1 supervisor test bit" "Normal,Gating"
|
|
newline
|
|
bitfld.long 0x00 2. " MO1CLKGATE ,Main clock 1 supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 1. " SO0CLKGATE ,Sub clock 0 supervisor test bit" "Normal,Gating"
|
|
bitfld.long 0x00 0. " MO0CLKGATE ,Main clock 0 supervisor test bit" "Normal,Gating"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SOURCE CLOCK TIMER"
|
|
base ad:0xB0600400
|
|
width 12.
|
|
group.long 0x00++0x0F "High-speed CR Clock Timer Registers"
|
|
line.long 0x00 "FCRCTTRGR,High-speed CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start"
|
|
line.long 0x04 "FCRCTCNTR,High-speed CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shot,Continuous"
|
|
line.long 0x08 "FCRCTCPR,High-speed CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
line.long 0x0C "FCRCTSTR,High-speed CR Clock Timer Status Register"
|
|
rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
group.long 0x80++0x0f "Low-speed CR Clock Timer Register"
|
|
line.long 0x00 "SCRCTTRGR,Low-speed CR Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start"
|
|
line.long 0x04 "SCRCTCNTR,Low-Speed CR Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous"
|
|
line.long 0x08 "SCRCTCPR,Low-speed CR Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
line.long 0x0C "SCRCTSTR,Low-speed CR Clock Timer Status Register"
|
|
rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
group.long 0x100++0x0F "Main Clock Timer Register"
|
|
line.long 0x00 "MOCTTRGR,Main Clock Timer Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Chang/Start"
|
|
line.long 0x04 "MOCTCNTR,Main Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous"
|
|
line.long 0x08 "MOCTCPR,Main Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
line.long 0x0C "MOCTSTR,Main Clock Timer Status Register"
|
|
rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
group.long 0x180++0x0F "Sub Clock Timer Registers"
|
|
line.long 0x00 "SOCTTRGR,Sub Clock Timer Trigger Register"
|
|
bitfld.long 0x00 2. " TCLR ,Timer clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CSTOP ,Count stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CGCPT ,Timer setting capture bit" "No effect,Change/Start"
|
|
line.long 0x04 "SOCTCNTR,Sub Clock Timer Control Register"
|
|
bitfld.long 0x04 1. " DBGEN ,Debug enable bit" "Continue,Stopped"
|
|
bitfld.long 0x04 0. " MODE ,Mode control bit" "Single-shoot,Continuous"
|
|
line.long 0x08 "SOCTCPR,Sub Clock Timer Compare Prescaler Register"
|
|
bitfld.long 0x08 16.--19. " PSCL ,Prescale bits" "No division,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
hexmask.long.word 0x08 0.--15. 1. " CMPR ,Compare value bits"
|
|
line.long 0x0C "SOCTSTR,Sub Clock Timer Status Register"
|
|
rbitfld.long 0x0C 2. " BUSY ,Setting update status bit" "Completed,In progress"
|
|
rbitfld.long 0x0C 1. " TST ,Timer status bit" "Stopped,Operating"
|
|
setclrfld.long 0x0C 0. 0x10 0. 0x14 0. " INTF_SET/CLR ,Interrupt flag bit" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (REAL TIME CLOCK)"
|
|
base ad:0xB0618000
|
|
width 14.
|
|
if ((per.l(ad:0xB0618000)&0x100)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WTCR,Timer Control Register"
|
|
bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update"
|
|
bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..."
|
|
bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow RC"
|
|
bitfld.long 0x00 10. " ENUP ,Enable/Disable calibration value update" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " MTRG ,Manual trigger for calibration" "No,Yes"
|
|
bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow RC,?..."
|
|
bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate"
|
|
newline
|
|
bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update"
|
|
bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-second counter"
|
|
bitfld.long 0x00 0. " ST ,Start" "Stopped,Started"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "WTCR,Timer Control Register"
|
|
bitfld.long 0x00 15. " UPCAL ,Update calibration period counter" "Completed,Update"
|
|
bitfld.long 0x00 12.--14. " SCAL ,Scale calibrated value" "No change,*2,*4,*8,*16,?..."
|
|
bitfld.long 0x00 11. " CCKSEL ,Clock select for calibration" "Sub,Slow RC"
|
|
newline
|
|
bitfld.long 0x00 8. " ACAL ,Automatic calibration" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " RCKSEL ,Clock select for RTC" "Main,Sub,Slow RC,?..."
|
|
bitfld.long 0x00 3. " CSM ,Clock switching mode" "Precise,Immediate"
|
|
newline
|
|
bitfld.long 0x00 2. " UPDT ,Update" "Completed,Update"
|
|
bitfld.long 0x00 1. " OE ,Output enable" "General purpose,Sub-second counter"
|
|
bitfld.long 0x00 0. " ST ,Start" "Stopped,Started"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "WTSR,Timer Status Register"
|
|
rbitfld.long 0x00 8. " RUNC ,Run calibration" "Inactive,In progress"
|
|
rbitfld.long 0x00 7. " CLK_STS ,Clock switching status" "Inactive,In progress"
|
|
bitfld.long 0x00 1. " CSF ,Clock switched flag" "Not switched,Switched"
|
|
rbitfld.long 0x00 0. " RUN ,RUN" "Inactive,Active"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "WTSR,Timer Status Register"
|
|
bitfld.long 0x00 8. " RUNC ,Run calibration" "Inactive,In progress"
|
|
bitfld.long 0x00 1. " CSF ,Clock switched flag" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " RUN ,RUN" "Inactive,Active"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "WINS_SET/CLR,Interrupt Status Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CALD_SET/CLR ,Calibration done" "In progress,Done"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CFD_SET/CLR ,Calibration failure detection" "No failure,Failure"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DAY_SET/CLR ,Day flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " HOUR_SET/CLR ,Hour flag" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " MIN_SET/CLR ,Minute flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " SEC_SET/CLR ,Second flag" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SUBSEC_SET/CLR ,Sub-second flag" "No interrupt,Interrupt"
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "WTBR,Sub-second Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " WTBR ,Sub-second value"
|
|
line.long 0x04 "WRT,Real Time Register"
|
|
bitfld.long 0x04 16.--20. " WTHR ,Hour register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
bitfld.long 0x04 8.--13. " WTMR ,Minute register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
bitfld.long 0x04 0.--5. " WTSR ,Second register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,?..."
|
|
line.long 0x08 "RTR1,Real Time Clock Real Time Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " WTDR ,Date bits"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CNTCAL,Calibration Clock Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CNTCAL ,Calibration clock counter value"
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "CNTPCAL,Calibration Clock Period Counter Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " CNTPCAL ,Calibration clock period register"
|
|
line.long 0x04 "DURMW,Calibration Duration Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DURMW ,Calibration duration value"
|
|
line.long 0x08 "CALTRG,Calibration Trigger Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " CALTRG ,Calibration trigger counter value"
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DEBUG,Debug Register"
|
|
bitfld.long 0x00 0. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("S6J312?HAA")&&!cpuis("S6J311?HAA")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PWUTRGCR,Partial Wake Up Trigger Control Register"
|
|
hexmask.long.tbyte 0x00 8.--25. 1. " C8MRL ,Reload value setting bit of 8ms counter"
|
|
bitfld.long 0x00 4. " MD ,Reload value setting bit to 8ms counter" "Manual operation,Sub-second"
|
|
bitfld.long 0x00 0.--2. " SEL ,Reload value setting bit to trigger counter" "8ms,16ms,24ms,32ms,40ms,48ms,56ms,64sms"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PWUTRGSR,Partial Wake Up Trigger Status Register"
|
|
bitfld.long 0x00 0. " BUSY ,Busy status" "Idle,Busy"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CR CALIBRATION"
|
|
base ad:0xB0688400
|
|
width 8.
|
|
group.word 0x00++0x03
|
|
line.word 0x00 "CUCR1,Correction Unit Register 1"
|
|
bitfld.word 0x00 4. " STRT ,Correction start" "Aborted,Started"
|
|
setclrfld.word 0x00 1. 0x00 1. 0x08 1. " INT_SET/CLR ,Interrupt" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " INTEN ,Enabling interrupts" "Disabled,Enabled"
|
|
line.word 0x02 "CUTD1,CR Clock Timer Data Register 1"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CUTR1,Main Oscillation Timer Data Register 1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer data"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BURIF (BACKUP RAM INTERFACE)"
|
|
base ad:0xB0680000
|
|
width 11.
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "UNLOCK,Unlock register"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "STATUS,Status register"
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " TM_ESKPG ,ECC generation function disable status bit" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " TM_ESKPC ,ECC test function disable status bit" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TM_EEACC ,ECC area access enable status bit" "Not allowed,Allowed"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
endif
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "DEEAR,Double-bit ECC error address register"
|
|
hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Double-bit error occurrence address bits"
|
|
rgroup.word 0xA++0x1
|
|
line.word 0x00 "SEEAR,Single-bit ECC error address register"
|
|
hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits"
|
|
if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "EFEAR,ECC pseudo-error generation address register"
|
|
hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits"
|
|
group.byte 0xF++0x0
|
|
line.byte 0x00 "EECSR,ECC error control register"
|
|
bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred"
|
|
group.tbyte 0x10++0x2
|
|
line.tbyte 0x00 "EFECR,ECC pseudo-error generation control register"
|
|
bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled"
|
|
hexmask.tbyte.byte 0x00 8.--15. 1. " EY ,Pseudo-error generation byte setting bits"
|
|
hexmask.tbyte.byte 0x00 0.--7. 1. " EI ,Pseudo-error generation bit setting bits"
|
|
else
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x00 "EFEAR,ECC pseudo-error generation address register"
|
|
hexmask.word 0x00 0.--14. 1. " ERR_ADDR ,Single-bit error occurrence address bits"
|
|
rgroup.byte 0xF++0x0
|
|
line.byte 0x00 "EECSR,ECC error control register"
|
|
bitfld.byte 0x00 3. " DEIE ,Double-bit-error-caused interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DEI ,Double-bit error occurrence bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " SEIE ,Single-bit-error-caused interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not occurred,Occurred"
|
|
rgroup.tbyte 0x10++0x2
|
|
line.tbyte 0x00 "EFECR,ECC pseudo-error generation control register"
|
|
bitfld.tbyte 0x00 16. " FERR ,Pseudo-error generation enable bit" "Disabled,Enabled"
|
|
hexmask.tbyte.byte 0x00 8.--15. 1. " EY ,Pseudo-error generation byte setting bits"
|
|
hexmask.tbyte.byte 0x00 0.--7. 1. " EI ,Pseudo-error generation bit setting bits"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00)
|
|
group.byte 0x13++0x0
|
|
line.byte 0x00 "EPDCR,ECC data path control register"
|
|
bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes"
|
|
bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes"
|
|
bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0x13++0x0
|
|
line.byte 0x00 "EPDCR,ECC data path control register"
|
|
bitfld.byte 0x00 2. " SKPG ,ECC generation function disable bit" "No,Yes"
|
|
bitfld.byte 0x00 1. " SKPC ,ECC test function disable bit" "No,Yes"
|
|
bitfld.byte 0x00 0. " EACC ,ECC area access enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x14++0x0
|
|
line.byte 0x00 "ECCTKCCR,ECC test mode key code control register"
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 2. " TM_ESKPG ,ECC generation function skip enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TM_ESKPC ,ECC test function skip enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TM_EEACC ,ECC area access enable bit" "Data area,ECC area"
|
|
endif
|
|
if (((per.l(ad:0xB0680000+0x18))&0xE0000000)!=0x00)
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "TEAR0,Test error address register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "TEAR0,Test error address register 0"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if (((per.l(ad:0xB0680000+0x1C))&0xE0000000)!=0x00)
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "TEAR1,Test error address register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "TEAR1,Test error address register 1"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if (((per.l(ad:0xB0680000+0x20))&0xE0000000)!=0x00)
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TEAR2,Test error address register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
else
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TEAR2,Test error address register 2"
|
|
bitfld.long 0x00 29.--31. " TER ,Diagnosis error factor indication" "No error,March,Checker,,Unique,?..."
|
|
endif
|
|
if (((per.l(ad:0xB0680000+0x04))&0x100)==0x00)
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TASAR,Test start address register"
|
|
hexmask.word 0x00 0.--14. 1. " SADDR ,RAM diagnosis start address"
|
|
group.word 0x26++0x1
|
|
line.word 0x00 "TAEAR,Test end address register"
|
|
hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TTCR,Test diagnosis function register"
|
|
rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or fewer,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TEI ,Error occurrence during diagnosis" "No error,Error"
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " TTYP[1] ,Checker diagnosis not performed/performed" "Not performed,Performed"
|
|
bitfld.word 0x00 1. " TTYP[0] ,March diagnosis not performed/performed" "Not performed,Performed"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
group.byte 0x2A++0x0
|
|
line.byte 0x00 "TICR,Test initialization function register"
|
|
bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed"
|
|
bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
group.byte 0x2B++0x0
|
|
line.byte 0x00 "TFECR,Test pseudo-error control register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error"
|
|
bitfld.byte 0x00 1. " ETYP[1] ,Pseudo-error generation processing specification (checker)" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " ETYP[0] ,Pseudo-error generation processing specification (march)" "No error,Error"
|
|
group.byte 0x2C++0x0
|
|
line.byte 0x00 "TKCCR,Test key code control register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis,"
|
|
else
|
|
textline " "
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis,"
|
|
endif
|
|
wgroup.byte 0x2F++0x0
|
|
line.byte 0x00 "TSRCR,Test software reset generation control register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "No reset,Reset"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x00 "EVENTCLR,Event clear register"
|
|
bitfld.long 0x00 26. " DEICLR ,Double-bit error occurrence clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 24. " SEICLR ,Single-bit error occurrence clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 18. " ICICLR ,RAM initialization end clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TEICLR ,Error occurrence during diagnosis" "No effect,Clear"
|
|
bitfld.long 0x00 4. " TCICLR ,Diagnosis end" "No effect,Clear"
|
|
else
|
|
rgroup.word 0x24++0x1
|
|
line.word 0x00 "TASAR,Test start address register"
|
|
hexmask.word 0x00 0.--14. 1. " SADDR ,RAM diagnosis start address"
|
|
rgroup.word 0x26++0x1
|
|
line.word 0x00 "TAEAR,Test end address register"
|
|
hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address"
|
|
rgroup.word 0x28++0x1
|
|
line.word 0x00 "TTCR,Test diagnosis function register"
|
|
bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or fewer,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TEI ,Error occurrence during diagnosis" "No error,Error"
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end factor interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TTYP[2] ,Unique diagnosis not performed/performed" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " TTYP[1] ,Checker diagnosis not performed/performed" "Not performed,Performed"
|
|
bitfld.word 0x00 1. " TTYP[0] ,March diagnosis not performed/performed" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
rgroup.byte 0x2A++0x0
|
|
line.byte 0x00 "TICR,Test initialization function register"
|
|
bitfld.byte 0x00 3. " ICIE ,RAM initialization end factor interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ICI ,RAM initialization end" "Not completed,Completed"
|
|
bitfld.byte 0x00 1. " ITYP ,RAM initialization contents specification" "0's,1's"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
rgroup.byte 0x2B++0x0
|
|
line.byte 0x00 "TFECR,Test pseudo-error control register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Pseudo-error generation processing specification (unique)" "No error,Error"
|
|
bitfld.byte 0x00 1. " ETYP[1] ,Pseudo-error generation processing specification (checker)" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " ETYP[0] ,Pseudo-error generation processing specification (march)" "No error,Error"
|
|
rgroup.byte 0x2C++0x0
|
|
line.byte 0x00 "TKCCR,Test key code control register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis,"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation specification" "Forced,Act. of initialization,Act. of diagnosis,"
|
|
endif
|
|
hgroup.byte 0x2F++0x0
|
|
hide.byte 0x00 "TSRCR,Test software reset generation control register"
|
|
hgroup.long 0x30++0x3
|
|
hide.long 0x00 "EVENTCLR,Event clear register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "EXTERNAL INTERRUPT"
|
|
base ad:0xB0620000
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "ENIR_SET/CLR,External interrupt enable register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " EN_set/clr_[31] ,External interrupt enable bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,External interrupt enable bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,External interrupt enable bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,External interrupt enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,External interrupt enable bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,External interrupt enable bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,External interrupt enable bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,External interrupt enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,External interrupt enable bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,External interrupt enable bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,External interrupt enable bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,External interrupt enable bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,External interrupt enable bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,External interrupt enable bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,External interrupt enable bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,External interrupt enable bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,External interrupt enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,External interrupt enable bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,External interrupt enable bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,External interrupt enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,External interrupt enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,External interrupt enable bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,External interrupt enable bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,External interrupt enable bit 08" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,External interrupt enable bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,External interrupt enable bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,External interrupt enable bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,External interrupt enable bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,External interrupt enable bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,External interrupt enable bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,External interrupt enable bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,External interrupt enable bit 00" "Disabled,Enabled"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "EIRR,External factor register"
|
|
bitfld.long 0x00 31. " ER_[31] ,External interrupt factor detection bit 31" "Not detected,Detected"
|
|
bitfld.long 0x00 30. " [30] ,External interrupt factor detection bit 30" "Not detected,Detected"
|
|
bitfld.long 0x00 29. " [29] ,External interrupt factor detection bit 29" "Not detected,Detected"
|
|
bitfld.long 0x00 28. " [28] ,External interrupt factor detection bit 28" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,External interrupt factor detection bit 27" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " [26] ,External interrupt factor detection bit 26" "Not detected,Detected"
|
|
bitfld.long 0x00 25. " [25] ,External interrupt factor detection bit 25" "Not detected,Detected"
|
|
bitfld.long 0x00 24. " [24] ,External interrupt factor detection bit 24" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,External interrupt factor detection bit 23" "Not detected,Detected"
|
|
bitfld.long 0x00 22. " [22] ,External interrupt factor detection bit 22" "Not detected,Detected"
|
|
bitfld.long 0x00 21. " [21] ,External interrupt factor detection bit 21" "Not detected,Detected"
|
|
bitfld.long 0x00 20. " [20] ,External interrupt factor detection bit 20" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,External interrupt factor detection bit 19" "Not detected,Detected"
|
|
bitfld.long 0x00 18. " [18] ,External interrupt factor detection bit 18" "Not detected,Detected"
|
|
bitfld.long 0x00 17. " [17] ,External interrupt factor detection bit 17" "Not detected,Detected"
|
|
bitfld.long 0x00 16. " [16] ,External interrupt factor detection bit 16" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,External interrupt factor detection bit 15" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " [14] ,External interrupt factor detection bit 14" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " [13] ,External interrupt factor detection bit 13" "Not detected,Detected"
|
|
bitfld.long 0x00 12. " [12] ,External interrupt factor detection bit 12" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,External interrupt factor detection bit 11" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " [10] ,External interrupt factor detection bit 10" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " [9] ,External interrupt factor detection bit 09" "Not detected,Detected"
|
|
bitfld.long 0x00 8. " [8] ,External interrupt factor detection bit 08" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,External interrupt factor detection bit 07" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " [6] ,External interrupt factor detection bit 06" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " [5] ,External interrupt factor detection bit 05" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " [4] ,External interrupt factor detection bit 04" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,External interrupt factor detection bit 03" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " [2] ,External interrupt factor detection bit 02" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " [1] ,External interrupt factor detection bit 01" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " [0] ,External interrupt factor detection bit 00" "Not detected,Detected"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "EIRCR,External interrupt factor clear register"
|
|
eventfld.long 0x00 31. " ERC_[31] ,External interrupt factor clear bit 31" ",Clear"
|
|
eventfld.long 0x00 30. " [30] ,External interrupt factor clear bit 30" ",Clear"
|
|
eventfld.long 0x00 29. " [29] ,External interrupt factor clear bit 29" ",Clear"
|
|
eventfld.long 0x00 28. " [28] ,External interrupt factor clear bit 28" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 27. " [27] ,External interrupt factor clear bit 27" ",Clear"
|
|
eventfld.long 0x00 26. " [26] ,External interrupt factor clear bit 26" ",Clear"
|
|
eventfld.long 0x00 25. " [25] ,External interrupt factor clear bit 25" ",Clear"
|
|
eventfld.long 0x00 24. " [24] ,External interrupt factor clear bit 24" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 23. " [23] ,External interrupt factor clear bit 23" ",Clear"
|
|
eventfld.long 0x00 22. " [22] ,External interrupt factor clear bit 22" ",Clear"
|
|
eventfld.long 0x00 21. " [21] ,External interrupt factor clear bit 21" ",Clear"
|
|
eventfld.long 0x00 20. " [20] ,External interrupt factor clear bit 20" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 19. " [19] ,External interrupt factor clear bit 19" ",Clear"
|
|
eventfld.long 0x00 18. " [18] ,External interrupt factor clear bit 18" ",Clear"
|
|
eventfld.long 0x00 17. " [17] ,External interrupt factor clear bit 17" ",Clear"
|
|
eventfld.long 0x00 16. " [16] ,External interrupt factor clear bit 16" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 15. " [15] ,External interrupt factor clear bit 15" ",Clear"
|
|
eventfld.long 0x00 14. " [14] ,External interrupt factor clear bit 14" ",Clear"
|
|
eventfld.long 0x00 13. " [13] ,External interrupt factor clear bit 13" ",Clear"
|
|
eventfld.long 0x00 12. " [12] ,External interrupt factor clear bit 12" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,External interrupt factor clear bit 11" ",Clear"
|
|
eventfld.long 0x00 10. " [10] ,External interrupt factor clear bit 10" ",Clear"
|
|
eventfld.long 0x00 9. " [9] ,External interrupt factor clear bit 09" ",Clear"
|
|
eventfld.long 0x00 8. " [8] ,External interrupt factor clear bit 08" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 7. " [7] ,External interrupt factor clear bit 07" ",Clear"
|
|
eventfld.long 0x00 6. " [6] ,External interrupt factor clear bit 06" ",Clear"
|
|
eventfld.long 0x00 5. " [5] ,External interrupt factor clear bit 05" ",Clear"
|
|
eventfld.long 0x00 4. " [4] ,External interrupt factor clear bit 04" ",Clear"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,External interrupt factor clear bit 03" ",Clear"
|
|
eventfld.long 0x00 2. " [2] ,External interrupt factor clear bit 02" ",Clear"
|
|
eventfld.long 0x00 1. " [1] ,External interrupt factor clear bit 01" ",Clear"
|
|
eventfld.long 0x00 0. " [0] ,External interrupt factor clear bit 00" ",Clear"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "NFER_SET/CLR,Noise filter enable register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " NFE_set/clr_[31] ,Noise filter enable bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,Noise filter enable bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,Noise filter enable bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,Noise filter enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,Noise filter enable bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,Noise filter enable bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,Noise filter enable bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,Noise filter enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,Noise filter enable bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,Noise filter enable bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,Noise filter enable bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,Noise filter enable bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,Noise filter enable bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,Noise filter enable bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,Noise filter enable bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,Noise filter enable bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,Noise filter enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,Noise filter enable bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,Noise filter enable bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,Noise filter enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,Noise filter enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,Noise filter enable bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 09. 0x08 09. " [9] ,Noise filter enable bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 08. 0x08 08. " [8] ,Noise filter enable bit 08" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 07. 0x08 07. " [7] ,Noise filter enable bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 06. 0x08 06. " [6] ,Noise filter enable bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 05. 0x08 05. " [5] ,Noise filter enable bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 04. 0x08 04. " [4] ,Noise filter enable bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 03. 0x08 03. " [3] ,Noise filter enable bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 02. 0x08 02. " [2] ,Noise filter enable bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 01. 0x08 01. " [1] ,Noise filter enable bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 00. 0x08 00. " [0] ,Noise filter enable bit 00" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "ELVR0,External interrupt level register"
|
|
bitfld.long 0x00 28.--30. " LCBA[7] ,INT7 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 24.--26. " [6] ,INT6 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 20.--22. " [5] ,INT5 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 16.--18. " [4] ,INT4 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " [3] ,INT3 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 8.--10. " [2] ,INT2 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 4.--6. " [1] ,INT1 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 0.--2. " [0] ,INT0 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ELVR1,External interrupt level register"
|
|
bitfld.long 0x00 28.--30. " LCBA[7] ,INT15 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 24.--26. " [6] ,INT14 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 20.--22. " [5] ,INT13 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 16.--18. " [4] ,INT12 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " [3] ,INT11 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 8.--10. " [2] ,INT10 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 4.--6. " [1] ,INT9 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 0.--2. " [0] ,INT8 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J311?JAA")&&!cpuis("S6J312?HAA")
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "ELVR2,External interrupt level register"
|
|
bitfld.long 0x00 28.--30. " LCBA[7] ,INT23 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 24.--26. " [6] ,INT22 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 20.--22. " [5] ,INT21 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 16.--18. " [4] ,INT20 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " [3] ,INT19 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 8.--10. " [2] ,INT18 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 4.--6. " [1] ,INT17 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 0.--2. " [0] ,INT16 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "ELVR3,External interrupt level register"
|
|
bitfld.long 0x00 28.--30. " LCBA[7] ,INT31 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 24.--26. " [6] ,INT30 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 20.--22. " [5] ,INT29 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 16.--18. " [4] ,INT28 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " [3] ,INT27 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 8.--10. " [2] ,INT26 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 4.--6. " [1] ,INT25 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
bitfld.long 0x00 0.--2. " [0] ,INT24 interrupt level setting" "L level,H level,Rising,Falling,Both,Both,Both,Both"
|
|
endif
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "NMIR,Non maskable interrupt register"
|
|
bitfld.long 0x00 8. " NMICLR ,Non maskable interrupt clear bit" ",Clear"
|
|
rbitfld.long 0x00 0. " NMIINT ,Non maskable interrupt request detection bit" "Not detected,Detected"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "DRER_SET/CLR,DMA request enable register"
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " DRE_set/clr_[31] ,DMA request enable bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,DMA request enable bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,DMA request enable bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,DMA request enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,DMA request enable bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,DMA request enable bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,DMA request enable bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,DMA request enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,DMA request enable bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,DMA request enable bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,DMA request enable bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,DMA request enable bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,DMA request enable bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,DMA request enable bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,DMA request enable bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,DMA request enable bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,DMA request enable bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,DMA request enable bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,DMA request enable bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,DMA request enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,DMA request enable bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,DMA request enable bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x04 09. 0x08 09. " [9] ,DMA request enable bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x04 08. 0x08 08. " [8] ,DMA request enable bit 08" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x04 07. 0x08 07. " [7] ,DMA request enable bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x04 06. 0x08 06. " [6] ,DMA request enable bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x04 05. 0x08 05. " [5] ,DMA request enable bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x04 04. 0x08 04. " [4] ,DMA request enable bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 03. 0x08 03. " [3] ,DMA request enable bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x04 02. 0x08 02. " [2] ,DMA request enable bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 01. 0x08 01. " [1] ,DMA request enable bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 00. 0x08 00. " [0] ,DMA request enable bit 00" "Disabled,Enabled"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "DRFR,DMA request flag register"
|
|
bitfld.long 0x00 31. " DRF_[31] ,DMA request detection bit 31" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,DMA request detection bit 30" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,DMA request detection bit 29" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,DMA request detection bit 28" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,DMA request detection bit 27" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " [26] ,DMA request detection bit 26" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,DMA request detection bit 25" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,DMA request detection bit 24" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,DMA request detection bit 23" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,DMA request detection bit 22" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,DMA request detection bit 21" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,DMA request detection bit 20" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,DMA request detection bit 19" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,DMA request detection bit 18" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,DMA request detection bit 17" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,DMA request detection bit 16" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,DMA request detection bit 15" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,DMA request detection bit 14" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,DMA request detection bit 13" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,DMA request detection bit 12" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,DMA request detection bit 11" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,DMA request detection bit 10" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,DMA request detection bit 09" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,DMA request detection bit 08" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,DMA request detection bit 07" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,DMA request detection bit 06" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,DMA request detection bit 05" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,DMA request detection bit 04" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,DMA request detection bit 03" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,DMA request detection bit 02" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,DMA request detection bit 01" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,DMA request detection bit 00" "Not requested,Requested"
|
|
width 0x0B
|
|
tree.end
|
|
tree "HWDT (HARDWARE WATCHDOG TIMER)"
|
|
base ad:0xB060C000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROT,Hardware Watchdog Protection Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Hardware Watchdog Counter Register"
|
|
if ((per.l(ad:0xB060C000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Hardware Watchdog Reset Factor Register"
|
|
bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No reset,Reset"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Hardware Watchdog Reset Factor Register"
|
|
bitfld.long 0x00 4. " RSTCAUSE4 ,Reset factor bit 4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RSTCAUSE3 ,Reset factor bit 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " RSTCAUSE2 ,Reset factor bit 2" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " RSTCAUSE1 ,Reset factor bit 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RSTCAUSE0 ,Reset factor bit 0" "No reset,Reset"
|
|
endif
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Hardware Watchdog Trigger 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Hardware Watchdog Trigger 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Hardware Watchdog Trigger 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Hardware Watchdog Trigger 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
endif
|
|
if ((per.l(ad:0xB060C000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT,Hardware Watchdog Interrupt"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated"
|
|
rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
sif cpuis("S6J342*")||cpuis("S6J351C*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
else
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
endif
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits"
|
|
line.long 0x04 "TRG1CFG,Hardware watchdog trigger 1 configuration register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits"
|
|
line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
endif
|
|
sif (cpuis("S6J33*"))||cpuis("S6J342*")||cpuis("S6J351C*")
|
|
if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed"
|
|
newline
|
|
rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" ",Enabled"
|
|
rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed"
|
|
newline
|
|
rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock"
|
|
newline
|
|
rbitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub Clock,Main Clock"
|
|
newline
|
|
rbitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INT,Hardware Watchdog Interrupt"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Interrupt"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated"
|
|
bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
else
|
|
sif (cpuis("S6J33*"))
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Hardware Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Cleared"
|
|
endif
|
|
endif
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "TRG0CFG,Hardware Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits"
|
|
line.long 0x04 "TRG1CFG,Hardware Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits"
|
|
line.long 0x08 "RUNLLS,Hardware Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Hardware Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Hardware Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Hardware Watchdog Upper Limit PSS Setting Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Hardware Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
endif
|
|
sif (cpuis("S6J33*"))||cpuis("S6J342*")||cpuis("S6J351C*")
|
|
if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,High-Speed,Low-Speed"
|
|
newline
|
|
bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" ",Enabled"
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock"
|
|
newline
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xB060C000+0x48)&0x02)==0x02)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock"
|
|
newline
|
|
bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-Speed,Low-Speed,Sub clock,Main clock"
|
|
newline
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x4C++0x0F
|
|
line.long 0x00 "RUNLLC,Hardware Watchdog Lower Limit RUN Current Register"
|
|
line.long 0x04 "RUNULC,Hardware Watchdog Upper Limit RUN Current Register"
|
|
line.long 0x08 "PSSLLC,Hardware Watchdog Lower Limit PSS Current Register"
|
|
line.long 0x0C "PSSULC,Hardware Watchdog Upper Limit PSS Current Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SWDT (SOFTWARE WATCHDOG TIMER)"
|
|
base ad:0xB0308000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PROT,Software Watchdog Protection Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Software Watchdog Counter Register"
|
|
if ((per.l(ad:0xB0308000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register"
|
|
bitfld.long 0x00 4. " RSTCAUSE_[4] ,Reset factor bit 4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " [3] ,Reset factor bit 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Reset factor bit 2" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Reset factor bit 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Reset factor bit 0" "No reset,Reset"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "RSTCAUSE,Software Watchdog Reset Factor Register"
|
|
bitfld.long 0x00 4. " RSTCAUSE_[4] ,Reset factor bit 4" "No reset,Reset"
|
|
bitfld.long 0x00 3. " [3] ,Reset factor bit 3" "No reset,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Reset factor bit 2" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Reset factor bit 1" "No reset,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Reset factor bit 0" "No reset,Reset"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRG0,Software Watchdog Trigger 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0 ,Watchdog trigger 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TRG1,Software Watchdog Trigger 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG1 ,Watchdog trigger 1"
|
|
if ((per.l(ad:0xB0308000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Generated"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated"
|
|
rbitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
sif cpuis("S6J342*")||cpuis("S6J351C*")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
else
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Clear"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
endif
|
|
group.long 0x2C++0x17
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits"
|
|
line.long 0x04 "TRG1CFG,Software watchdog trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits"
|
|
line.long 0x08 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Software watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Software watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Software watchdog Upper Limit PSS Setting Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Software Watchdog Reset Delay Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
endif
|
|
if ((per.l(ad:0xB0308000+0x48)&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "INT,Software Watchdog Interrupt"
|
|
bitfld.long 0x00 17. " RSTEN ,Reset/NMI enable bit" "NMI,Interrupt"
|
|
bitfld.long 0x00 16. " IRQEN ,Prior warning interrupt enable bit" "Not generated,Generated"
|
|
bitfld.long 0x00 1. " NMIFLAG ,NMI flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x00 0. " IRQFLAG ,IRQ flag" "Not detected,Detected"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
else
|
|
sif (cpuis("S6J33*"))
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Clear"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTCLR,Software Watchdog Interrupt Clear Register"
|
|
bitfld.long 0x00 1. " NMICLR ,NMI clear bit" ",Cleared"
|
|
bitfld.long 0x00 0. " IRQCLR ,Prior warning interrupt clear bit" ",Cleared"
|
|
endif
|
|
endif
|
|
rgroup.long 0x2C++0x17
|
|
line.long 0x00 "TRG0CFG,Software Watchdog Trigger 0 Configuration Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDGTRG0CFG ,Watchdog trigger 0 configuration bits"
|
|
line.long 0x04 "TRG1CFG,Software Watchdog Trigger 1 Configuration Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " WDGTRG1CFG ,Watchdog trigger 1 configuration bits"
|
|
line.long 0x08 "RUNLLS,Software Watchdog Lower Limit RUN Setting Register"
|
|
line.long 0x0C "RUNULS,Software Watchdog Upper Limit RUN Setting Register"
|
|
line.long 0x10 "PSSLLS,Software Watchdog Lower Limit PSS Setting Register"
|
|
line.long 0x14 "PSSULS,Software Watchdog Upper Limit PSS Setting Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RSTDLY,Software watchdog reset delay counter register"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RSTDLY,Software watchdog reset delay counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDGRSTDLY ,Reset/NMI delay counter bits"
|
|
endif
|
|
if ((per.l(ad:0xB0308000+0x48)&0x02)==0x02)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2. " ALLOWSTOPCLK ,Clock stop for PSS enable bits" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CFG,Hardware Watchdog Configuration Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,?..."
|
|
newline
|
|
else
|
|
bitfld.long 0x00 24. " LOCK ,Lock bit" "Unlocked,Locked"
|
|
bitfld.long 0x00 16.--20. " OBSSEL ,Watchdog counter monitor bit output selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Clock selection bits" "High-speed,Low-speed,Sub clock,Main clock"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " WDENPSS ,Watchdog counter for PSS enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WDENRUN ,Watchdog counter for RUN enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x4C++0x0F
|
|
line.long 0x00 "RUNLLC,Software Watchdog Lower Limit RUN Current Register"
|
|
line.long 0x04 "RUNULC,Software Watchdog Upper Limit RUN Current Register"
|
|
line.long 0x08 "PSSLLC,Software Watchdog Lower Limit PSS Current Register"
|
|
line.long 0x0C "PSSULC,Software Watchdog Upper Limit PSS Current Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TCRAM (TCRAM INTERFACE)"
|
|
base ad:0xB0410000
|
|
width 14.
|
|
if ((per.l(ad:0xB0410000)&0x100)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
rbitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,Configuration Register 1"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "TCMCFG0,Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " DWAIT ,Number of data wait bits" "0,1,2,3"
|
|
bitfld.long 0x00 8. " LOCKSTATUS ,Lock status bit" "Unlocked,Locked"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC data error insertion bits"
|
|
line.long 0x04 "TCMCFG1,Configuration Register 1"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "TCMUNLOCK,Unlock register"
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
if ((per.l(ad:0xB0410000)&0x100)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ECCDEN,ECC Direct Access Enable Register"
|
|
bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock"
|
|
endif
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ECCDEN,ECC Direct Access Enable Register"
|
|
bitfld.long 0x00 23. " DEN ,Direct access enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
hexmask.long.byte 0x00 16.--22. 1. " DENUNLOCK ,Direct access enable unlock"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
rgroup.long 0x14++0x0B
|
|
line.long 0x00 "ECCDR_PARITY,ECC Direct Read Parity Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ECCDR_PARITY ,Direct read parity data"
|
|
line.long 0x04 "ECCDR_DATA0,ECC Direct Read Data Register 0"
|
|
line.long 0x08 "ECCDR_DATA1,ECC Direct Read Data Register 1"
|
|
else
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "ECCDR_PARITY,ECC Direct Read Parity Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ECCDR_PARITY ,Direct read parity data"
|
|
line.long 0x04 "ECCDR_DATA0,ECC Direct Read Data Register 0"
|
|
line.long 0x08 "ECCDR_DATA1,ECC Direct Read Data Register 1"
|
|
endif
|
|
if ((per.l(ad:0xB0410000)&0x100)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECCDW,ECC Direct Write Register"
|
|
bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock"
|
|
hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ECCDW,ECC Direct Write Register"
|
|
bitfld.long 0x00 31. " DWEN ,Direct access enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " DWENUNLOCK ,Direct write access enable unlock"
|
|
hexmask.long.word 0x00 0.--13. 1. " ECCDW_PARITY ,Direct write parity data"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0xB0410000+0x30)&0xE0000000)!=0x00)
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,Error Address Register 0"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
endif
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "TEAR0,Error Address Register 0"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error " "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
endif
|
|
if ((per.l(ad:0xB0410000+0x34)&0xE0000000)!=0x00)
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,Error Address Register 1"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
endif
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "TEAR1,Error Address Register 1"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
endif
|
|
if ((per.l(ad:0xB0410000+0x38)&0xE0000000)!=0x00)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,Error Address Register 2"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.word 0x00 0.--13. 1. " ERR_ADDR ,Error occurrence address"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--14. 1. " ERR_ADDR ,Error occurrence address"
|
|
endif
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "TEAR2,Error Address Register 2"
|
|
bitfld.long 0x00 31. " TER[2] ,Unique diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 30. " TER[1] ,Checker diagnosis error" "No error,Error"
|
|
bitfld.long 0x00 29. " TER[0] ,March diagnosis error" "No error,Error"
|
|
endif
|
|
if ((per.l(ad:0xB0410000)&0x100)==0x00)
|
|
group.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,End Address Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--13. 1. " EADDR ,RAM diagnosis end address"
|
|
else
|
|
hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address"
|
|
endif
|
|
line.word 0x02 "TASAR,Start Address Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x02 0.--13. 1. " SADDR ,RAM diagnosis start address"
|
|
else
|
|
hexmask.word 0x02 0.--14. 1. " SADDR ,RAM diagnosis start address"
|
|
endif
|
|
group.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,Unique pseudo-error generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " ETYP[1] ,Checker pseudo-error generation" "Not generated,Generated"
|
|
newline
|
|
bitfld.byte 0x00 0. " ETYP[0] ,March pseudo-error generation" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
rbitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
newline
|
|
rbitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "TTCR,Diagnosis Function Register"
|
|
rbitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
rbitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
newline
|
|
bitfld.word 0x00 3. " TTYP[2] ,Perform unique diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " TTYP[1] ,Perform checked diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 1. " TTYP[0] ,Perform march diagnosis" "Not performed,Performed"
|
|
newline
|
|
rbitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,Software reset" "Not reset,Reset"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,Key Code Control Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,?..."
|
|
endif
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "TSCR,Status Clear Register"
|
|
bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear"
|
|
else
|
|
rgroup.word 0x3C++0x03
|
|
line.word 0x00 "TAEAR,End Address Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--13. 1. " EADDR ,RAM diagnosis end address"
|
|
else
|
|
hexmask.word 0x00 0.--14. 1. " EADDR ,RAM diagnosis end address"
|
|
endif
|
|
line.word 0x02 "TASAR,Start Address Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x02 0.--13. 1. " SADDR ,RAM diagnosis start address"
|
|
else
|
|
hexmask.word 0x02 0.--14. 1. " SADDR ,RAM diagnosis start address"
|
|
endif
|
|
rgroup.byte 0x40++0x01
|
|
line.byte 0x00 "TFECR,Pseudo Error Generation Control Register"
|
|
bitfld.byte 0x00 3. " FERR ,RAM diagnosis pseudo-error generation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ETYP[2] ,March pseudo-error generation processing specification" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " ETYP[1] ,Checker pseudo-error generation processing specification" "Not generated,Generated"
|
|
newline
|
|
bitfld.byte 0x00 0. " ETYP[0] ,Unique pseudo-error generation processing specification" "Not generated,Generated"
|
|
line.byte 0x01 "TICR,Initialization Function Register"
|
|
bitfld.byte 0x01 3. " ICIE ,RAM initialization end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " ICI ,RAM initialization completion" "Not completed,Completed"
|
|
bitfld.byte 0x01 1. " ITYP ,RAM initialization contents specification" "0,1"
|
|
newline
|
|
bitfld.byte 0x01 0. " IRUN ,RAM initialization operation status" "Not in progress,In progress"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "TTCR,Diagnosis Function Register"
|
|
bitfld.word 0x00 9. " TSTAT ,RAM diagnosis error detection" "No error,Error"
|
|
bitfld.word 0x00 8. " OVFLW ,RAM diagnosis error overflow" "3 or less,4 or more"
|
|
bitfld.word 0x00 7. " TEIE ,Enable error occurrence interrupt during diagnosis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 6. " TEI ,Diagnosis-time error generation" "0,1"
|
|
bitfld.word 0x00 5. " TCIE ,Diagnosis end source interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " TCI ,Diagnosis end" "Not completed,Completed"
|
|
newline
|
|
bitfld.word 0x00 3. " TTYP[2] ,Perform march diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 2. " TTYP[1] ,Perform checked diagnosis" "Not performed,Performed"
|
|
bitfld.word 0x00 1. " TTYP[0] ,Perform unique diagnosis" "Not performed,Performed"
|
|
newline
|
|
bitfld.word 0x00 0. " TRUN ,RAM diagnosis operation status" "Not in progress,In progress"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J33*")
|
|
hgroup.byte 0x44++0x00
|
|
hide.byte 0x00 "TSRCR,Soft Reset Generation Control Register"
|
|
rgroup.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,Key Code Control Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,"
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,"
|
|
endif
|
|
hgroup.byte 0x45++0x00
|
|
hide.byte 0x00 "TSCR,Status Clear Register"
|
|
else
|
|
rgroup.byte 0x44++0x00
|
|
line.byte 0x00 "TSRCR,Soft Reset Generation Control Register"
|
|
bitfld.byte 0x00 7. " SRST ,software reset" "No reset,Reset"
|
|
rgroup.byte 0x47++0x00
|
|
line.byte 0x00 "TKCCR,Key Code Control Register"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,"
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY ,Key code control" "00,01,10,11"
|
|
bitfld.byte 0x00 0.--1. " CODE ,Operation Specification" "Forcibly terminate,Activate initialization,Activate diagnosis,"
|
|
endif
|
|
rgroup.byte 0x45++0x00
|
|
line.byte 0x00 "TSCR,Status Clear Register"
|
|
bitfld.byte 0x00 6. " TEIC ,Diagnosis-time error generation clear" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " TCIC ,Diagnosis end clear" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " ICIC ,Ram initialization end clear" "No effect,Clear"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TCFLASH"
|
|
base ad:0xB0411000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FCPROTKEY,Configuration Protection Key Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FCFGR,Configuration Register"
|
|
bitfld.long 0x00 6. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " TCMPR ,TCM priority enable" "AXI and TCM,TCM"
|
|
bitfld.long 0x00 4. " WE ,Program enable" "Disabled,Enabled"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
newline
|
|
bitfld.long 0x00 2. " TCMSPEC ,TCM speculative access enable" "Disabled,Enabled"
|
|
textfld " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " FAWC ,Flash wait control" "No wait,1 cycle,2cycles,3cycles"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FECCCTRL,ECC Control Register"
|
|
bitfld.long 0x00 0. " ECCOFF ,ECC off" "Performed,Not performed"
|
|
newline
|
|
sif cpuis("S6J336*")||cpuis("S6j337*")
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FDATEIR_L,Data Bit Error Injection Register"
|
|
bitfld.long 0x00 31. " FDATEIR[63] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 30. " [62] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 29. " [61] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 28. " [60] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " [59] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 26. " [58] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 25. " [57] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 24. " [56] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 23. " [55] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 22. " [54] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 21. " [53] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 20. " [52] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 19. " [51] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 18. " [50] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 17. " [49] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 16. " [48] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 15. " [47] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 14. " [46] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 13. " [45] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 12. " [44] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 11. " [43] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 10. " [42] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 9. " [41] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 8. " [40] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 7. " [39] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 6. " [38] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 5. " [37] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 4. " [36] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " [35] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 2. " [34] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 1. " [33] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x00 0. " [32] ,Data bit error injection point" "No error,Error"
|
|
line.long 0x04 "FDATEIR_H,Data Bit Error Injection Register"
|
|
bitfld.long 0x04 31. " FDATEIR[31] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 30. " [30] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 29. " [29] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 28. " [28] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 26. " [26] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 25. " [25] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 24. " [24] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 22. " [22] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 21. " [21] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 20. " [20] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 18. " [18] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 17. " [17] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 16. " [16] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 14. " [14] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 13. " [13] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 12. " [12] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 10. " [10] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 9. " [9] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 8. " [8] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 6. " [6] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 5. " [5] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 4. " [4] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 2. " [2] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 1. " [1] ,Data bit error injection point" "No error,Error"
|
|
bitfld.long 0x04 0. " [0] ,Data bit error injection point" "No error,Error"
|
|
newline
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FECCEIR,Bit Error Injection Register"
|
|
sif (cpuis("S6J33*"))
|
|
bitfld.long 0x00 27. " LMASK[3] ,Error injection lane mask (0x18 to 0x1F)" "Error,No error"
|
|
bitfld.long 0x00 26. " LMASK[2] ,Error injection lane mask (0x10 to 0x17)" "Error,No error"
|
|
bitfld.long 0x00 25. " LMASK[1] ,Error injection lane mask (0x08 to 0x0F)" "Error,No error"
|
|
bitfld.long 0x00 24. " LMASK[0] ,Error injection lane mask (0x00 to 0x07)" "Error,No error"
|
|
newline
|
|
bitfld.long 0x00 7. " FECCEIR[7] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 6. " FECCEIR[6] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 5. " FECCEIR[5] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 4. " FECCEIR[4] ,ECC bit injection point" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " FECCEIR[3] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 2. " FECCEIR[2] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 1. " FECCEIR[1] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 0. " FECCEIR[0] ,ECC bit injection point" "0,1"
|
|
else
|
|
bitfld.long 0x00 25. " LMASK[1] ,Error injection lane mask" "Error,No error"
|
|
bitfld.long 0x00 24. " LMASK[0] ,Error injection lane mask" "Error,No error"
|
|
bitfld.long 0x00 7. " FECCEIR[7] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 6. " FECCEIR[6] ,ECC bit injection point" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. " FECCEIR[5] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 4. " FECCEIR[4] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 3. " FECCEIR[3] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 2. " FECCEIR[2] ,ECC bit injection point" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " FECCEIR[1] ,ECC bit injection point" "0,1"
|
|
bitfld.long 0x00 0. " FECCEIR[0] ,ECC bit injection point" "0,1"
|
|
endif
|
|
sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "FICTRL0,Interrupt Control Register"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "FICTRL1,Interrupt Control Register"
|
|
bitfld.long 0x04 9. " HANGIC ,Hang interrupt bit" "No effect,Clear"
|
|
bitfld.long 0x04 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x04 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FICTRL,Interrupt Control Register"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RDYIE ,Programming/erasing ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("S6J33*")
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FDATEIR_L,Data Bit Error Injection Register"
|
|
line.long 0x04 "FDATEIR_H,Data Bit Error Injection Register"
|
|
endif
|
|
sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J33*")
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "FSTAT0,Status Register"
|
|
bitfld.long 0x00 16. " MARGIN ,MARGIN" "0,1"
|
|
bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " CERS ,Chip erase status" "Not performed,Performed"
|
|
bitfld.long 0x00 6. " PGMS ,Program status" "No programming,Programming"
|
|
bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended"
|
|
bitfld.long 0x00 3. " SERS ,Sector erase status" "Not performed,Performed"
|
|
bitfld.long 0x00 2. " READ ,Reading ready" "Unable,Able"
|
|
newline
|
|
bitfld.long 0x00 1. " HANG ,Hangup" "No,Yes"
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Performing,Completed"
|
|
line.long 0x04 "FSTAT1,Status Register"
|
|
bitfld.long 0x04 16. " MARGIN ,MARGIN" "0,1"
|
|
bitfld.long 0x04 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 7. " CERS ,Chip erase status" "Not performed,Performed"
|
|
bitfld.long 0x04 6. " PGMS ,Program status" "No programming,Programming"
|
|
bitfld.long 0x04 5. " ESPS ,Erase suspend status" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended"
|
|
bitfld.long 0x04 3. " SERS ,Sector erase status" "Not performed,Performed"
|
|
bitfld.long 0x04 2. " READ ,Reading ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x04 1. " HANG ,Hangup" "No,Yes"
|
|
bitfld.long 0x04 0. " RDY ,Programming/erasing ready" "Performing,Completed"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "FSTAT,Status Register"
|
|
bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " CERS ,Chip erase status" "Not performed,Performed"
|
|
newline
|
|
bitfld.long 0x00 6. " PGMS ,Program status" "No programming,Programming"
|
|
bitfld.long 0x00 5. " ESPS ,Erase suspend status" "Not suspended,Suspended"
|
|
bitfld.long 0x00 4. " ERSEC ,Erase suspend sector status" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 3. " SERS ,Sector erase status" "Not performed,Performed"
|
|
bitfld.long 0x00 2. " READ ,Reading ready" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " HANG ,Hangup" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " RDY ,Programming/erasing ready" "Performing,Completed"
|
|
endif
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FSECIR,Interrupt Register"
|
|
sif !cpuis("S6J336*")&&!cpuis("S6j337*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
sif cpuis("S6J33*")
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FECCEAR,ECC Error Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " FECCEAR_BASE ,Base Error Address"
|
|
newline
|
|
bitfld.long 0x00 3. " SELF[3] ,Single Error Lane Flag bit 3 [255:192]" "No error,Error"
|
|
bitfld.long 0x00 2. " SELF[2] ,Single Error Lane Flag bit 2 [191:128]" "No error,Error"
|
|
bitfld.long 0x00 1. " SELF[1] ,Single Error Lane Flag bit 1 [127:64]" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 0. " SELF[0] ,Single Error Lane Flag bit 0 [63:0]" "No error,Error"
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "FUIDR0,TCFLASH Unique ID ROM Register 0"
|
|
line.long 0x04 "FUIDR1,TCFLASH Unique ID ROM Register 1"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FUCEDIR,Uncorrectable Error Detection Interrupt Register"
|
|
rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "No error,Error"
|
|
bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" "No effect,Clear"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FUCEAR,Uncorrectable Error Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " UCEA_BASE ,Uncorrectable Error Address"
|
|
newline
|
|
bitfld.long 0x00 3. " UCELF[3] ,Uncorrectable Error Lane Flag bit 3 [255:192]" "No error,Error"
|
|
bitfld.long 0x00 2. " UCELF[2] ,Uncorrectable Error Lane Flag bit 2 [191:128]" "No error,Error"
|
|
bitfld.long 0x00 1. " UCELF[1] ,Uncorrectable Error Lane Flag bit 1 [127:64]" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 0. " UCELF[0] ,Uncorrectable Error Lane Flag bit 0 [63:0]" "No error,Error"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "SYNR,Syndrome Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN[3] ,Syndrome of FWORD256 [255:192]"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SYN[2] ,Syndrome of FWORD256 [191:128]"
|
|
hexmask.long.word 0x00 8.--16. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SYNR,Syndrome Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN[3] ,Syndrome of FWORD256 [255:192]"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SYN[2] ,Syndrome of FWORD256 [191:128]"
|
|
hexmask.long.word 0x00 8.--16. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SYN[1] ,Syndrome of FWORD256 [127:64]"
|
|
endif
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FECCEAR,ECC Error Address Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FUCEDIR,Uncorrectable Error Detection Interrupt Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " UCEDINT ,Uncorrectable error detection interrupt" "Not generated,Generated"
|
|
bitfld.long 0x00 8. " UCEDIC ,Uncorrectable error detection interrupt clear" "No effect,Clear"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "FUCEAR,Uncorrectable Error Address Register"
|
|
endif
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "BRCFG,Buffer Region Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " REGION_END_BUF ,TCM buffer word number of region end"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SSEC ,Starting bufferable sector number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESEC ,Ending bufferable sector number"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BRAT,Buffer Region Attribute Register"
|
|
bitfld.long 0x00 16. " VCLR ,TCM buffer region international clear" "No effect,Clear"
|
|
bitfld.long 0x00 8.--9. " AM ,Buffer policy for TCM buffer region" "Wait state,2 pieces,Locked,?..."
|
|
bitfld.long 0x00 0. " RGEN ,TCM Buffer region enable" "Disabled,Enabled"
|
|
newline
|
|
width 26.
|
|
sif (cpuis("S6J33*"))
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x400+0x00)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x400+0x04)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x400+0x08)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x400+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x400+0x10)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x400+0x14)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x400+0x18)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x400+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x400+0x20)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x400+0x24)++0x03
|
|
line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x400+0x28)++0x03
|
|
line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x400+0x00)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x400+0x04)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x400+0x08)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x400+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x400+0x10)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x400+0x14)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x400+0x18)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x400+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x400+0x20)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x400+0x24)++0x03
|
|
line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x400+0x28)++0x03
|
|
line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x400+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x400+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x400+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x400+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x400+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x400+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x400+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x400+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x400+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x400+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x400+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x440+0x00)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x440+0x04)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x440+0x08)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x440+0x10)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x440+0x18)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x440+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x440+0x20)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x440+0x24)++0x03
|
|
line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x440+0x28)++0x03
|
|
line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x440+0x00)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x440+0x04)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x440+0x08)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x440+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x440+0x10)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x440+0x14)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x440+0x18)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x440+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x440+0x20)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x440+0x24)++0x03
|
|
line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x440+0x28)++0x03
|
|
line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x440+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x440+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x440+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x440+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x440+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x440+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x440+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x440+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x440+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x440+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x440+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x480+0x00)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x480+0x04)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x480+0x08)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x480+0x10)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x480+0x14)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x480+0x18)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x480+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x480+0x20)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x480+0x24)++0x03
|
|
line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x480+0x28)++0x03
|
|
line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x480+0x00)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x480+0x04)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x480+0x08)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x480+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x480+0x10)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x480+0x14)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x480+0x18)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x480+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x480+0x20)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x480+0x24)++0x03
|
|
line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x480+0x28)++0x03
|
|
line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x480+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x480+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x480+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x480+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x480+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x480+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x480+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x480+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x480+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x480+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x480+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x4C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x4C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x4C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x4C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x4C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x4C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x4C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x4C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x4C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x4C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x4C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x4C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x4C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x4C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x4C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x4C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x4C0+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x500+0x00)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x500+0x04)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x500+0x08)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x500+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x500+0x10)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x500+0x14)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x500+0x18)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x500+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x500+0x20)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x500+0x24)++0x03
|
|
line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x500+0x28)++0x03
|
|
line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x500+0x00)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x500+0x04)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x500+0x08)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x500+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x500+0x10)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x500+0x14)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x500+0x18)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x500+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x500+0x20)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x500+0x24)++0x03
|
|
line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x500+0x28)++0x03
|
|
line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x500+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x500+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x500+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x500+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x500+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x500+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x500+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x500+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x500+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x500+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x500+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x540+0x00)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x540+0x04)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x540+0x08)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x540+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x540+0x10)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x540+0x14)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x540+0x18)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x540+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x540+0x20)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x540+0x24)++0x03
|
|
line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x540+0x28)++0x03
|
|
line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x540+0x00)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x540+0x04)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x540+0x08)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x540+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x540+0x10)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x540+0x14)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x540+0x18)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x540+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x540+0x20)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x540+0x24)++0x03
|
|
line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x540+0x28)++0x03
|
|
line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x540+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x540+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x540+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x540+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x540+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x540+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x540+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x540+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x540+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x540+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x540+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x580+0x00)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x580+0x04)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x580+0x08)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x580+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x580+0x10)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x580+0x14)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x580+0x18)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x580+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x580+0x20)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x580+0x24)++0x03
|
|
line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x580+0x28)++0x03
|
|
line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x580+0x00)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x580+0x04)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x580+0x08)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x580+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x580+0x10)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x580+0x14)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x580+0x18)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x580+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x580+0x20)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x580+0x24)++0x03
|
|
line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x580+0x28)++0x03
|
|
line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x580+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x580+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x580+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x580+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x580+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x580+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x580+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x580+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x580+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x580+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x580+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x5C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x5C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x5C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x5C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x5C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x5C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x5C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x5C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x5C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x5C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x5C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x5C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x5C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x5C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x5C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x5C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x5C0+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x600+0x00)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x600+0x04)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x600+0x08)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x600+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x600+0x10)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x600+0x14)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x600+0x18)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x600+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x600+0x20)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x600+0x24)++0x03
|
|
line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x600+0x28)++0x03
|
|
line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x600+0x00)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x600+0x04)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x600+0x08)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x600+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x600+0x10)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x600+0x14)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x600+0x18)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x600+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x600+0x20)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x600+0x24)++0x03
|
|
line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x600+0x28)++0x03
|
|
line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x600+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x600+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x600+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x600+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x600+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x600+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x600+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x600+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x600+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x600+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x600+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x640+0x00)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x640+0x04)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x640+0x08)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x640+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x640+0x10)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x640+0x14)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x640+0x18)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x640+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x640+0x20)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x640+0x24)++0x03
|
|
line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x640+0x28)++0x03
|
|
line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x640+0x00)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x640+0x04)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x640+0x08)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x640+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x640+0x10)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x640+0x14)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x640+0x18)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x640+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x640+0x20)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x640+0x24)++0x03
|
|
line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x640+0x28)++0x03
|
|
line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x640+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x640+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x640+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x640+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x640+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x640+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x640+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x640+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x640+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x640+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x640+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x680+0x00)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x680+0x04)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x680+0x08)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x680+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x680+0x10)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x680+0x14)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x680+0x18)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x680+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x680+0x20)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x680+0x24)++0x03
|
|
line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x680+0x28)++0x03
|
|
line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x680+0x00)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x680+0x04)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x680+0x08)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x680+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x680+0x10)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x680+0x14)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x680+0x18)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x680+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x680+0x20)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x680+0x24)++0x03
|
|
line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x680+0x28)++0x03
|
|
line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x680+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x680+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x680+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x680+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x680+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x680+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x680+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x680+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x680+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x680+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x680+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x6C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x6C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x6C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x6C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x6C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x6C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x6C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x6C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x6C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x6C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x6C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x6C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x6C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x6C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x6C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x6C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x6C0+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x700+0x00)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x700+0x04)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x700+0x08)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x700+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x700+0x10)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x700+0x14)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x700+0x18)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x700+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x700+0x20)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x700+0x24)++0x03
|
|
line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x700+0x28)++0x03
|
|
line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x700+0x00)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x700+0x04)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x700+0x08)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x700+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x700+0x10)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x700+0x14)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x700+0x18)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x700+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x700+0x20)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x700+0x24)++0x03
|
|
line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x700+0x28)++0x03
|
|
line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x700+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x700+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x700+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x700+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x700+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x700+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x700+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x700+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x700+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x700+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x700+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x740+0x00)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x740+0x04)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x740+0x08)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x740+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x740+0x10)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x740+0x14)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x740+0x18)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x740+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x740+0x20)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x740+0x24)++0x03
|
|
line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x740+0x28)++0x03
|
|
line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x740+0x00)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x740+0x04)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x740+0x08)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x740+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x740+0x10)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x740+0x14)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x740+0x18)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x740+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x740+0x20)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x740+0x24)++0x03
|
|
line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x740+0x28)++0x03
|
|
line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x740+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x740+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x740+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x740+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x740+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x740+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x740+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x740+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x740+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x740+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x740+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x780+0x00)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x780+0x04)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x780+0x08)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x780+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x780+0x10)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x780+0x14)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x780+0x18)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x780+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x780+0x20)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x780+0x24)++0x03
|
|
line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x780+0x28)++0x03
|
|
line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x780+0x00)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x780+0x04)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x780+0x08)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x780+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x780+0x10)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x780+0x14)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x780+0x18)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x780+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x780+0x20)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x780+0x24)++0x03
|
|
line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x780+0x28)++0x03
|
|
line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x780+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x780+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x780+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x780+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x780+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x780+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x780+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x780+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x780+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x780+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x780+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x301)==0x200)
|
|
group.long (0x7C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x7C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x7C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x7C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x7C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register"
|
|
group.long (0x7C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register"
|
|
group.long (0x7C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register"
|
|
group.long (0x7C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register"
|
|
group.long (0x7C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x7C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
group.long (0x7C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
elif ((((per.l(ad:0xB0411000+0x98))&0x300)!=0x200)&&((per.l(ad:0xB0411000+0x98)&0x01)==0x00))
|
|
rgroup.long (0x7C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register"
|
|
rgroup.long (0x7C0+0x20)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
hexmask.long.tbyte 0x00 5.--22. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--4. 1. " BUFADDL ,Buffer address lower bit"
|
|
else
|
|
bitfld.long 0x00 24. " READ1 , Read 1" ",1"
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
rgroup.long (0x7C0+0x24)++0x03
|
|
line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
rgroup.long (0x7C0+0x28)++0x03
|
|
line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
hgroup.long (0x7C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[128:159],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[160:191],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[192:223],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[224:255],TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x20)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x24)++0x03
|
|
hide.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register"
|
|
hgroup.long (0x7C0+0x28)++0x03
|
|
hide.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x100+0x00)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x100+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x100+0x10)++0x03
|
|
line.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x100+0x14)++0x03
|
|
line.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x100+0x18)++0x03
|
|
line.long 0x00 "TCMBUF0_W6,TCMBUF0_W6"
|
|
group.long (0x100+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x100+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x100+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x100+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x100+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x100+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x100+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF0_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x100+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF0_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x100+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF0_W6,TCMBUF0_W6"
|
|
endif
|
|
hgroup.long (0x100+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF0_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x120+0x00)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x120+0x04)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x120+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x120+0x10)++0x03
|
|
line.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x120+0x14)++0x03
|
|
line.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x120+0x18)++0x03
|
|
line.long 0x00 "TCMBUF1_W6,TCMBUF1_W6"
|
|
group.long (0x120+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x120+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x120+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x120+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x120+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x120+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x120+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF1_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x120+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF1_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x120+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF1_W6,TCMBUF1_W6"
|
|
endif
|
|
hgroup.long (0x120+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF1_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x140+0x00)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x140+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x140+0x10)++0x03
|
|
line.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x140+0x14)++0x03
|
|
line.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x140+0x18)++0x03
|
|
line.long 0x00 "TCMBUF2_W6,TCMBUF2_W6"
|
|
group.long (0x140+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x140+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x140+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x140+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x140+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x140+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x140+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF2_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x140+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF2_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x140+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF2_W6,TCMBUF2_W6"
|
|
endif
|
|
hgroup.long (0x140+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF2_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x160+0x00)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x160+0x04)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x160+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x160+0x10)++0x03
|
|
line.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x160+0x14)++0x03
|
|
line.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x160+0x18)++0x03
|
|
line.long 0x00 "TCMBUF3_W6,TCMBUF3_W6"
|
|
group.long (0x160+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x160+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x160+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x160+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x160+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x160+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x160+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF3_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x160+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF3_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x160+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF3_W6,TCMBUF3_W6"
|
|
endif
|
|
hgroup.long (0x160+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF3_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x180+0x00)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x180+0x04)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x180+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x180+0x10)++0x03
|
|
line.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x180+0x14)++0x03
|
|
line.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x180+0x18)++0x03
|
|
line.long 0x00 "TCMBUF4_W6,TCMBUF4_W6"
|
|
group.long (0x180+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x180+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x180+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x180+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x180+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x180+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x180+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF4_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x180+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF4_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x180+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF4_W6,TCMBUF4_W6"
|
|
endif
|
|
hgroup.long (0x180+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF4_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x1A0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x1A0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x1A0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x1A0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x1A0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x1A0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF5_W6,TCMBUF5_W6"
|
|
group.long (0x1A0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x1A0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x1A0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x1A0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x1A0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x1A0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x1A0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF5_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x1A0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF5_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x1A0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF5_W6,TCMBUF5_W6"
|
|
endif
|
|
hgroup.long (0x1A0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF5_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x1C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x1C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x1C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x1C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x1C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x1C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF6_W6,TCMBUF6_W6"
|
|
group.long (0x1C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x1C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x1C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x1C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x1C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x1C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x1C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF6_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x1C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF6_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x1C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF6_W6,TCMBUF6_W6"
|
|
endif
|
|
hgroup.long (0x1C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF6_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x1E0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x1E0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x1E0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x1E0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x1E0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x1E0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF7_W6,TCMBUF7_W6"
|
|
group.long (0x1E0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x1E0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x1E0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x1E0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x1E0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x1E0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x1E0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF7_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x1E0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF7_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x1E0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF7_W6,TCMBUF7_W6"
|
|
endif
|
|
hgroup.long (0x1E0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF7_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x200+0x00)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x200+0x04)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x200+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "TCMBUF8_W6,TCMBUF8_W6"
|
|
group.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x200+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x200+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x200+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x200+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x200+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF8_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x200+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF8_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x200+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF8_W6,TCMBUF8_W6"
|
|
endif
|
|
hgroup.long (0x200+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF8_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x220+0x00)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x220+0x04)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x220+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x220+0x10)++0x03
|
|
line.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x220+0x14)++0x03
|
|
line.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x220+0x18)++0x03
|
|
line.long 0x00 "TCMBUF9_W6,TCMBUF9_W6"
|
|
group.long (0x220+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x220+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x220+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x220+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x220+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x220+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x220+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF9_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x220+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF9_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x220+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF9_W6,TCMBUF9_W6"
|
|
endif
|
|
hgroup.long (0x220+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF9_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x240+0x00)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x240+0x04)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x240+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x240+0x10)++0x03
|
|
line.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x240+0x14)++0x03
|
|
line.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x240+0x18)++0x03
|
|
line.long 0x00 "TCMBUF10_W6,TCMBUF10_W6"
|
|
group.long (0x240+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x240+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x240+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x240+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x240+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x240+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x240+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF10_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x240+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF10_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x240+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF10_W6,TCMBUF10_W6"
|
|
endif
|
|
hgroup.long (0x240+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF10_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x260+0x00)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x260+0x04)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x260+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x260+0x10)++0x03
|
|
line.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x260+0x14)++0x03
|
|
line.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x260+0x18)++0x03
|
|
line.long 0x00 "TCMBUF11_W6,TCMBUF11_W6"
|
|
group.long (0x260+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x260+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x260+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x260+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x260+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x260+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x260+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF11_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x260+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF11_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x260+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF11_W6,TCMBUF11_W6"
|
|
endif
|
|
hgroup.long (0x260+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF11_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x280+0x00)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x280+0x04)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x280+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x280+0x10)++0x03
|
|
line.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x280+0x14)++0x03
|
|
line.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x280+0x18)++0x03
|
|
line.long 0x00 "TCMBUF12_W6,TCMBUF12_W6"
|
|
group.long (0x280+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x280+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x280+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x280+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x280+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x280+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x280+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF12_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x280+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF12_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x280+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF12_W6,TCMBUF12_W6"
|
|
endif
|
|
hgroup.long (0x280+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF12_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x2A0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x2A0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x2A0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x2A0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x2A0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x2A0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF13_W6,TCMBUF13_W6"
|
|
group.long (0x2A0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x2A0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x2A0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x2A0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x2A0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x2A0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x2A0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF13_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x2A0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF13_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x2A0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF13_W6,TCMBUF13_W6"
|
|
endif
|
|
hgroup.long (0x2A0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF13_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x2C0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x2C0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x2C0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x2C0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x2C0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x2C0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF14_W6,TCMBUF14_W6"
|
|
group.long (0x2C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x2C0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x2C0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x2C0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x2C0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x2C0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x2C0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF14_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x2C0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF14_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x2C0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF14_W6,TCMBUF14_W6"
|
|
endif
|
|
hgroup.long (0x2C0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF14_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
if ((per.l(ad:0xB0411000+0x98)&0x01)==0x00)
|
|
group.long (0x2E0+0x00)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register"
|
|
group.long (0x2E0+0x04)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register"
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register"
|
|
group.long (0x2E0+0x0C)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register"
|
|
group.long (0x2E0+0x10)++0x03
|
|
line.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BUFADD ,Buffer address upper bit"
|
|
newline
|
|
else
|
|
hexmask.long.tbyte 0x00 4.--23. 1. " BUFADDH ,Buffer address upper bit"
|
|
hexmask.long.byte 0x00 0.--3. 1. " BUFADDL ,Buffer address lower bit"
|
|
endif
|
|
group.long (0x2E0+0x14)++0x03
|
|
line.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register"
|
|
bitfld.long 0x00 0. " BVALID ,Buffer valid" "Invalid,Valid"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.long (0x2E0+0x18)++0x03
|
|
line.long 0x00 "TCMBUF15_W6,TCMBUF15_W6"
|
|
group.long (0x2E0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
else
|
|
group.long (0x2E0+0x1C)++0x03
|
|
line.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_PARITY ,Parity value of TCM buffer"
|
|
endif
|
|
else
|
|
hgroup.long (0x2E0+0x00)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[0:31],TCM Buffer Register"
|
|
hgroup.long (0x2E0+0x04)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[32:63],TCM Buffer Register"
|
|
hgroup.long (0x2E0+0x08)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[64:95],TCM Buffer Register"
|
|
hgroup.long (0x2E0+0x0C)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFDATA[96:127],TCM Buffer Register"
|
|
hgroup.long (0x2E0+0x10)++0x03
|
|
hide.long 0x00 "TCMBUF15_BUFADD,TCM Buffer Register"
|
|
hgroup.long (0x2E0+0x14)++0x03
|
|
hide.long 0x00 "TCMBUF15_BVALID,TCM Buffer Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hgroup.long (0x2E0+0x18)++0x03
|
|
hide.long 0x00 "TCMBUF15_W6,TCMBUF15_W6"
|
|
endif
|
|
hgroup.long (0x2E0+0x1C)++0x03
|
|
hide.long 0x00 "TCMBUF15_ECC_PARITY,TCM Buffer Register"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SECURITY"
|
|
base ad:0xB04113C0
|
|
width 16.
|
|
if (((per.l(ad:0xB04113C0+0x00))&0x01)==0x00)
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "TCFCFG_SECSTAT,Security Status Register"
|
|
bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "0,1"
|
|
bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished"
|
|
bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "TCFCFG_SECSTAT,Security Status Register"
|
|
bitfld.long 0x00 8. " UMV ,Specification of the unlock marker value" "0,1"
|
|
bitfld.long 0x00 5. " SFDONE ,Security fetch done register" "Ongoing,Finished"
|
|
bitfld.long 0x00 4. " SWPOE ,Sector write permission overwrite enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECOE ,Security overwrite enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CEEN ,Chip erase enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SECSC ,Security scope register" "Flash protection,Device protection"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECEN ,Security enable register" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCFCFG_SER,Security Enable Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCFCFG_SSR,Security Scope Register"
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TCFCFG_CEER,Chip Erase Enable Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCFCFG_SOER,Security Overwrite Enable Register"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TCFCFG_SWPOER,Sector Write Permission Overwrite Enable Register"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TCFCFG_WSWP,Work Flash Sector Write Permissions Register"
|
|
bitfld.long 0x00 13. " WSWP_[13] ,Work flash sector write permission SA13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Work flash sector write permission SA12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Work flash sector write permission SA11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Work flash sector write permission SA10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Work flash sector write permission SA9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Work flash sector write permission SA8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Work flash sector write permission SA7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Work flash sector write permission SA6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Work flash sector write permission SA5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Work flash sector write permission SA4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Work flash sector write permission SA3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Work flash sector write permission SA2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Work flash sector write permission SA1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Work flash sector write permission SA0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TCFCFG_C0SWP,Code Flash 0 Sector Write Permissions of the small sectors Register"
|
|
bitfld.long 0x00 7. " C0SWP_[7] ,Code flash sector write permission SA7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Code flash sector write permission SA6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Code flash sector write permission SA5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Code flash sector write permission SA4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Code flash sector write permission SA3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Code flash sector write permission SA2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Code flash sector write permission SA1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Code flash sector write permission SA0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TCFCFG_C1SWP,Code Flash 0 Sector Write Permissions of the large sectors Register"
|
|
bitfld.long 0x00 31. " C1SWP_[39] ,Code flash sector write permission SA39" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [38] ,Code flash sector write permission SA38" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [37] ,Code flash sector write permission SA37" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [36] ,Code flash sector write permission SA36" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [35] ,Code flash sector write permission SA35" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [34] ,Code flash sector write permission SA34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [33] ,Code flash sector write permission SA33" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [32] ,Code flash sector write permission SA32" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [31] ,Code flash sector write permission SA31" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [30] ,Code flash sector write permission SA30" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [29] ,Code flash sector write permission SA29" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [28] ,Code flash sector write permission SA28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [27] ,Code flash sector write permission SA27" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [26] ,Code flash sector write permission SA26" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [25] ,Code flash sector write permission SA25" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [24] ,Code flash sector write permission SA24" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [23] ,Code flash sector write permission SA23" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [22] ,Code flash sector write permission SA22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [21] ,Code flash sector write permission SA21" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [20] ,Code flash sector write permission SA20" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [19] ,Code flash sector write permission SA19" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [18] ,Code flash sector write permission SA18" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [17] ,Code flash sector write permission SA17" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [16] ,Code flash sector write permission SA16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [15] ,Code flash sector write permission SA15" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [14] ,Code flash sector write permission SA14" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [13] ,Code flash sector write permission SA13" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [12] ,Code flash sector write permission SA12" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [11] ,Code flash sector write permission SA11" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [10] ,Code flash sector write permission SA10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [9] ,Code flash sector write permission SA9" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [8] ,Code flash sector write permission SA8" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TCFCFG_C2SWP,Code Flash 1 Sector Write Permissions of the large sectors Register"
|
|
bitfld.long 0x00 31. " C2SWP_[39] ,Code flash sector write permission SA39" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [38] ,Code flash sector write permission SA38" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [37] ,Code flash sector write permission SA37" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [36] ,Code flash sector write permission SA36" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [35] ,Code flash sector write permission SA35" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [34] ,Code flash sector write permission SA34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [33] ,Code flash sector write permission SA33" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [32] ,Code flash sector write permission SA32" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [31] ,Code flash sector write permission SA31" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [30] ,Code flash sector write permission SA30" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [29] ,Code flash sector write permission SA29" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [28] ,Code flash sector write permission SA28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [27] ,Code flash sector write permission SA27" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [26] ,Code flash sector write permission SA26" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [25] ,Code flash sector write permission SA25" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [24] ,Code flash sector write permission SA24" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [23] ,Code flash sector write permission SA23" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [22] ,Code flash sector write permission SA22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [21] ,Code flash sector write permission SA21" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [20] ,Code flash sector write permission SA20" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [19] ,Code flash sector write permission SA19" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [18] ,Code flash sector write permission SA18" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [17] ,Code flash sector write permission SA17" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [16] ,Code flash sector write permission SA16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [15] ,Code flash sector write permission SA15" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [14] ,Code flash sector write permission SA14" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [13] ,Code flash sector write permission SA13" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [12] ,Code flash sector write permission SA12" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [11] ,Code flash sector write permission SA11" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [10] ,Code flash sector write permission SA10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [9] ,Code flash sector write permission SA9" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [8] ,Code flash sector write permission SA8" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TCFCFG_C3SWP,Code Flash 2 Sector Write Permissions of the large sectors Register"
|
|
bitfld.long 0x00 31. " C3SWP_[39] ,Code flash sector write permission SA39" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [38] ,Code flash sector write permission SA38" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [37] ,Code flash sector write permission SA37" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [36] ,Code flash sector write permission SA36" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [35] ,Code flash sector write permission SA35" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [34] ,Code flash sector write permission SA34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [33] ,Code flash sector write permission SA33" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [32] ,Code flash sector write permission SA32" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [31] ,Code flash sector write permission SA31" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [30] ,Code flash sector write permission SA30" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [29] ,Code flash sector write permission SA29" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [28] ,Code flash sector write permission SA28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [27] ,Code flash sector write permission SA27" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [26] ,Code flash sector write permission SA26" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [25] ,Code flash sector write permission SA25" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [24] ,Code flash sector write permission SA24" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [23] ,Code flash sector write permission SA23" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [22] ,Code flash sector write permission SA22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [21] ,Code flash sector write permission SA21" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [20] ,Code flash sector write permission SA20" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [19] ,Code flash sector write permission SA19" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [18] ,Code flash sector write permission SA18" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [17] ,Code flash sector write permission SA17" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [16] ,Code flash sector write permission SA16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [15] ,Code flash sector write permission SA15" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [14] ,Code flash sector write permission SA14" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [13] ,Code flash sector write permission SA13" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [12] ,Code flash sector write permission SA12" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [11] ,Code flash sector write permission SA11" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [10] ,Code flash sector write permission SA10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [9] ,Code flash sector write permission SA9" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [8] ,Code flash sector write permission SA8" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WORKFLASH"
|
|
base ad:0xB0412000
|
|
width 9.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "CPR,Configuration protection key register"
|
|
if ((per.l(ad:0xB0412000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CR,Configuration register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Write enable" "Disabled,Enabled"
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "ECR,ECC control register"
|
|
bitfld.long 0x00 0. " ECCOFF ,ECC off" "No,Yes"
|
|
else
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "CR,Configuration register"
|
|
bitfld.long 0x00 16. " SWFRST ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " WE ,Write enable" "Disabled,Enabled"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "ECR,ECC control register"
|
|
bitfld.long 0x00 0. " ECCOFF ,ECC off" "No,Yes"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WCR,Write command sequencer configuration register"
|
|
bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WSR,Write command sequencer status register"
|
|
bitfld.long 0x00 0.--1. " ST ,Write command sequencer status" "Idle,Sending,Waiting,"
|
|
if ((per.l(ad:0xB0412000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "EEIR,ECC bit error injection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EEIR ,ECC bit error injection location"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "EEIR,ECC bit error injection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EEIR ,ECC bit error injection location"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ICR,Interrupt control register"
|
|
bitfld.long 0x00 9. " HANGIC ,Hang interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RDYIC ,Ready interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " HANGIE ,Hang interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDYIE ,Ready interrupt enable" "Disabled,Enabled"
|
|
sif !cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J311*")&&!cpuis("S6J312?HAA")
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 16. " MARGIN ,MARGIN" "0,1"
|
|
bitfld.long 0x00 12. " WERINT ,Write enable release interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ESPS ,Erase Suspend status" "Not suspended,Suspended"
|
|
bitfld.long 0x00 3. " SERS ,Sector erase status" "Not erasing,Erasing"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDY ,Ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SR,Status register"
|
|
bitfld.long 0x00 12. " WERINT ,Write enable release interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " HANGINT ,Hangup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " RDYINT ,Ready interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ESPS ,Erase Suspend status" "Not suspended,Suspended"
|
|
bitfld.long 0x00 3. " SERS ,Sector erase status" "Not erasing,Erasing"
|
|
bitfld.long 0x00 0. " RDY ,Ready" "Not ready,Ready"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SECIR,SEC interrupt register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome"
|
|
rbitfld.long 0x00 16. " SECINT ,1-bit error correction interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SECIC ,1-bit error correction interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECIE ,1-bit error correction interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "EEAR,ECC error address register"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "EMENR,Extra mode enable register"
|
|
bitfld.long 0x00 8. " AEE ,Read arbitration error enable" "Disabled,Enabled"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "SEQCM,Sequencer command register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ERS ,Sector erase instruction"
|
|
bitfld.long 0x00 0.--1. " OPC ,Command" "No operation,Read/Reset,Erase command,Suspend command"
|
|
rgroup.long 0x58++0x3
|
|
line.long 0x00 "ARBERR,Arbitration error register"
|
|
bitfld.long 0x00 0. " ARBERR ,Read arbitration error" "No error,Error"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "ARBCLR,Arbitration error clear register"
|
|
bitfld.long 0x00 0. " ARBCLR ,Read arbitration error clear" "No effect,Clear"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x00 "BERR,Bus error response status register"
|
|
bitfld.long 0x00 11. " ERSIGN ,ERS writing violation" "Not detected,Detected"
|
|
bitfld.long 0x00 10. " RORW ,Write access to a read-only register" "Not detected,Detected"
|
|
bitfld.long 0x00 9. " NWTM ,Writing to mirror area 4" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ACCIGN ,Command overrun" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " ECRWL ,Protection sequence violation" "Not detected,Detected"
|
|
bitfld.long 0x00 6. " UNACC ,Unprivileged writing" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESA ,Reserved area access" "Not detected,Detected"
|
|
bitfld.long 0x00 4. " RWE ,Reserved area access" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " SIZE ,Access size violation" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRWE ,Writing prohibition violation" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DED ,Uncorrectable error detection" "Not detected,Detected"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x00 "BERRCLR,Bus error response status clear register"
|
|
bitfld.long 0x00 11. " ERSIGNCLR ,ERSIGN clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RORWCLR ,RORW clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " NWTMCLR ,NWTM clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ACCIGNCLR ,ACCIGN clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " ECRWLCLR ,ECRWL clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UNACCLR ,UNACC clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RESACLR ,RESA clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " RWECLR ,RWE clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " SIZECLR ,SIZE clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRWECLR ,CRWE clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DEDCLR ,DED clear" "No effect,Clear"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "WARBR,Write arbitration register"
|
|
rbitfld.long 0x00 24. " WERSTS ,Write enable release status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WERINT ,Write enable release interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " WERINTCLR ,Write enable release interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WERINTE ,Write enable release interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x6C++0x3
|
|
line.long 0x00 "UCESR,Uncorrectable error status register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SYN ,Syndrome"
|
|
rgroup.long 0x70++0x3
|
|
line.long 0x00 "UCEAR,Uncorrectable error address register"
|
|
if ((per.l(ad:0xB0412000)&0xFFFFFFFF)==0xFFFFFFFF)
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "DBEIR_L,Data bot error injection register"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "DBEIR_H,Data bot error injection register"
|
|
else
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x00 "DBEIR_L,Data bot error injection register"
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x00 "DBEIR_H,Data bot error injection register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "BOOTROM HARDWARE INTERFACE"
|
|
base ad:0xFFFEFC00
|
|
width 13.
|
|
wgroup.long 0x358++0x03
|
|
line.long 0x00 "UNLOCK,Lock Release Register"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "CNFG,Setting Register"
|
|
bitfld.long 0x00 8. " SWAP ,Exception vector register swap bit" "No effect,Swap"
|
|
rbitfld.long 0x00 0. " LST ,BootROM hardware interface lock status bit" "Unlocked,Locked"
|
|
group.long 0x384++0x0F
|
|
line.long 0x00 "UNDEFINACT,Undefined Instruction Vector Register"
|
|
line.long 0x04 "SVCINACT,Supervisor Call Vector Register"
|
|
line.long 0x08 "PABORTINACT,Prefetch Abort Vector Register"
|
|
line.long 0x0C "DABORTINACT,Data Abort Vector Register"
|
|
rgroup.long 0x3C4++0x0F
|
|
line.long 0x00 "UNDEFACT,Undefined Instruction Vector Register"
|
|
line.long 0x04 "SVCACT,Supervisor Call Vector Register"
|
|
line.long 0x08 "PABORTACT,Prefetch Abort Vector Register"
|
|
line.long 0x0C "DABORTACT,Data Abort Vector Register"
|
|
width 0x0B
|
|
tree.end
|
|
;tree "BOOTROM SOFTWARE INTERFACE"
|
|
; tree "TCM"
|
|
; base ad:0x009F00000
|
|
; %include s6j320/softint.ph
|
|
; tree.end
|
|
; sif (!cpuis("S6J311*"))&&(!cpuis("S6J312?HAA"))
|
|
; tree "AXI"
|
|
; base ad:0x019F0000
|
|
; %include s6j320/softint.ph
|
|
; tree.end
|
|
; endif
|
|
;tree.end
|
|
;tree "EAM (EXCLUSIVE ACCESS MEMORY)"
|
|
; base ad:0x02800000
|
|
; %include s6j320/eam.ph
|
|
;tree.end
|
|
tree "INTC (INTERRUPT CONTROLER)"
|
|
base ad:0xB0400000
|
|
width 10.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "NMIVAS,IRC NMI vector address status register"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "NMIST,IRC NMI Status register"
|
|
bitfld.long 0x00 8.--11. " NMIPS ,NMI priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " NMISN ,NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "IRQVAS,IRC IRQ vector address status register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "IRQST,IRC IRQ status register"
|
|
bitfld.long 0x00 24. " NIRQ ,IRQ interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16.--20. " IRQPS ,IRQ priority status bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " IRQSN ,IRQ channel number bits"
|
|
tree "NMI vector address registers"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "NMIVA0,(Ext-IRC) IRQ NMI vector address register"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "NMIVA4,(LVDs IRQ) IRQ NMI vector address register"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "NMIVA5,(CSV/Profile) IRQ NMI vector address register"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "NMIVA6,(HW-WDT) IRQ NMI vector address register"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "NMIVA7,(SW-WDT) IRQ NMI vector address register"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "NMIVA8,(IRC 2-bit ECC error detection) IRQ NMI vector address register"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "NMIVA11,(Backup RAM 2-bit ECC error detection) IRQ NMI vector address register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "NMIVA12,(CAN-FD RAMs 2-bit ECC error detection) IRQ NMI vector address register"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "NMIVA13,(DMAC MPU #0 protection violation) IRQ NMI vector address register"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "NMIVA15,(SHE MPU) IRQ NMI vector address register"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "NMIVA18,(TPU(s) protection violation) IRQ NMI vector address register"
|
|
tree.end
|
|
tree "IRQ vector address registers"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "IRQVA1,(System Control Status Interrupt Request) IRQ vector address register"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "IRQVA2,(HW-WDT Pre-warning Interrupt Request) IRQ vector address register"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "IRQVA3,(SW-WDT Pre-warning Interrupt Request) IRQ vector address register"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "IRQVA8,(TCFLASH Interrupt Request) IRQ vector address register"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "IRQVA10,(Work FLASH HANG Interrupt Request) IRQ vector address register"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "IRQVA14,(Scratch Pad RAM Single Bit Error Interrupt Request) IRQ vector address register"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "IRQVA15,(Backup RAM / CAN FD RAMs Single Bit Error Interrupt Request) IRQ vector address register"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "IRQVA16,(IRC0 Vector Address RAM Single Bit Error Interrupt Request) IRQ vector address register"
|
|
group.long 0xDC++0x3
|
|
line.long 0x00 "IRQVA19,(Debugger Interrupt Request) IRQ vector address register"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "IRQVA20,(Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request)IRQ vector address register"
|
|
group.long 0xEC++0x3
|
|
line.long 0x00 "IRQVA23,(EICU) IRQ vector address register"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "IRQVA24,(External Interrupt Request ch.0) IRQ vector address register"
|
|
group.long 0xF4++0x3
|
|
line.long 0x00 "IRQVA25,(External Interrupt Request ch.1) IRQ vector address register"
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "IRQVA26,(External Interrupt Request ch.2) IRQ vector address register"
|
|
group.long 0xFC++0x3
|
|
line.long 0x00 "IRQVA27,(External Interrupt Request ch.3) IRQ vector address register"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "IRQVA28,(External Interrupt Request ch.4) IRQ vector address register"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "IRQVA29,(External Interrupt Request ch.5) IRQ vector address register"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "IRQVA30,(External Interrupt Request ch.6) IRQ vector address register"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "IRQVA31,(External Interrupt Request ch.7) IRQ vector address register"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "IRQVA32,(External Interrupt Request ch.8) IRQ vector address register"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "IRQVA33,(External Interrupt Request ch.9) IRQ vector address register"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "IRQVA34,(External Interrupt Request ch.10) IRQ vector address register"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "IRQVA35,(External Interrupt Request ch.11) IRQ vector address register"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "IRQVA36,(External Interrupt Request ch.12) IRQ vector address register"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "IRQVA37,(External Interrupt Request ch.13) IRQ vector address register"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "IRQVA38,(External Interrupt Request ch.14) IRQ vector address register"
|
|
group.long 0x12C++0x3
|
|
line.long 0x00 "IRQVA39,(External Interrupt Request ch.15) IRQ vector address register"
|
|
group.long 0x170++0x3
|
|
line.long 0x00 "IRQVA56,(CAN-FD ch.0 (OR-ed of all factors)) IRQ vector address register"
|
|
sif !cpuis("S6J311?HAA")
|
|
group.long 0x174++0x3
|
|
line.long 0x00 "IRQVA57,(CAN-FD ch.1 (OR-ed of all factors)) IRQ vector address register"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x178++0x3
|
|
line.long 0x00 "IRQVA58,(CAN-FD ch.2 (OR-ed of all factors)) IRQ vector address register"
|
|
endif
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "IRQVA64,(M.F.S RX ch.0) IRQ vector address register"
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "IRQVA65,(M.F.S TX ch.0) IRQ vector address register"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "IRQVA66,(M.F.S Rx ch.1) IRQ vector address register"
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "IRQVA67,(M.F.S TX ch.1) IRQ vector address register"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "IRQVA68,(M.F.S Rx ch.2) IRQ vector address register"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "IRQVA69,(M.F.S TX ch.2) IRQ vector address register"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "IRQVA70,(M.F.S Rx ch.3) IRQ vector address register"
|
|
group.long 0x1AC++0x3
|
|
line.long 0x00 "IRQVA71,(M.F.S TX ch.3) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "IRQVA72,(M.F.S Rx ch.4) IRQ vector address register"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x00 "IRQVA73,(M.F.S TX ch.4) IRQ vector address register"
|
|
group.long 0x1D0++0x3
|
|
line.long 0x00 "IRQVA80,(M.F.S Rx ch.8) IRQ vector address register"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x00 "IRQVA81,(M.F.S TX ch.8) IRQ vector address register"
|
|
group.long 0x1D8++0x3
|
|
line.long 0x00 "IRQVA82,(M.F.S Rx ch.9) IRQ vector address register"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x00 "IRQVA83,(M.F.S TX ch.9) IRQ vector address register"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x00 "IRQVA84,(M.F.S Rx ch.10) IRQ vector address register"
|
|
group.long 0x1E4++0x3
|
|
line.long 0x00 "IRQVA85,(M.F.S TX ch.10) IRQ vector address register"
|
|
group.long 0x1E8++0x3
|
|
line.long 0x00 "IRQVA86,(M.F.S Rx ch.11) IRQ vector address register"
|
|
group.long 0x1EC++0x3
|
|
line.long 0x00 "IRQVA87,(M.F.S TX ch.11) IRQ vector address register"
|
|
group.long 0x1F0++0x3
|
|
line.long 0x00 "IRQVA88,(M.F.S Rx ch.12) IRQ vector address register"
|
|
group.long 0x1F4++0x3
|
|
line.long 0x00 "IRQVA89,(M.F.S TX ch.12) IRQ vector address register"
|
|
elif (!cpuis("S6J311?HAA"))
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "IRQVA72,(M.F.S Rx ch.4) IRQ vector address register"
|
|
group.long 0x1B4++0x3
|
|
line.long 0x00 "IRQVA73,(M.F.S TX ch.4) IRQ vector address register"
|
|
group.long 0x1B8++0x3
|
|
line.long 0x00 "IRQVA74,(M.F.S Rx ch.5) IRQ vector address register"
|
|
group.long 0x1BC++0x3
|
|
line.long 0x00 "IRQVA75,(M.F.S TX ch.5) IRQ vector address register"
|
|
group.long 0x1C0++0x3
|
|
line.long 0x00 "IRQVA76,(M.F.S Rx ch.6) IRQ vector address register"
|
|
group.long 0x1C4++0x3
|
|
line.long 0x00 "IRQVA77,(M.F.S TX ch.6) IRQ vector address register"
|
|
group.long 0x1C8++0x3
|
|
line.long 0x00 "IRQVA78,(M.F.S Rx ch.7) IRQ vector address register"
|
|
group.long 0x1CC++0x3
|
|
line.long 0x00 "IRQVA79,(M.F.S TX ch.7) IRQ vector address register"
|
|
endif
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "IRQVA100,(SHE Err IRQ) IRQ vector address register"
|
|
group.long 0x224++0x3
|
|
line.long 0x00 "IRQVA101,(SHE IRQ) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x228++0x3
|
|
line.long 0x00 "IRQVA102,(DDR_HSSPI ch.0 RX) IRQ vector address register"
|
|
group.long 0x22C++0x3
|
|
line.long 0x00 "IRQVA103,(DDR_HSSPI ch.0 TX) IRQ vector address register"
|
|
endif
|
|
group.long 0x248++0x3
|
|
line.long 0x00 "IRQVA110,(TCRAM diag) IRQ vector address register"
|
|
group.long 0x250++0x3
|
|
line.long 0x00 "IRQVA112,(Backup RAM diag) IRQ vector address register"
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "IRQVA116,(RTC+Calibration IRQ) IRQ vector address register"
|
|
group.long 0x264++0x3
|
|
line.long 0x00 "IRQVA117,(CR calibration IRQ) IRQ vector address register"
|
|
group.long 0x290++0x3
|
|
line.long 0x00 "IRQVA128,(Base Timer ch.0/8/9/10/11) IRQ vector address register"
|
|
group.long 0x294++0x3
|
|
line.long 0x00 "IRQVA129,(Base Timer ch.1) IRQ vector address register"
|
|
group.long 0x298++0x3
|
|
line.long 0x00 "IRQVA130,(Base Timer ch.2) IRQ vector address register"
|
|
group.long 0x29C++0x3
|
|
line.long 0x00 "IRQVA131,(Base Timer ch.3) IRQ vector address register"
|
|
group.long 0x2A0++0x3
|
|
line.long 0x00 "IRQVA132,(Base Timer ch.4) IRQ vector address register"
|
|
group.long 0x2A4++0x3
|
|
line.long 0x00 "IRQVA133,(Base Timer ch.5) IRQ vector address register"
|
|
group.long 0x2A8++0x3
|
|
line.long 0x00 "IRQVA134,(Base Timer ch.6) IRQ vector address register"
|
|
group.long 0x2AC++0x3
|
|
line.long 0x00 "IRQVA135,(Base Timer ch.7) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x2F0++0x3
|
|
line.long 0x00 "IRQVA152,(Reload Timer ch.0) IRQ vector address register"
|
|
group.long 0x2F4++0x3
|
|
line.long 0x00 "IRQVA153,(Reload Timer ch.1) IRQ vector address register"
|
|
group.long 0x2F8++0x3
|
|
line.long 0x00 "IRQVA154,(Reload Timer ch.2) IRQ vector address register"
|
|
group.long 0x2FC++0x3
|
|
line.long 0x00 "IRQVA155,(Reload Timer ch.3) IRQ vector address register"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "IRQVA160,(Reload Timer ch.16) IRQ vector address register"
|
|
group.long 0x314++0x3
|
|
line.long 0x00 "IRQVA161,(Reload Timer ch.17) IRQ vector address register"
|
|
group.long 0x318++0x3
|
|
line.long 0x00 "IRQVA162,(Reload Timer ch.18) IRQ vector address register"
|
|
group.long 0x31C++0x3
|
|
line.long 0x00 "IRQVA163,(Reload Timer ch.19) IRQ vector address register"
|
|
group.long 0x330++0x3
|
|
line.long 0x00 "IRQVA168,(Reload Timer ch.32) IRQ vector address register"
|
|
group.long 0x334++0x3
|
|
line.long 0x00 "IRQVA169,(Reload Timer ch.33) IRQ vector address register"
|
|
endif
|
|
group.long 0x350++0x3
|
|
line.long 0x00 "IRQVA176,(FRT ch.0) IRQ vector address register"
|
|
group.long 0x354++0x3
|
|
line.long 0x00 "IRQVA177,(FRT ch.1) IRQ vector address register"
|
|
group.long 0x358++0x3
|
|
line.long 0x00 "IRQVA178,(FRT ch.2) IRQ vector address register"
|
|
group.long 0x35C++0x3
|
|
line.long 0x00 "IRQVA179,(FRT ch.3) IRQ vector address register"
|
|
group.long 0x360++0x3
|
|
line.long 0x00 "IRQVA180,(FRT ch.4) IRQ vector address register"
|
|
group.long 0x364++0x3
|
|
line.long 0x00 "IRQVA181,(FRT ch.5) IRQ vector address register"
|
|
group.long 0x390++0x3
|
|
line.long 0x00 "IRQVA192,(ICU ch.0) IRQ vector address register"
|
|
group.long 0x394++0x3
|
|
line.long 0x00 "IRQVA193,(ICU ch.2) IRQ vector address register"
|
|
group.long 0x398++0x3
|
|
line.long 0x00 "IRQVA194,(ICU ch.4) IRQ vector address register"
|
|
group.long 0x39C++0x3
|
|
line.long 0x00 "IRQVA195,(ICU ch.6) IRQ vector address register"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x00 "IRQVA196,(ICU ch.8) IRQ vector address register"
|
|
group.long 0x3A4++0x3
|
|
line.long 0x00 "IRQVA197,(ICU ch.10) IRQ vector address register"
|
|
group.long 0x3D0++0x3
|
|
line.long 0x00 "IRQVA208,(OCU ch.0) IRQ vector address register"
|
|
group.long 0x3D4++0x3
|
|
line.long 0x00 "IRQVA209,(OCU ch.2) IRQ vector address register"
|
|
group.long 0x3D8++0x3
|
|
line.long 0x00 "IRQVA210,(OCU ch.4) IRQ vector address register"
|
|
group.long 0x3DC++0x3
|
|
line.long 0x00 "IRQVA211,(OCU ch.6) IRQ vector address register"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x00 "IRQVA212,(OCU ch.8) IRQ vector address register"
|
|
group.long 0x3E4++0x3
|
|
line.long 0x00 "IRQVA213,(OCU ch.10) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x430++0x3
|
|
line.long 0x00 "IRQVA232,(QPRC ch.8) IRQ vector address register"
|
|
group.long 0x434++0x3
|
|
line.long 0x00 "IRQVA233,(QPRC ch.9) IRQ vector address register"
|
|
endif
|
|
group.long 0x450++0x3
|
|
line.long 0x00 "IRQVA240,(ICU ch.1) IRQ vector address register"
|
|
group.long 0x454++0x3
|
|
line.long 0x00 "IRQVA241,(ICU ch.3) IRQ vector address register"
|
|
group.long 0x458++0x3
|
|
line.long 0x00 "IRQVA242,(ICU ch.5) IRQ vector address register"
|
|
group.long 0x45C++0x3
|
|
line.long 0x00 "IRQVA243,(ICU ch.7) IRQ vector address register"
|
|
group.long 0x460++0x3
|
|
line.long 0x00 "IRQVA244,(ICU ch.9) IRQ vector address register"
|
|
group.long 0x464++0x3
|
|
line.long 0x00 "IRQVA245,(ICU ch.11) IRQ vector address register"
|
|
group.long 0x490++0x3
|
|
line.long 0x00 "IRQVA256,(OCU ch.1) IRQ vector address register"
|
|
group.long 0x494++0x3
|
|
line.long 0x00 "IRQVA257,(OCU ch.3) IRQ vector address register"
|
|
group.long 0x498++0x3
|
|
line.long 0x00 "IRQVA258,(OCU ch.5) IRQ vector address register"
|
|
group.long 0x49C++0x3
|
|
line.long 0x00 "IRQVA259,(OCU ch.7) IRQ vector address register"
|
|
group.long 0x4A0++0x3
|
|
line.long 0x00 "IRQVA260,(OCU ch.9) IRQ vector address register"
|
|
group.long 0x4A4++0x3
|
|
line.long 0x00 "IRQVA261,(OCU ch.11) IRQ vector address register"
|
|
group.long 0x4D0++0x3
|
|
line.long 0x00 "IRQVA272,(DMA Error Interrupt Request) IRQ vector address register"
|
|
group.long 0x4D4++0x3
|
|
line.long 0x00 "IRQVA273,(DMA Completion Interrupt Request ch.0) IRQ vector address register"
|
|
group.long 0x4D8++0x3
|
|
line.long 0x00 "IRQVA274,(DMA Completion Interrupt Request ch.1) IRQ vector address register"
|
|
group.long 0x4DC++0x3
|
|
line.long 0x00 "IRQVA275,(DMA Completion Interrupt Request ch.2) IRQ vector address register"
|
|
group.long 0x4E0++0x3
|
|
line.long 0x00 "IRQVA276,(DMA Completion Interrupt Request ch.3) IRQ vector address register"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x00 "IRQVA277,(DMA Completion Interrupt Request ch.4) IRQ vector address register"
|
|
group.long 0x4E8++0x3
|
|
line.long 0x00 "IRQVA278,(DMA Completion Interrupt Request ch.5) IRQ vector address register"
|
|
group.long 0x4EC++0x3
|
|
line.long 0x00 "IRQVA279,(DMA Completion Interrupt Request ch.6) IRQ vector address register"
|
|
group.long 0x4F0++0x3
|
|
line.long 0x00 "IRQVA280,(DMA Completion Interrupt Request ch.7) IRQ vector address register"
|
|
group.long 0x4F8++0x3
|
|
line.long 0x00 "IRQVA282,(DMAC RLT ch.0/1/2/3) IRQ vector address register"
|
|
group.long 0x504++0x3
|
|
line.long 0x00 "IRQVA285,(DMA Completion Interrupt Request ch.8) IRQ vector address register"
|
|
group.long 0x508++0x3
|
|
line.long 0x00 "IRQVA286,(DMA Completion Interrupt Request ch.9) IRQ vector address register"
|
|
group.long 0x50C++0x3
|
|
line.long 0x00 "IRQVA287,(DMA Completion Interrupt Request ch.10) IRQ vector address register"
|
|
group.long 0x510++0x3
|
|
line.long 0x00 "IRQVA288,(DMA Completion Interrupt Request ch.11) IRQ vector address register"
|
|
group.long 0x514++0x3
|
|
line.long 0x00 "IRQVA289,(DMA Completion Interrupt Request ch.12) IRQ vector address register"
|
|
group.long 0x518++0x3
|
|
line.long 0x00 "IRQVA290,(DMA Completion Interrupt Request ch.13) IRQ vector address register"
|
|
group.long 0x51C++0x3
|
|
line.long 0x00 "IRQVA291,(DMA Completion Interrupt Request ch.14) IRQ vector address register"
|
|
group.long 0x520++0x3
|
|
line.long 0x00 "IRQVA292,(DMA Completion Interrupt Request ch.15) IRQ vector address register"
|
|
group.long 0x560++0x3
|
|
line.long 0x00 "IRQVA308,(SCT RC IRQ) IRQ vector address register"
|
|
group.long 0x564++0x3
|
|
line.long 0x00 "IRQVA309,(SCT SRC IRQ) IRQ vector address register"
|
|
group.long 0x568++0x3
|
|
line.long 0x00 "IRQVA310,(SCT Main OSC IRQ) IRQ vector address register"
|
|
group.long 0x570++0x3
|
|
line.long 0x00 "IRQVA312,(CR5 Performance Monitor Unit IRQ) IRQ vector address register"
|
|
group.long 0x574++0x3
|
|
line.long 0x00 "IRQVA313,(BPC IRQs) IRQ vector address register"
|
|
group.long 0x590++0x3
|
|
line.long 0x00 "IRQVA320,(M.F.S Error ch.0) IRQ vector address register"
|
|
group.long 0x594++0x3
|
|
line.long 0x00 "IRQVA321,(M.F.S Error ch.1) IRQ vector address register"
|
|
group.long 0x598++0x3
|
|
line.long 0x00 "IRQVA322,(M.F.S Error ch.2) IRQ vector address register"
|
|
group.long 0x59C++0x3
|
|
line.long 0x00 "IRQVA323,(M.F.S Error ch.3) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x5A0++0x3
|
|
line.long 0x00 "IRQVA324,(M.F.S Error ch.4) IRQ vector address register"
|
|
group.long 0x5B0++0x3
|
|
line.long 0x00 "IRQVA328,(M.F.S Error ch.8) IRQ vector address register"
|
|
group.long 0x5B4++0x3
|
|
line.long 0x00 "IRQVA329,(M.F.S Error ch.9) IRQ vector address register"
|
|
group.long 0x5B8++0x3
|
|
line.long 0x00 "IRQVA330,(M.F.S Error ch.10) IRQ vector address register"
|
|
group.long 0x5BC++0x3
|
|
line.long 0x00 "IRQVA331,(M.F.S Error ch.11) IRQ vector address register"
|
|
group.long 0x5C0++0x3
|
|
line.long 0x00 "IRQVA332,(M.F.S Error ch.12) IRQ vector address register"
|
|
elif (!cpuis("S6J311?HAA"))
|
|
group.long 0x5A0++0x3
|
|
line.long 0x00 "IRQVA324,(M.F.S Error ch.4) IRQ vector address register"
|
|
group.long 0x5A4++0x3
|
|
line.long 0x00 "IRQVA325,(M.F.S Error ch.5) IRQ vector address register"
|
|
group.long 0x5A8++0x3
|
|
line.long 0x00 "IRQVA326,(M.F.S Error ch.6) IRQ vector address register"
|
|
group.long 0x5AC++0x3
|
|
line.long 0x00 "IRQVA327,(M.F.S Error ch.7) IRQ vector address register"
|
|
group.long 0x5DC++0x3
|
|
line.long 0x00 "IRQVA339,(M.F.S RX ch.8) IRQ vector address register"
|
|
group.long 0x5E0++0x3
|
|
line.long 0x00 "IRQVA340,(M.F.S TX ch.8) IRQ vector address register"
|
|
group.long 0x5E4++0x3
|
|
line.long 0x00 "IRQVA341,(M.F.S RX ch.9) IRQ vector address register"
|
|
group.long 0x5E8++0x3
|
|
line.long 0x00 "IRQVA342,(M.F.S TX ch.9) IRQ vector address register"
|
|
group.long 0x5EC++0x3
|
|
line.long 0x00 "IRQVA343,(M.F.S RX ch.10) IRQ vector address register"
|
|
group.long 0x5F0++0x3
|
|
line.long 0x00 "IRQVA344,(M.F.S TX ch.10) IRQ vector address register"
|
|
group.long 0x5F4++0x3
|
|
line.long 0x00 "IRQVA345,(M.F.S RX ch.11) IRQ vector address register"
|
|
group.long 0x5F8++0x3
|
|
line.long 0x00 "IRQVA346,(M.F.S TX ch.11) IRQ vector address register"
|
|
group.long 0x5FC++0x3
|
|
line.long 0x00 "IRQVA347,(M.F.S RX ch.12) IRQ vector address register"
|
|
group.long 0x600++0x3
|
|
line.long 0x00 "IRQVA348,(M.F.S TX ch.12) IRQ vector address register"
|
|
group.long 0x604++0x3
|
|
line.long 0x00 "IRQVA349,(M.F.S RX ch.13) IRQ vector address register"
|
|
group.long 0x608++0x3
|
|
line.long 0x00 "IRQVA350,(M.F.S TX ch.13) IRQ vector address register"
|
|
group.long 0x60C++0x3
|
|
line.long 0x00 "IRQVA351,(M.F.S RX ch.14) IRQ vector address register"
|
|
group.long 0x610++0x3
|
|
line.long 0x00 "IRQVA352,(M.F.S TX ch.14) IRQ vector address register"
|
|
group.long 0x614++0x3
|
|
line.long 0x00 "IRQVA353,(M.F.S RX ch.15) IRQ vector address register"
|
|
group.long 0x618++0x3
|
|
line.long 0x00 "IRQVA354,(M.F.S TX ch.15) IRQ vector address register"
|
|
group.long 0x61C++0x3
|
|
line.long 0x00 "IRQVA355,(M.F.S RX ch.16) IRQ vector address register"
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "IRQVA356,(M.F.S TX ch.16) IRQ vector address register"
|
|
group.long 0x624++0x3
|
|
line.long 0x00 "IRQVA357,(M.F.S RX ch.17) IRQ vector address register"
|
|
group.long 0x628++0x3
|
|
line.long 0x00 "IRQVA358,(M.F.S TX ch.17) IRQ vector address register"
|
|
group.long 0x62C++0x3
|
|
line.long 0x00 "IRQVA359,(M.F.S RX ch.18) IRQ vector address register"
|
|
group.long 0x630++0x3
|
|
line.long 0x00 "IRQVA360,(M.F.S TX ch.18) IRQ vector address register"
|
|
group.long 0x634++0x3
|
|
line.long 0x00 "IRQVA361,(M.F.S RX ch.19) IRQ vector address register"
|
|
group.long 0x638++0x3
|
|
line.long 0x00 "IRQVA362,(M.F.S TX ch.19) IRQ vector address register"
|
|
group.long 0x63C++0x3
|
|
line.long 0x00 "IRQVA363,(M.F.S RX ch.20) IRQ vector address register"
|
|
group.long 0x640++0x3
|
|
line.long 0x00 "IRQVA364,(M.F.S TX ch.20) IRQ vector address register"
|
|
group.long 0x644++0x3
|
|
line.long 0x00 "IRQVA365,(M.F.S RX ch.21) IRQ vector address register"
|
|
group.long 0x648++0x3
|
|
line.long 0x00 "IRQVA366,(M.F.S TX ch.21) IRQ vector address register"
|
|
group.long 0x64C++0x3
|
|
line.long 0x00 "IRQVA367,(M.F.S Error ch.8) IRQ vector address register"
|
|
group.long 0x650++0x3
|
|
line.long 0x00 "IRQVA368,(M.F.S Error ch.9) IRQ vector address register"
|
|
group.long 0x654++0x3
|
|
line.long 0x00 "IRQVA369,(M.F.S Error ch.10) IRQ vector address register"
|
|
group.long 0x658++0x3
|
|
line.long 0x00 "IRQVA370,(M.F.S Error ch.11) IRQ vector address register"
|
|
group.long 0x65C++0x3
|
|
line.long 0x00 "IRQVA371,(M.F.S Error ch.12) IRQ vector address register"
|
|
group.long 0x660++0x3
|
|
line.long 0x00 "IRQVA372,(M.F.S Error ch.13) IRQ vector address register"
|
|
group.long 0x664++0x3
|
|
line.long 0x00 "IRQVA373,(M.F.S Error ch.14) IRQ vector address register"
|
|
group.long 0x668++0x3
|
|
line.long 0x00 "IRQVA374,(M.F.S Error ch.15) IRQ vector address register"
|
|
group.long 0x66C++0x3
|
|
line.long 0x00 "IRQVA375,(M.F.S Error ch.16) IRQ vector address register"
|
|
group.long 0x670++0x3
|
|
line.long 0x00 "IRQVA376,(M.F.S Error ch.17) IRQ vector address register"
|
|
group.long 0x674++0x3
|
|
line.long 0x00 "IRQVA377,(M.F.S Error ch.18) IRQ vector address register"
|
|
group.long 0x678++0x3
|
|
line.long 0x00 "IRQVA378,(M.F.S Error ch.19) IRQ vector address register"
|
|
group.long 0x67C++0x3
|
|
line.long 0x00 "IRQVA379,(M.F.S Error ch.20) IRQ vector address register"
|
|
group.long 0x680++0x3
|
|
line.long 0x00 "IRQVA380,(M.F.S Error ch.21) IRQ vector address register"
|
|
endif
|
|
group.long 0x684++0x3
|
|
line.long 0x00 "IRQVA381,(Base Timer ch.12/20/21/22/23) IRQ vector address register"
|
|
group.long 0x688++0x3
|
|
line.long 0x00 "IRQVA382,(Base Timer ch.13) IRQ vector address register"
|
|
group.long 0x68C++0x3
|
|
line.long 0x00 "IRQVA383,(Base Timer ch.14) IRQ vector address register"
|
|
group.long 0x690++0x3
|
|
line.long 0x00 "IRQVA384,(Base Timer ch.15) IRQ vector address register"
|
|
group.long 0x694++0x3
|
|
line.long 0x00 "IRQVA385,(Base Timer ch.16) IRQ vector address register"
|
|
group.long 0x698++0x3
|
|
line.long 0x00 "IRQVA386,(Base Timer ch.17) IRQ vector address register"
|
|
group.long 0x69C++0x3
|
|
line.long 0x00 "IRQVA387,(Base Timer ch.18) IRQ vector address register"
|
|
group.long 0x6A0++0x3
|
|
line.long 0x00 "IRQVA388,(Base Timer ch.19) IRQ vector address register"
|
|
group.long 0x6A4++0x3
|
|
line.long 0x00 "IRQVA389,(Base Timer ch.24) IRQ vector address register"
|
|
group.long 0x6A8++0x3
|
|
line.long 0x00 "IRQVA390,(Base Timer ch.25) IRQ vector address register"
|
|
group.long 0x6AC++0x3
|
|
line.long 0x00 "IRQVA391,(Base Timer ch.26) IRQ vector address register"
|
|
group.long 0x6B0++0x3
|
|
line.long 0x00 "IRQVA392,(Base Timer ch.27) IRQ vector address register"
|
|
group.long 0x6B4++0x3
|
|
line.long 0x00 "IRQVA393,(Base Timer ch.28) IRQ vector address register"
|
|
group.long 0x6B8++0x3
|
|
line.long 0x00 "IRQVA394,(Base Timer ch.29) IRQ vector address register"
|
|
group.long 0x6BC++0x3
|
|
line.long 0x00 "IRQVA395,(A/D unit.0 Scan Conversion End) IRQ vector address register"
|
|
group.long 0x6C0++0x3
|
|
line.long 0x00 "IRQVA396,(A/D unit.0 A/D Conversion End) IRQ vector address register"
|
|
group.long 0x6C4++0x3
|
|
line.long 0x00 "IRQVA397,(A/D unit.0 Range Compare) IRQ vector address register"
|
|
group.long 0x6C8++0x3
|
|
line.long 0x00 "IRQVA398,(A/D unit.1 Scan Conversion End) IRQ vector address register"
|
|
group.long 0x6CC++0x3
|
|
line.long 0x00 "IRQVA399,(A/D unit.1 A/D Conversion End) IRQ vector address register"
|
|
group.long 0x6D0++0x3
|
|
line.long 0x00 "IRQVA400,(A/D unit.1 Range Compare) IRQ vector address register"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x6E0++0x3
|
|
line.long 0x00 "IRQVA404,(Sound Generator ch.0) IRQ vector address register"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x00 "IRQVA405,(Sound Generator ch.1) IRQ vector address register"
|
|
group.long 0x6E8++0x3
|
|
line.long 0x00 "IRQVA406,(Sound Generator ch.2) IRQ vector address register"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
tree "NMI priority level registers"
|
|
group.long 0x890++0x13
|
|
line.long 0x00 "NMIPL0,NMI Priority Level Register"
|
|
bitfld.long 0x00 0.--3. " NMIPL0 ,NMI (Ext-IRC) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "NMIPL1,NMI Priority Level Register"
|
|
bitfld.long 0x04 24.--27. " NMIPL3 ,NMI3 (LVDs IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " NMIPL2 ,NMI2 (CSV/Profile) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " NMIPL1 ,NMI1 (HW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " NMIPL0 ,NMI0 (SW-WDT) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "NMIPL2,NMI Priority Level Register"
|
|
bitfld.long 0x08 24.--27. " NMIPL3 ,NMI3 (IRC 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " NMIPL0 ,NMI0 (Backup RAM 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "NMIPL3,NMI Priority Level Register"
|
|
bitfld.long 0x0C 24.--27. " NMIPL3 ,NMI3 (CAN-FD RAMs 2-bit ECC error detection) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " NMIPL1 ,NMI1 (DMAC MPU #0 protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " NMIPL0 ,NMI0 (SHE MPU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "NMIPL4,NMI Priority Level Register"
|
|
bitfld.long 0x10 16.--19. " NMIPL2 ,NMI2 (TPU(s) protection violation) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 10.
|
|
tree "IRQ priority level registers"
|
|
group.long 0x8B0++0x3
|
|
line.long 0x00 "IRQPL0,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (SW-WDT Pre-warning Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (HW-WDT Pre-warning Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (System Control Status Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8B8++0x3
|
|
line.long 0x00 "IRQPL2,IRQ priority level register"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Work FLASH HANG Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (TCFLASH Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8BC++0x3
|
|
line.long 0x00 "IRQPL3,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Backup RAM/CAN FD RAMs Single Bit Error Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Scratch Pad RAM Single Bit Error Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8C0++0x3
|
|
line.long 0x00 "IRQPL4,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Debugger Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (IRC0 Vector Address RAM Single Bit Error Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8C4++0x3
|
|
line.long 0x00 "IRQPL5,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (EICU) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8C8++0x3
|
|
line.long 0x00 "IRQPL6,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (External Interrupt Request ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (External Interrupt Request ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (External Interrupt Request ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (External Interrupt Request ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8CC++0x3
|
|
line.long 0x00 "IRQPL7,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (External Interrupt Request ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (External Interrupt Request ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (External Interrupt Request ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (External Interrupt Request ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8D0++0x3
|
|
line.long 0x00 "IRQPL8,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (External Interrupt Request ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (External Interrupt Request ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (External Interrupt Request ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (External Interrupt Request ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8D4++0x3
|
|
line.long 0x00 "IRQPL9,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (External Interrupt Request ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (External Interrupt Request ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (External Interrupt Request ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (External Interrupt Request ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8E8++0x3
|
|
line.long 0x00 "IRQPL14,IRQ priority level register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (CAN-FD ch.2 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (CAN-FD ch.1 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (CAN-FD ch.0 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif !cpuis("S6J311?HAA")
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (CAN-FD ch.1 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (CAN-FD ch.0 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (CAN-FD ch.0 (OR-ed of all factors)) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x8F0++0x3
|
|
line.long 0x00 "IRQPL16,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S RX ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8F4++0x3
|
|
line.long 0x00 "IRQPL17,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x8F8++0x3
|
|
line.long 0x00 "IRQPL18,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x900++0x3
|
|
line.long 0x00 "IRQPL20,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x904++0x3
|
|
line.long 0x00 "IRQPL21,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x908++0x3
|
|
line.long 0x00 "IRQPL22,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif !cpuis("S6J311?HAA")
|
|
group.long 0x8F8++0x3
|
|
line.long 0x00 "IRQPL18,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x8FC++0x3
|
|
line.long 0x00 "IRQPL19,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S TX ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Rx ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S TX ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Rx ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x914++0x3
|
|
line.long 0x00 "IRQPL25,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL3 ,IRQ3 (DDR_HSSPI ch.0 TX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL2 ,IRQ2 (DDR_HSSPI ch.0 RX) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (SHE IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (SHE Err IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x914++0x3
|
|
line.long 0x00 "IRQPL25,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (SHE IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (SHE Err IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x91C++0x3
|
|
line.long 0x00 "IRQPL27,IRQ priority level register"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (TCRAM diag) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "IRQPL28,IRQ priority level register"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Backup RAM diag) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x924++0x3
|
|
line.long 0x00 "IRQPL29,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (CR calibration IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (RTC+Calibration IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x930++0x3
|
|
line.long 0x00 "IRQPL32,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Base Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Base Timer ch.0/8/9/10/11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x934++0x3
|
|
line.long 0x00 "IRQPL33,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Base Timer ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Base Timer ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x948++0x3
|
|
line.long 0x00 "IRQPL38,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Reload Timer ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Reload Timer ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Reload Timer ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Reload Timer ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x950++0x3
|
|
line.long 0x00 "IRQPL40,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Reload Timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Reload Timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Reload Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Reload Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x958++0x3
|
|
line.long 0x00 "IRQPL42,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Reload Timer ch.33) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Reload Timer ch.32) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x960++0x3
|
|
line.long 0x00 "IRQPL44,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (FRT ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (FRT ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (FRT ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (FRT ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x964++0x3
|
|
line.long 0x00 "IRQPL45,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (FRT ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (FRT ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x970++0x3
|
|
line.long 0x00 "IRQPL48,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (ICU ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (ICU ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (ICU ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (ICU ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x974++0x3
|
|
line.long 0x00 "IRQPL49,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (ICU ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (ICU ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x980++0x3
|
|
line.long 0x00 "IRQPL52,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (OCU ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (OCU ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (OCU ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (OCU ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x984++0x3
|
|
line.long 0x00 "IRQPL53,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (OCU ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (OCU ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x998++0x3
|
|
line.long 0x00 "IRQPL58,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (QPRC ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (QPRC ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x9A0++0x3
|
|
line.long 0x00 "IRQPL60,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (ICU ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (ICU ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (ICU ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (ICU ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9A4++0x3
|
|
line.long 0x00 "IRQPL61,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (ICU ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (ICU ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9B0++0x3
|
|
line.long 0x00 "IRQPL64,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (OCU ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (OCU ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (OCU ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (OCU ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9B4++0x3
|
|
line.long 0x00 "IRQPL65,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (OCU ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (OCU ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9C0++0x3
|
|
line.long 0x00 "IRQPL68,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (DMA Completion Interrupt Request ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (DMA Completion Interrupt Request ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (DMA Completion Interrupt Request ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (DMA Error Interrupt Request) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9C4++0x3
|
|
line.long 0x00 "IRQPL69,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (DMA Completion Interrupt Request ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (DMA Completion Interrupt Request ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (DMA Completion Interrupt Request ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (DMA Completion Interrupt Request ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x00 "IRQPL70,IRQ priority level register"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (DMAC RLT ch.0/1/2/3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (DMA Completion Interrupt Request ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9CC++0x3
|
|
line.long 0x00 "IRQPL71,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (DMA Completion Interrupt Request ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (DMA Completion Interrupt Request ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (DMA Completion Interrupt Request ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9D0++0x3
|
|
line.long 0x00 "IRQPL72,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (DMA Completion Interrupt Request ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (DMA Completion Interrupt Request ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (DMA Completion Interrupt Request ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (DMA Completion Interrupt Request ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9D4++0x3
|
|
line.long 0x00 "IRQPL73,IRQ priority level register"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (DMA Completion Interrupt Request ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9E4++0x3
|
|
line.long 0x00 "IRQPL77,IRQ priority level register"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (SCT Main OSC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (SCT SRC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (SCT RC IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9E8++0x3
|
|
line.long 0x00 "IRQPL78,IRQ priority level register"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (BPC IRQs) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (CR5 Performance Monitor Unit IRQ) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9F0++0x3
|
|
line.long 0x00 "IRQPL80,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.3) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0x9F4++0x3
|
|
line.long 0x00 "IRQPL81,IRQ priority level register"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9F8++0x3
|
|
line.long 0x00 "IRQPL82,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x9FC++0x3
|
|
line.long 0x00 "IRQPL83,IRQ priority level register"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif !cpuis("S6J311?HAA")
|
|
group.long 0x9F4++0x3
|
|
line.long 0x00 "IRQPL81,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.7) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.6) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.5) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.4) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA00++0x3
|
|
line.long 0x00 "IRQPL84,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA04++0x3
|
|
line.long 0x00 "IRQPL85,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA08++0x3
|
|
line.long 0x00 "IRQPL86,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA0C++0x3
|
|
line.long 0x00 "IRQPL87,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA10++0x3
|
|
line.long 0x00 "IRQPL88,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA14++0x3
|
|
line.long 0x00 "IRQPL89,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA18++0x3
|
|
line.long 0x00 "IRQPL90,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S RX ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA1C++0x3
|
|
line.long 0x00 "IRQPL91,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.8) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S TX ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S RX ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S TX ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA20++0x3
|
|
line.long 0x00 "IRQPL92,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.12) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.11) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.10) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.9) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA24++0x3
|
|
line.long 0x00 "IRQPL93,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA28++0x3
|
|
line.long 0x00 "IRQPL94,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (M.F.S Error ch.20) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (M.F.S Error ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (M.F.S Error ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0xA2C++0x3
|
|
line.long 0x00 "IRQPL95,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Base Timer ch.14) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.13) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.12/20/21/22/23) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J311?JAA")
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (M.F.S Error ch.21) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0xA30++0x3
|
|
line.long 0x00 "IRQPL96,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Base Timer ch.18) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.17) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.16) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Base Timer ch.15) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA34++0x3
|
|
line.long 0x00 "IRQPL97,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (Base Timer ch.26) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.25) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.24) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Base Timer ch.19) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA38++0x3
|
|
line.long 0x00 "IRQPL98,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (A/D unit.0 Scan Conversion End) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Base Timer ch.29) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Base Timer ch.28) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Base Timer ch.27) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA3C++0x3
|
|
line.long 0x00 "IRQPL99,IRQ priority level register"
|
|
bitfld.long 0x00 24.--28. " IRQPL3 ,IRQ3 (A/D unit.1 A/D Conversion End) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (A/D unit.1 Scan Conversion End) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (A/D unit.0 Range Compare) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (A/D unit.0 A/D Conversion End) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "IRQPL100,IRQ priority level register"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (A/D unit.1 Range Compare) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("S6J312?HAA")
|
|
group.long 0xA44++0x3
|
|
line.long 0x00 "IRQPL101,IRQ priority level register"
|
|
bitfld.long 0x00 16.--20. " IRQPL2 ,IRQ2 (Sound Generator ch.2) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " IRQPL1 ,IRQ1 (Sound Generator ch.1) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " IRQPL0 ,IRQ0 (Sound Generator ch.0) priority level bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
tree.end
|
|
textline ""
|
|
width 16.
|
|
group.long 0xAB8++0x3
|
|
line.long 0x00 "NMISIS_SET/CLR,IRC NMI software interrupt status register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " NMISIS[18]_set/clr ,NMI (TPU(s) protection violation) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,NMI (SHE MPU) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,NMI (DMAC MPU #0 protection violation) software interrupt status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,NMI (CAN-FD RAMs 2-bit ECC error detection) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,NMI (Backup RAM 2-bit ECC error detection) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x08 08. -0x04 08. " [08] ,NMI (IRC 2-bit ECC error detection) software interrupt status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 07. -0x08 07. -0x04 07. " [07] ,NMI (SW-WDT) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x08 06. -0x04 06. " [06] ,NMI (HW-WDT) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x08 05. -0x04 05. " [05] ,NMI (CSV/Profile) software interrupt status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 04. -0x08 04. -0x04 04. " [04] ,NMI (LVDs IRQ) software interrupt status bit" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x08 01. -0x04 00. " [00] ,NMI (NMIX pin (Ext-IRC)) software interrupt status bit" "No interrupt,Interrupt"
|
|
tree "IRC IRQ software interrupt status registers"
|
|
width 17.
|
|
group.long 0xB40++0x3
|
|
line.long 0x00 "IRQSIS0_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQSIS_[31] ,IRQ (External Interrupt Request ch.7) software interrupt status bit 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [30] ,IRQ (External Interrupt Request ch.6) software interrupt status bit 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [29] ,IRQ (External Interrupt Request ch.5) software interrupt status bit 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [28] ,IRQ (External Interrupt Request ch.4) software interrupt status bit 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [27] ,IRQ (External Interrupt Request ch.3) software interrupt status bit 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [26] ,IRQ (External Interrupt Request ch.2) software interrupt status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [25] ,IRQ (External Interrupt Request ch.1) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [24] ,IRQ (External Interrupt Request ch.0) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [23] ,IRQ (EICU) software interrupt status bit 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [20] ,IRQ (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [19] ,IRQ (Debugger Interrupt Request) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [16] ,IRQ (IRC0 Vector Address RAM Single Bit Error Interrupt Request)software interrupt status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [15] ,IRQ (Backup RAM/CAN FD RAMs Single Bit Error Interrupt Request) software interrupt status bit 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [14] ,IRQ (Scratch Pad RAM Single Bit Error Interrupt Request)software interrupt status bit 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [10] ,IRQ (Work FLASH HANG Interrupt Request) software interrupt status bit 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [8] ,IRQ (TCFLASH Interrupt Request) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [3] ,IRQ (SW-WDT Pre-warning Interrupt Request) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [2] ,IRQ (HW-WDT Pre-warning Interrupt Request) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [1] ,IRQ (System Control Status Interrupt Request) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
group.long 0xB44++0x3
|
|
line.long 0x00 "IRQSIS1_SET/CLR,IRC IRQ software interrupt status register"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (CAN-FD ch.2) software interrupt status bit 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (CAN-FD ch.1) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (CAN-FD ch.1) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (External Interrupt Request ch.15) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (External Interrupt Request ch.14) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (External Interrupt Request ch.13) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (External Interrupt Request ch.12) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (External Interrupt Request ch.11) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (External Interrupt Request ch.10) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (External Interrupt Request ch.9) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [32] ,IRQ (External Interrupt Request ch.8) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB48++0x3
|
|
line.long 0x00 "IRQSIS2_SET/CLR,IRC IRQ software interrupt status register"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [89] ,IRQ (M.F.S TX ch.12) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [88] ,IRQ (M.F.S Rx ch.12) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [87] ,IRQ (M.F.S TX ch.11) software interrupt status bit 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [86] ,IRQ (M.F.S Rx ch.11) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [85] ,IRQ (M.F.S TX ch.10) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [84] ,IRQ (M.F.S Rx ch.10) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [83] ,IRQ (M.F.S TX ch.9) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [82] ,IRQ (M.F.S Rx ch.9) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [81] ,IRQ (M.F.S TX ch.8) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [80] ,IRQ (M.F.S Rx ch.8) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [73] ,IRQ (M.F.S TX ch.4) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [72] ,IRQ (M.F.S Rx ch.4) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [79] ,IRQ (M.F.S TX ch.7) software interrupt status bit 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [78] ,IRQ (M.F.S Rx ch.7) software interrupt status bit 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [77] ,IRQ (M.F.S TX ch.6) software interrupt status bit 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [76] ,IRQ (M.F.S Rx ch.6) software interrupt status bit 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [75] ,IRQ (M.F.S TX ch.5) software interrupt status bit 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [74] ,IRQ (M.F.S Rx ch.5) software interrupt status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [73] ,IRQ (M.F.S TX ch.4) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [72] ,IRQ (M.F.S Rx ch.4) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [71] ,IRQ (M.F.S TX ch.3) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [70] ,IRQ (M.F.S Rx ch.3) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [69] ,IRQ (M.F.S TX ch.2) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [68] ,IRQ (M.F.S Rx ch.2) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [67] ,IRQ (M.F.S TX ch.1) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [66] ,IRQ (M.F.S Rx ch.1) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [65] ,IRQ (M.F.S TX ch.0) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [64] ,IRQ (M.F.S RX ch.0) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB4C++0x3
|
|
line.long 0x00 "IRQSIS3_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [117] ,IRQ (CR calibration IRQ) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [116] ,IRQ (RTC+Calibration IRQ) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [112] ,IRQ (Backup RAM diag) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [110] ,IRQ (TCRAM diag) software interrupt status bit 14" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [103] ,IRQ (DDR_HSSPI ch.0 TX) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [102] ,IRQ (DDR_HSSPI ch.0 RX) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [101] ,IRQ (SHE IRQ) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [100] ,IRQ (SHE Err IRQ) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [101] ,IRQ (SHE IRQ) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [100] ,IRQ (SHE Err IRQ) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0xB50++0x3
|
|
line.long 0x00 "IRQSIS4_SET/CLR,IRC IRQ software interrupt status register"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [155] ,IRQ (Reload Timer ch.3) software interrupt status bit 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [154] ,IRQ (Reload Timer ch.2) software interrupt status bit 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [153] ,IRQ (Reload Timer ch.1) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [152] ,IRQ (Reload Timer ch.0) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [135] ,IRQ (Base Timer ch.7) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [134] ,IRQ (Base Timer ch.6) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [133] ,IRQ (Base Timer ch.5) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [132] ,IRQ (Base Timer ch.4) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [131] ,IRQ (Base Timer ch.3) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [130] ,IRQ (Base Timer ch.2) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [129] ,IRQ (Base Timer ch.1) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [128] ,IRQ (Base Timer ch.0/8/9/10/11) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB54++0x3
|
|
line.long 0x00 "IRQSIS5_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [181] ,IRQ (FRT ch.5) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [180] ,IRQ (FRT ch.4) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [179] ,IRQ (FRT ch.3) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [178] ,IRQ (FRT ch.2) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [177] ,IRQ (FRT ch.1) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [176] ,IRQ (FRT ch.0) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x80 9. -0x40 9. " [169] ,IRQ (Reload Timer ch.33) software interrupt status bit 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " [168] ,IRQ (Reload Timer ch.32) software interrupt status bit 8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " [163] ,IRQ (Reload Timer ch.19) software interrupt status bit 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " [162] ,IRQ (Reload Timer ch.18) software interrupt status bit 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " [161] ,IRQ (Reload Timer ch.17) software interrupt status bit 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x80 0. -0x40 0. " [160] ,IRQ (Reload Timer ch.16) software interrupt status bit 0" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0xB58++0x3
|
|
line.long 0x00 "IRQSIS6_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [213] ,IRQ (OCU ch.10) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [212] ,IRQ (OCU ch.8) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [211] ,IRQ (OCU ch.6) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [210] ,IRQ (OCU ch.4) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [209] ,IRQ (OCU ch.2) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [208] ,IRQ (OCU ch.0) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [197] ,IRQ (ICU ch.10) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [196] ,IRQ (ICU ch.8) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [195] ,IRQ (ICU ch.6) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [194] ,IRQ (ICU ch.4) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [193] ,IRQ (ICU ch.2) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [192] ,IRQ (ICU ch.0) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB5C++0x3
|
|
line.long 0x00 "IRQSIS7_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [245] ,IRQ (ICU ch.11) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [244] ,IRQ (ICU ch.9) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [243] ,IRQ (ICU ch.7) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [242] ,IRQ (ICU ch.5) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [241] ,IRQ (ICU ch.3) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [240] ,IRQ (ICU ch.1) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [233] ,IRQ (QPRC ch.9) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [232] ,IRQ (QPRC ch.8) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0xB60++0x3
|
|
line.long 0x00 "IRQSIS8_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [287] ,IRQ (DMA Completion Interrupt Request ch.10) software interrupt status bit 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [286] ,IRQ (DMA Completion Interrupt Request ch.9) software interrupt status bit 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [285] ,IRQ (DMA Completion Interrupt Request ch.8) software interrupt status bit 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [282] ,IRQ (DMAC RLT ch.0/1/2/3)software interrupt status bit 26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [280] ,IRQ (DMA Completion Interrupt Request ch.7) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [279] ,IRQ (DMA Completion Interrupt Request ch.6) software interrupt status bit 23" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [278] ,IRQ (DMA Completion Interrupt Request ch.5) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [277] ,IRQ (DMA Completion Interrupt Request ch.4) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [276] ,IRQ (DMA Completion Interrupt Request ch.3) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [275] ,IRQ (DMA Completion Interrupt Request ch.2) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [274] ,IRQ (DMA Completion Interrupt Request ch.1) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [273] ,IRQ (DMA Completion Interrupt Request ch.0) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [272] ,IRQ (DMA Error Interrupt Request) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [261] ,IRQ (OCU ch.11) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [260] ,IRQ (OCU ch.9) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [259] ,IRQ (OCU ch.7) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [258] ,IRQ (OCU ch.5) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [257] ,IRQ (OCU ch.3) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [256] ,IRQ (OCU ch.1) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB64++0x3
|
|
line.long 0x00 "IRQSIS9_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [313] ,IRQ (BPC IRQs) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [312] ,IRQ (CR5 Performance Monitor Unit IRQ) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [310] ,IRQ (SCT Main OSC IRQ) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [309] ,IRQ (SCT SRC IRQ) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [308] ,IRQ (SCT RC IRQ) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [292] ,IRQ (DMA Completion Interrupt Request ch.15) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [291] ,IRQ (DMA Completion Interrupt Request ch.14) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [290] ,IRQ (DMA Completion Interrupt Request ch.13) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [289] ,IRQ (DMA Completion Interrupt Request ch.12) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [288] ,IRQ (DMA Completion Interrupt Request ch.11) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB68++0x3
|
|
line.long 0x00 "IRQSIS10_SET/CLR,IRC IRQ software interrupt status register"
|
|
sif (cpuis("S6J311?JAA"))
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [351] ,IRQ (M.F.S RX ch.14) software interrupt status bit 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [350] ,IRQ (M.F.S TX ch.13) software interrupt status bit 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [349] ,IRQ (M.F.S RX ch.13) software interrupt status bit 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [348] ,IRQ (M.F.S TX ch.12) software interrupt status bit 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [347] ,IRQ (M.F.S RX ch.12) software interrupt status bit 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [346] ,IRQ (M.F.S TX ch.11) software interrupt status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [345] ,IRQ (M.F.S RX ch.11) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [344] ,IRQ (M.F.S TX ch.10) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [343] ,IRQ (M.F.S RX ch.10) software interrupt status bit 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [342] ,IRQ (M.F.S TX ch.9) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [341] ,IRQ (M.F.S RX ch.9) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [340] ,IRQ (M.F.S TX ch.8) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [339] ,IRQ (M.F.S RX ch.8) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [327] ,IRQ (M.F.S Error ch.7) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [326] ,IRQ (M.F.S Error ch.6) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [325] ,IRQ (M.F.S Error ch.5) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [324] ,IRQ (M.F.S Error ch.4) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [332] ,IRQ (M.F.S Error ch.12) software interrupt status bit 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [331] ,IRQ (M.F.S Error ch.11) software interrupt status bit 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [330] ,IRQ (M.F.S Error ch.10) software interrupt status bit 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [329] ,IRQ (M.F.S Error ch.9) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [328] ,IRQ (M.F.S Error ch.8) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [324] ,IRQ (M.F.S Error ch.4) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [323] ,IRQ (M.F.S Error ch.3) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [322] ,IRQ (M.F.S Error ch.2) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [321] ,IRQ (M.F.S Error ch.1) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [320] ,IRQ (M.F.S Error ch.0) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
group.long 0xB6C++0x3
|
|
line.long 0x00 "IRQSIS11_SET/CLR,IRC IRQ software interrupt status register"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [383] ,IRQ (Base Timer ch.14) software interrupt status bit 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [382] ,IRQ (Base Timer ch.13) software interrupt status bit 30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [381] ,IRQ (Base Timer ch.12/20/21/22/23) software interrupt status bit 29" "No interrupt,Interrupt"
|
|
sif (cpuis("S6J311?JAA"))
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [380] ,IRQ (M.F.S Error ch.21) software interrupt status bit 28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [379] ,IRQ (M.F.S Error ch.20) software interrupt status bit 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [378] ,IRQ (M.F.S Error ch.19) software interrupt status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [377] ,IRQ (M.F.S Error ch.18) software interrupt status bit 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [376] ,IRQ (M.F.S Error ch.17) software interrupt status bit 24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [375] ,IRQ (M.F.S Error ch.16) software interrupt status bit 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [374] ,IRQ (M.F.S Error ch.15) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [373] ,IRQ (M.F.S Error ch.14) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [372] ,IRQ (M.F.S Error ch.13) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [371] ,IRQ (M.F.S Error ch.12) software interrupt status bit 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [370] ,IRQ (M.F.S Error ch.11) software interrupt status bit 18" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [369] ,IRQ (M.F.S Error ch.10) software interrupt status bit 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [368] ,IRQ (M.F.S Error ch.9) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [367] ,IRQ (M.F.S Error ch.8) software interrupt status bit 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [366] ,IRQ (M.F.S TX ch.21) software interrupt status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [365] ,IRQ (M.F.S RX ch.21) software interrupt status bit 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [364] ,IRQ (M.F.S TX ch.20) software interrupt status bit 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [363] ,IRQ (M.F.S RX ch.20) software interrupt status bit 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [362] ,IRQ (M.F.S TX ch.19) software interrupt status bit 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [361] ,IRQ (M.F.S RX ch.19) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [360] ,IRQ (M.F.S TX ch.18) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [359] ,IRQ (M.F.S RX ch.18) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [358] ,IRQ (M.F.S TX ch.17) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [357] ,IRQ (M.F.S RX ch.17) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [356] ,IRQ (M.F.S TX ch.16) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [355] ,IRQ (M.F.S RX ch.16) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [354] ,IRQ (M.F.S TX ch.15) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [353] ,IRQ (M.F.S RX ch.15) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [352] ,IRQ (M.F.S TX ch.14) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0xB70++0x3
|
|
line.long 0x00 "IRQSIS12_SET/CLR,IRC IRQ software interrupt status register"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [406] ,IRQ (Sound Generator ch.2) software interrupt status bit 22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [405] ,IRQ (Sound Generator ch.1) software interrupt status bit 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [404] ,IRQ (Sound Generator ch.0) software interrupt status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [400] ,IRQ (A/D unit.1 Range Compare) software interrupt status bit 16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [399] ,IRQ (A/D unit.1 A/D Conversion End) software interrupt status bit 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [398] ,IRQ (A/D unit.1 Scan Conversion End) software interrupt status bit 14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [397] ,IRQ (A/D unit.0 Range Compare) software interrupt status bit 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [396] ,IRQ (A/D unit.0 A/D Conversion End) software interrupt status bit 12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [395] ,IRQ (A/D unit.0 Scan Conversion End) software interrupt status bit 11" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [394] ,IRQ (Base Timer ch.29) software interrupt status bit 10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [393] ,IRQ (Base Timer ch.28) software interrupt status bit 09" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [392] ,IRQ (Base Timer ch.27) software interrupt status bit 08" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [391] ,IRQ (Base Timer ch.26) software interrupt status bit 07" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [390] ,IRQ (Base Timer ch.25) software interrupt status bit 06" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [389] ,IRQ (Base Timer ch.24) software interrupt status bit 05" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [388] ,IRQ (Base Timer ch.19) software interrupt status bit 04" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [387] ,IRQ (Base Timer ch.18) software interrupt status bit 03" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [386] ,IRQ (Base Timer ch.17) software interrupt status bit 02" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [385] ,IRQ (Base Timer ch.16) software interrupt status bit 01" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [384] ,IRQ (Base Timer ch.15) software interrupt status bit 00" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRC IRQ channel enable registers"
|
|
width 17.
|
|
group.long 0xC00++0x3
|
|
line.long 0x00 "IRQCE00_SET/CLR,IRC IRQ channel enable setting register 00"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " IRQCE_[31] ,IRQ (External Interrupt Request ch.7) channel enable setting bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [30] ,IRQ (External Interrupt Request ch.6) channel enable setting bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [29] ,IRQ (External Interrupt Request ch.5) channel enable setting bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [28] ,IRQ (External Interrupt Request ch.4) channel enable setting bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [27] ,IRQ (External Interrupt Request ch.3) channel enable setting bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [26] ,IRQ (External Interrupt Request ch.2) channel enable setting bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [25] ,IRQ (External Interrupt Request ch.1) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [24] ,IRQ (External Interrupt Request ch.0) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [23] ,IRQ (EICU) channel enable setting bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [20] ,IRQ (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [19] ,IRQ (Debugger Interrupt Request) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [16] ,IRQ (IRC0 Vector Address RAM Single Bit Error Interrupt Request) channel enable setting bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [15] ,IRQ (Backup RAM / CAN FD RAMs Single Bit Error Interrupt Request) channel enable setting bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [14] ,IRQ (Scratch Pad RAM Single Bit Error Interrupt Request) channel enable setting bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [10] ,IRQ (Work FLASH HANG Interrupt Request) channel enable setting bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [8] ,IRQ (TCFLASH Interrupt Request) channel enable setting bit 08" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [3] ,IRQ (SW-WDT Pre-warning Interrupt Request) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [2] ,IRQ (HW-WDT Pre-warning Interrupt Request) channel enable setting bit 02" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [1] ,IRQ (System Control Status Interrupt Request) channel enable setting bit 01" "Disabled,Enabled"
|
|
group.long 0xC04++0x3
|
|
line.long 0x00 "IRQCE01_SET/CLR,IRC IRQ channel enable setting register 01"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [58] ,IRQ (CAN-FD ch.2) channel enable setting bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (CAN-FD ch.1) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) channel enable setting bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("S6J311?HAA")
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [57] ,IRQ (CAN-FD ch.1) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) channel enable setting bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [56] ,IRQ (CAN-FD ch.0) channel enable setting bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [39] ,IRQ (External Interrupt Request ch.15) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [38] ,IRQ (External Interrupt Request ch.14) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [37] ,IRQ (External Interrupt Request ch.13) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [36] ,IRQ (External Interrupt Request ch.12) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [35] ,IRQ (External Interrupt Request ch.11) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [34] ,IRQ (External Interrupt Request ch.10) channel enable setting bit 02" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [33] ,IRQ (External Interrupt Request ch.9) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [32] ,IRQ (External Interrupt Request ch.8) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC08++0x3
|
|
line.long 0x00 "IRQCE02_SET/CLR,IRC IRQ channel enable setting register 02"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [89] ,IRQ (M.F.S TX ch.12) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [88] ,IRQ (M.F.S Rx ch.12) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [87] ,IRQ (M.F.S TX ch.11) channel enable setting bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [86] ,IRQ (M.F.S Rx ch.11) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [85] ,IRQ (M.F.S TX ch.10) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [84] ,IRQ (M.F.S Rx ch.10) channel enable setting bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [83] ,IRQ (M.F.S TX ch.9) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [82] ,IRQ (M.F.S Rx ch.9) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [81] ,IRQ (M.F.S TX ch.8) channel enable setting bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [80] ,IRQ (M.F.S Rx ch.8) channel enable setting bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [73] ,IRQ (M.F.S TX ch.4) channel enable setting bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [72] ,IRQ (M.F.S Rx ch.4) channel enable setting bit 08" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("S6J311?HAA")
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [79] ,IRQ (M.F.S TX ch.7) channel enable setting bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [78] ,IRQ (M.F.S Rx ch.7) channel enable setting bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [77] ,IRQ (M.F.S TX ch.6) channel enable setting bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [76] ,IRQ (M.F.S Rx ch.6) channel enable setting bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [75] ,IRQ (M.F.S TX ch.5) channel enable setting bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [74] ,IRQ (M.F.S Rx ch.5) channel enable setting bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [73] ,IRQ (M.F.S TX ch.4) channel enable setting bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [72] ,IRQ (M.F.S Rx ch.4) channel enable setting bit 08" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [71] ,IRQ (M.F.S TX ch.3) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [70] ,IRQ (M.F.S Rx ch.3) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [69] ,IRQ (M.F.S TX ch.2) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [68] ,IRQ (M.F.S Rx ch.2) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [67] ,IRQ (M.F.S TX ch.1) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [66] ,IRQ (M.F.S Rx ch.1) channel enable setting bit 02" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [65] ,IRQ (M.F.S TX ch.0) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [64] ,IRQ (M.F.S RX ch.0) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC0C++0x3
|
|
line.long 0x00 "IRQCE03_SET/CLR,IRC IRQ channel enable setting register 03"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [117] ,IRQ (CR calibration IRQ) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [116] ,IRQ (RTC+Calibration IRQ) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [112] ,IRQ (Backup RAM diag) channel enable setting bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [110] ,IRQ (TCRAM diag) channel enable setting bit 14" "Disabled,Enabled"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [103] ,IRQ (DDR_HSSPI ch.0 TX) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [102] ,IRQ (DDR_HSSPI ch.0 RX) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [101] ,IRQ (SHE IRQ) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [100] ,IRQ (SHE Err IRQ) channel enable setting bit 04" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [101] ,IRQ (SHE IRQ) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [100] ,IRQ (SHE Err IRQ) channel enable setting bit 04" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC10++0x3
|
|
line.long 0x00 "IRQCE04_SET/CLR,IRC IRQ channel enable setting register 04"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [155] ,IRQ (Reload Timer ch.3) channel enable setting bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [154] ,IRQ (Reload Timer ch.2) channel enable setting bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [153] ,IRQ (Reload Timer ch.1) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [152] ,IRQ (Reload Timer ch.0) channel enable setting bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [135] ,IRQ (Base Timer ch.7) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [134] ,IRQ (Base Timer ch.6) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [133] ,IRQ (Base Timer ch.5) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [132] ,IRQ (Base Timer ch.4) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [131] ,IRQ (Base Timer ch.3) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [130] ,IRQ (Base Timer ch.2) channel enable setting bit 02" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [129] ,IRQ (Base Timer ch.1) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [128] ,IRQ (Base Timer ch.0/8/9/10/11) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC14++0x3
|
|
line.long 0x00 "IRQCE05_SET/CLR,IRC IRQ channel enable setting register 05"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [181] ,IRQ (FRT ch.5) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [180] ,IRQ (FRT ch.4) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [179] ,IRQ (FRT ch.3) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [178] ,IRQ (FRT ch.2) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [177] ,IRQ (FRT ch.1) channel enable setting bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [176] ,IRQ (FRT ch.0) channel enable setting bit 16" "Disabled,Enabled"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 9. -0x80 9. -0x40 9. " [169] ,IRQ (Reload Timer ch.33) channel enable setting bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x80 8. -0x40 8. " [168] ,IRQ (Reload Timer ch.32) channel enable setting bit 8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x80 3. -0x40 3. " [163] ,IRQ (Reload Timer ch.19) channel enable setting bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x80 2. -0x40 2. " [162] ,IRQ (Reload Timer ch.18) channel enable setting bit 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x80 1. -0x40 1. " [161] ,IRQ (Reload Timer ch.17) channel enable setting bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x80 0. -0x40 0. " [160] ,IRQ (Reload Timer ch.16) channel enable setting bit 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC18++0x3
|
|
line.long 0x00 "IRQCE06_SET/CLR,IRC IRQ channel enable setting register 06"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [213] ,IRQ (OCU ch.10) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [212] ,IRQ (OCU ch.8) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [211] ,IRQ (OCU ch.6) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [210] ,IRQ (OCU ch.4) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [209] ,IRQ (OCU ch.2) channel enable setting bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [208] ,IRQ (OCU ch.0) channel enable setting bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [197] ,IRQ (ICU ch.10) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [196] ,IRQ (ICU ch.8) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [195] ,IRQ (ICU ch.6) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [194] ,IRQ (ICU ch.4) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [193] ,IRQ (ICU ch.2) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [192] ,IRQ (ICU ch.0) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC1C++0x3
|
|
line.long 0x00 "IRQCE07_SET/CLR,IRC IRQ channel enable setting register 07"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [245] ,IRQ (ICU ch.11) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [244] ,IRQ (ICU ch.9) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [243] ,IRQ (ICU ch.7) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [242] ,IRQ (ICU ch.5) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [241] ,IRQ (ICU ch.3) channel enable setting bit 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [240] ,IRQ (ICU ch.1) channel enable setting bit 16" "Disabled,Enabled"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [233] ,IRQ (QPRC ch.9) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [232] ,IRQ (QPRC ch.8) channel enable setting bit 18" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC20++0x3
|
|
line.long 0x00 "IRQCE08_SET/CLR,IRC IRQ channel enable setting register 08"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [287] ,IRQ (DMA Completion Interrupt Request ch.10) channel enable setting bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [286] ,IRQ (DMA Completion Interrupt Request ch.9) channel enable setting bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [285] ,IRQ (DMA Completion Interrupt Request ch.8) channel enable setting bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [282] ,IRQ (DMAC RLT ch.0/1/2/3) channel enable setting bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [280] ,IRQ (DMA Completion Interrupt Request ch.7) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [279] ,IRQ (DMA Completion Interrupt Request ch.6) channel enable setting bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [278] ,IRQ (DMA Completion Interrupt Request ch.5) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [277] ,IRQ (DMA Completion Interrupt Request ch.4) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [276] ,IRQ (DMA Completion Interrupt Request ch.3) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [275] ,IRQ (DMA Completion Interrupt Request ch.2) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [274] ,IRQ (DMA Completion Interrupt Request ch.1) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [273] ,IRQ (DMA Completion Interrupt Request ch.0) channel enable setting bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [272] ,IRQ (DMA Error Interrupt Request) channel enable setting bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [261] ,IRQ (OCU ch.11) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [260] ,IRQ (OCU ch.9) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [259] ,IRQ (OCU ch.7) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [258] ,IRQ (OCU ch.5) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [257] ,IRQ (OCU ch.3) channel enable setting bit 01" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [256] ,IRQ (OCU ch.1) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC24++0x3
|
|
line.long 0x00 "IRQCE09_SET/CLR,IRC IRQ channel enable setting register 09"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [313] ,IRQ (BPC IRQs) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [312] ,IRQ (CR5 Performance Monitor Unit IRQ) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [310] ,IRQ (SCT Main OSC IRQ) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [309] ,IRQ (SCT SRC IRQ) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [308] ,IRQ (SCT RC IRQ) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [292] ,IRQ (DMA Completion Interrupt Request ch.15) channel enable setting bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [291] ,IRQ (DMA Completion Interrupt Request ch.14) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [290] ,IRQ (DMA Completion Interrupt Request ch.13) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [289] ,IRQ (DMA Completion Interrupt Request ch.12) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [288] ,IRQ (DMA Completion Interrupt Request ch.11) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC28++0x3
|
|
line.long 0x00 "IRQCE10_SET/CLR,IRC IRQ channel enable setting register 10"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [332] ,IRQ (M.F.S RX ch.12) channel enable setting bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [331] ,IRQ (M.F.S Error ch.11) channel enable setting bit 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [330] ,IRQ (M.F.S Error ch.10) channel enable setting bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [329] ,IRQ (M.F.S Error ch.9) channel enable setting bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [328] ,IRQ (M.F.S Error ch.8) channel enable setting bit 08" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [324] ,IRQ (M.F.S Error ch.4) channel enable setting bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
elif !cpuis("S6J311?HAA")
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [351] ,IRQ (M.F.S RX ch.14) channel enable setting bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [350] ,IRQ (M.F.S TX ch.13) channel enable setting bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [349] ,IRQ (M.F.S RX ch.13) channel enable setting bit 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [348] ,IRQ (M.F.S TX ch.12) channel enable setting bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [347] ,IRQ (M.F.S RX ch.12) channel enable setting bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [346] ,IRQ (M.F.S TX ch.11) channel enable setting bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [345] ,IRQ (M.F.S RX ch.11) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [344] ,IRQ (M.F.S TX ch.10) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [343] ,IRQ (M.F.S RX ch.10) channel enable setting bit 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [342] ,IRQ (M.F.S TX ch.9) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [341] ,IRQ (M.F.S RX ch.9) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [340] ,IRQ (M.F.S TX ch.8) channel enable setting bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [339] ,IRQ (M.F.S RX ch.8) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [327] ,IRQ (M.F.S Error ch.7) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [326] ,IRQ (M.F.S Error ch.6) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [325] ,IRQ (M.F.S Error ch.5) channel enable setting bit 05" "Disabled,Enabled"
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [324] ,IRQ (M.F.S Error ch.4) channel enable setting bit 04" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [323] ,IRQ (M.F.S Error ch.3) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [322] ,IRQ (M.F.S Error ch.2) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [321] ,IRQ (M.F.S Error ch.1) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [320] ,IRQ (M.F.S Error ch.0) channel enable setting bit 00" "Disabled,Enabled"
|
|
group.long 0xC2C++0x3
|
|
line.long 0x00 "IRQCE11_SET/CLR,IRC IRQ channel enable setting register 11"
|
|
setclrfld.long 0x00 31. -0x80 31. -0x40 31. " [383] ,IRQ (Base Timer ch.14) channel enable setting bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x80 30. -0x40 30. " [382] ,IRQ (Base Timer ch.13) channel enable setting bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x80 29. -0x40 29. " [381] ,IRQ (Base Timer ch.12/20/21/22/23) channel enable setting bit 29" "Disabled,Enabled"
|
|
sif !cpuis("S6J311?HAA")&&!cpuis("S6J312?HAA")
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x80 28. -0x40 28. " [380] ,IRQ (M.F.S Error ch.21) channel enable setting bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x80 27. -0x40 27. " [379] ,IRQ (M.F.S Error ch.20) channel enable setting bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x80 26. -0x40 26. " [378] ,IRQ (M.F.S Error ch.19) channel enable setting bit 26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x80 25. -0x40 25. " [377] ,IRQ (M.F.S Error ch.18) channel enable setting bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x80 24. -0x40 24. " [376] ,IRQ (M.F.S Error ch.17) channel enable setting bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x80 23. -0x40 23. " [375] ,IRQ (M.F.S Error ch.16) channel enable setting bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [374] ,IRQ (M.F.S Error ch.15) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [373] ,IRQ (M.F.S Error ch.14) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [372] ,IRQ (M.F.S Error ch.13) channel enable setting bit 20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x80 19. -0x40 19. " [371] ,IRQ (M.F.S Error ch.12) channel enable setting bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x80 18. -0x40 18. " [370] ,IRQ (M.F.S Error ch.11) channel enable setting bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x80 17. -0x40 17. " [369] ,IRQ (M.F.S Error ch.10) channel enable setting bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [368] ,IRQ (M.F.S Error ch.9) channel enable setting bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [367] ,IRQ (M.F.S Error ch.8) channel enable setting bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [366] ,IRQ (M.F.S TX ch.21) channel enable setting bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [365] ,IRQ (M.F.S RX ch.21) channel enable setting bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [364] ,IRQ (M.F.S TX ch.20) channel enable setting bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [363] ,IRQ (M.F.S RX ch.20) channel enable setting bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [362] ,IRQ (M.F.S TX ch.19) channel enable setting bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [361] ,IRQ (M.F.S RX ch.19) channel enable setting bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [360] ,IRQ (M.F.S TX ch.18) channel enable setting bit 08" "Disabled,Enabled"
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [359] ,IRQ (M.F.S RX ch.18) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [358] ,IRQ (M.F.S TX ch.17) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [357] ,IRQ (M.F.S RX ch.17) channel enable setting bit 05" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [356] ,IRQ (M.F.S TX ch.16) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [355] ,IRQ (M.F.S RX ch.16) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [354] ,IRQ (M.F.S TX ch.15) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [353] ,IRQ (M.F.S RX ch.15) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [352] ,IRQ (M.F.S TX ch.14) channel enable setting bit 00" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC30++0x3
|
|
line.long 0x00 "IRQCE12_SET/CLR,IRC IRQ channel enable setting register 12"
|
|
sif cpuis("S6J312?HAA")
|
|
setclrfld.long 0x00 22. -0x80 22. -0x40 22. " [406] ,IRQ (Sound Generator ch.2) channel enable setting bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x80 21. -0x40 21. " [405] ,IRQ (Sound Generator ch.1) channel enable setting bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x80 20. -0x40 20. " [404] ,IRQ (Sound Generator ch.0) channel enable setting bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 16. -0x80 16. -0x40 16. " [400] ,IRQ (A/D unit.1 Range Compare) channel enable setting bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x80 15. -0x40 15. " [399] ,IRQ (A/D unit.1 A/D Conversion End) channel enable setting bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x80 14. -0x40 14. " [398] ,IRQ (A/D unit.1 Scan Conversion End) channel enable setting bit 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x80 13. -0x40 13. " [397] ,IRQ (A/D unit.0 Range Compare) channel enable setting bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x80 12. -0x40 12. " [396] ,IRQ (A/D unit.0 A/D Conversion End) channel enable setting bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x80 11. -0x40 11. " [395] ,IRQ (A/D unit.0 Scan Conversion End) channel enable setting bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x80 10. -0x40 10. " [394] ,IRQ (Base Timer ch.29) channel enable setting bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 09. -0x80 09. -0x40 09. " [393] ,IRQ (Base Timer ch.28) channel enable setting bit 09" "Disabled,Enabled"
|
|
setclrfld.long 0x00 08. -0x80 08. -0x40 08. " [392] ,IRQ (Base Timer ch.27) channel enable setting bit 08" "Disabled,Enabled"
|
|
setclrfld.long 0x00 07. -0x80 07. -0x40 07. " [391] ,IRQ (Base Timer ch.26) channel enable setting bit 07" "Disabled,Enabled"
|
|
setclrfld.long 0x00 06. -0x80 06. -0x40 06. " [390] ,IRQ (Base Timer ch.25) channel enable setting bit 06" "Disabled,Enabled"
|
|
setclrfld.long 0x00 05. -0x80 05. -0x40 05. " [389] ,IRQ (Base Timer ch.24) channel enable setting bit 05" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 04. -0x80 04. -0x40 04. " [388] ,IRQ (Base Timer ch.19) channel enable setting bit 04" "Disabled,Enabled"
|
|
setclrfld.long 0x00 03. -0x80 03. -0x40 03. " [387] ,IRQ (Base Timer ch.18) channel enable setting bit 03" "Disabled,Enabled"
|
|
setclrfld.long 0x00 02. -0x80 02. -0x40 02. " [386] ,IRQ (Base Timer ch.17) channel enable setting bit 02" "Disabled,Enabled"
|
|
setclrfld.long 0x00 01. -0x80 01. -0x40 01. " [385] ,IRQ (Base Timer ch.16) channel enable setting bit 01" "Disabled,Enabled"
|
|
setclrfld.long 0x00 00. -0x80 01. -0x40 00. " [384] ,IRQ (Base Timer ch.15) channel enable setting bit 00" "Disabled,Enabled"
|
|
tree.end
|
|
textline ""
|
|
width 7.
|
|
group.long 0xC40++0x3
|
|
line.long 0x00 "NMIHC,IRC NMI Hold Clear Register"
|
|
bitfld.long 0x00 0.--4. " NMIHCN ,Hold clear NMI channel number bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0xC44++0x3
|
|
line.long 0x00 "NMIHS,IRC NMI Hold Status Register"
|
|
bitfld.long 0x00 18. " NMIHS_[18] ,NMI18 (TPU(s) protection violation) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 15. " [15] ,NMI15 (SHE MPU) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " [13] ,NMI13 (DMAC MPU #0 protection violation) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 12. " [12] ,NMI12 (CAN-FD RAMs 2-bit ECC error detection) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " [11] ,NMI11 (Backup RAM 2-bit ECC error detection) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [8] ,NMI8 (IRC 2-bit ECC error detection) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,NMI7 (SW-WDT) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [6] ,NMI6 (HW-WDT) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [5] ,NMI5 (CSV/Profile) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [4] ,NMI4 (LVDs IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [0] ,NMI0 (NMIX pin (Ext-IRC)) hold status bit" "Not applied,Applied"
|
|
group.long 0xC48++0x3
|
|
line.long 0x00 "IRQHC,IRC IRQ Hold Clear Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " IRQHCN ,Bits for IRQ channel number for which holds to be cleared"
|
|
width 9.
|
|
tree "IRQHS 0-511"
|
|
rgroup.long 0xC50++0x3
|
|
line.long 0x00 "IRQHS0,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 31. " IRQHS_[31] ,IRQ31 (External Interrupt Request ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " [30] ,IRQ30 (External Interrupt Request ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " [29] ,IRQ29 (External Interrupt Request ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 28. " [28] ,IRQ28 (External Interrupt Request ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 27. " [27] ,IRQ27 (External Interrupt Request ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " [26] ,IRQ26 (External Interrupt Request ch.2) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,IRQ25 (External Interrupt Request ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [24] ,IRQ24 (External Interrupt Request ch.0) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [23] ,IRQ23 (EICU) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [20] ,IRQ20 (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " [19] ,IRQ19 (Debugger Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [16] ,IRQ16 (IRC0 Vector Address RAM Single Bit Error Interrupt Request) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,IRQ15 (Backup RAM / CAN FD RAMs Single Bit Error Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 14. " [14] ,IRQ14 (Scratch Pad RAM Single Bit Error Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 10. " [10] ,IRQ10 (Work FLASH HANG Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [8] ,IRQ8 (TCFLASH Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [3] ,IRQ3 (SW-WDT Pre-warning Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [2] ,IRQ2 (HW-WDT Pre-warning Interrupt Request) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,IRQ1 (System Control Status Interrupt Request) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC54++0x3
|
|
line.long 0x00 "IRQHS1,IRC IRQ Hold Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 26. " [58] ,IRQ58 (CAN-FD ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.0) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [39] ,IRQ39 (External Interrupt Request ch.15) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [38] ,IRQ38 (External Interrupt Request ch.14) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [37] ,IRQ37 (External Interrupt Request ch.13) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [36] ,IRQ36 (External Interrupt Request ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [35] ,IRQ35 (External Interrupt Request ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [34] ,IRQ34 (External Interrupt Request ch.10) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [33] ,IRQ33 (External Interrupt Request ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [32] ,IRQ32 (External Interrupt Request ch.8) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC58++0x3
|
|
line.long 0x00 "IRQHS2,IRC IRQ Hold Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 25. " [89] ,IRQ73 (M.F.S TX ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [88] ,IRQ72 (M.F.S Rx ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [87] ,IRQ72 (M.F.S Rx ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " [86] ,IRQ72 (M.F.S Rx ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [85] ,IRQ72 (M.F.S Rx ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [84] ,IRQ72 (M.F.S Rx ch.10) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [83] ,IRQ73 (M.F.S TX ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [82] ,IRQ72 (M.F.S Rx ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [81] ,IRQ72 (M.F.S Rx ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [80] ,IRQ72 (M.F.S Rx ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 15. " [79] ,IRQ79 (M.F.S TX ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 14. " [78] ,IRQ78 (M.F.S Rx ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " [77] ,IRQ77 (M.F.S TX ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 12. " [76] ,IRQ76 (M.F.S Rx ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " [75] ,IRQ75 (M.F.S TX ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 10. " [74] ,IRQ74 (M.F.S Rx ch.5) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [71] ,IRQ71 (M.F.S TX ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [70] ,IRQ70 (M.F.S Rx ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [69] ,IRQ69 (M.F.S TX ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [68] ,IRQ68 (M.F.S Rx ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [67] ,IRQ67 (M.F.S TX ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [66] ,IRQ66 (M.F.S Rx ch.1) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [65] ,IRQ65 (M.F.S TX ch.0) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [64] ,IRQ64 (M.F.S RX ch.0) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC5C++0x3
|
|
line.long 0x00 "IRQHS3,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 21. " [117] ,IRQ117 (CR calibration IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [116] ,IRQ116 (RTC+Calibration IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [112] ,IRQ112 (Backup RAM diag) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 14. " [110] ,IRQ110 (TCRAM diag) hold status bit" "Not applied,Applied"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 5. " [103] ,IRQ103 (DDR_HSSPI ch.0 TX) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [102] ,IRQ102 (DDR_HSSPI ch.0 RX) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) hold status bit" "Not applied,Applied"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) hold status bit" "Not applied,Applied"
|
|
endif
|
|
rgroup.long 0xC60++0x3
|
|
line.long 0x00 "IRQHS4,IRC IRQ Hold Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 27. " [155] ,IRQ155 (Reload Timer ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " [154] ,IRQ154 (Reload Timer ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 25. " [153] ,IRQ153 (Reload Timer ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [152] ,IRQ152 (Reload Timer ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [135] ,IRQ135 (Base Timer ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [134] ,IRQ134 (Base Timer ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [133] ,IRQ133 (Base Timer ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [132] ,IRQ132 (Base Timer ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [131] ,IRQ131 (Base Timer ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [130] ,IRQ130 (Base Timer ch.2) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [129] ,IRQ129 (Base Timer ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [128] ,IRQ128 (Base Timer ch.0/8/9/10/11) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC64++0x3
|
|
line.long 0x00 "IRQHS5,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 21. " [181] ,IRQ181 (FRT ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [180] ,IRQ180 (FRT ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " [179] ,IRQ179 (FRT ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [178] ,IRQ178 (FRT ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [177] ,IRQ177 (FRT ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [176] ,IRQ176 (FRT ch.0) hold status bit" "Not applied,Applied"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 9. " [169] ,IRQ169 (Reload Timer ch.33) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [168] ,IRQ168 (Reload Timer ch.32) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [163] ,IRQ163 (Reload Timer ch.19) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [162] ,IRQ162 (Reload Timer ch.18) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [161] ,IRQ161 (Reload Timer ch.17) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [160] ,IRQ160 (Reload Timer ch.16) hold status bit" "Not applied,Applied"
|
|
endif
|
|
rgroup.long 0xC68++0x3
|
|
line.long 0x00 "IRQHS6,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 21. " [213] ,IRQ213 (OCU ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [212] ,IRQ212 (OCU ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " [211] ,IRQ211 (OCU ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [210] ,IRQ210 (OCU ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [209] ,IRQ209 (OCU ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [208] ,IRQ208 (OCU ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [197] ,IRQ197 (ICU ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [196] ,IRQ196 (ICU ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [195] ,IRQ195 (ICU ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [194] ,IRQ194 (ICU ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [193] ,IRQ193 (ICU ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [192] ,IRQ192 (ICU ch.0) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC6C++0x3
|
|
line.long 0x00 "IRQHS7,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 21. " [245] ,IRQ245 (ICU ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [244] ,IRQ244 (ICU ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " [243] ,IRQ243 (ICU ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [242] ,IRQ242 (ICU ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [241] ,IRQ241 (ICU ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [240] ,IRQ240 (ICU ch.1) hold status bit" "Not applied,Applied"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 9. " [233] ,IRQ233 (QPRC ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [232] ,IRQ232 (QPRC ch.8) hold status bit" "Not applied,Applied"
|
|
endif
|
|
rgroup.long 0xC70++0x3
|
|
line.long 0x00 "IRQHS8,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 31. " [287] ,IRQ287 (DMA Completion Interrupt Request ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " [286] ,IRQ286 (DMA Completion Interrupt Request ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " [285] ,IRQ285 (DMA Completion Interrupt Request ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " [282] ,IRQ282 (DMAC RLT ch.0/1/2/3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [280] ,IRQ280 (DMA Completion Interrupt Request ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [279] ,IRQ279 (DMA Completion Interrupt Request ch.6) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [278] ,IRQ278 (DMA Completion Interrupt Request ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [277] ,IRQ277 (DMA Completion Interrupt Request ch.4) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [276] ,IRQ276 (DMA Completion Interrupt Request ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 19. " [275] ,IRQ275 (DMA Completion Interrupt Request ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [274] ,IRQ274 (DMA Completion Interrupt Request ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [273] ,IRQ273 (DMA Completion Interrupt Request ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [272] ,IRQ272 (DMA Error Interrupt Request) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [261] ,IRQ261 (OCU ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [260] ,IRQ260 (OCU ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [259] ,IRQ259 (OCU ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [258] ,IRQ258 (OCU ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [257] ,IRQ257 (OCU ch.3) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [256] ,IRQ256 (OCU ch.1) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC74++0x3
|
|
line.long 0x00 "IRQHS9,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 25. " [313] ,IRQ313 (BPC IRQs) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [312] ,IRQ312 (CR5 Performance Monitor Unit IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " [310] ,IRQ310 (SCT Main OSC IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [309] ,IRQ309 (SCT SRC IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [308] ,IRQ308 (SCT RC IRQ) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [292] ,IRQ292 (DMA Completion Interrupt Request ch.15) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [291] ,IRQ291 (DMA Completion Interrupt Request ch.14) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [290] ,IRQ290 (DMA Completion Interrupt Request ch.13) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [289] ,IRQ289 (DMA Completion Interrupt Request ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [288] ,IRQ288 (DMA Completion Interrupt Request ch.11) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC78++0x3
|
|
line.long 0x00 "IRQHS10,IRC IRQ Hold Status Register"
|
|
sif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 31. " [351] ,IRQ351 (M.F.S RX ch.14) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " [350] ,IRQ350 (M.F.S TX ch.13) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " [349] ,IRQ349 (M.F.S RX ch.13) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 28. " [348] ,IRQ348 (M.F.S TX ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 27. " [347] ,IRQ347 (M.F.S RX ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " [346] ,IRQ346 (M.F.S TX ch.11) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [345] ,IRQ345 (M.F.S RX ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [344] ,IRQ344 (M.F.S TX ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [343] ,IRQ343 (M.F.S RX ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " [342] ,IRQ342 (M.F.S TX ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [341] ,IRQ341 (M.F.S RX ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [340] ,IRQ340 (M.F.S TX ch.8) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [339] ,IRQ339 (M.F.S RX ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 7. " [327] ,IRQ327 (M.F.S Error ch.7) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [326] ,IRQ326 (M.F.S Error ch.6) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [325] ,IRQ325 (M.F.S Error ch.5) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [324] ,IRQ324 (M.F.S Error ch.4) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
elif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 25. " [332] ,IRQ332 (M.F.S Error ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [331] ,IRQ331 (M.F.S Error ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [330] ,IRQ330 (M.F.S Error ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " [329] ,IRQ329 (M.F.S Error ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [328] ,IRQ328 (M.F.S Error ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [324] ,IRQ324 (M.F.S Error ch.4) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " [323] ,IRQ323 (M.F.S Error ch.3) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [322] ,IRQ322 (M.F.S Error ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [321] ,IRQ321 (M.F.S Error ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [320] ,IRQ320 (M.F.S Error ch.0) hold status bit" "Not applied,Applied"
|
|
rgroup.long 0xC7C++0x3
|
|
line.long 0x00 "IRQHS11,IRC IRQ Hold Status Register"
|
|
bitfld.long 0x00 31. " [383] ,IRQ383 (Base Timer ch.14) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 30. " [382] ,IRQ382 (Base Timer ch.13) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 29. " [381] ,IRQ381 (Base Timer ch.12/20/21/22/23) hold status bit" "Not applied,Applied"
|
|
sif (cpuis("S6J311?JAA"))
|
|
textline " "
|
|
bitfld.long 0x00 28. " [380] ,IRQ380 (M.F.S Error ch.21) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 27. " [379] ,IRQ379 (M.F.S Error ch.20) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 26. " [378] ,IRQ378 (M.F.S Error ch.19) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [377] ,IRQ377 (M.F.S Error ch.18) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 24. " [376] ,IRQ376 (M.F.S Error ch.17) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 23. " [375] ,IRQ375 (M.F.S Error ch.16) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 22. " [374] ,IRQ374 (M.F.S Error ch.15) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [373] ,IRQ373 (M.F.S Error ch.14) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [372] ,IRQ372 (M.F.S Error ch.13) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [371] ,IRQ371 (M.F.S Error ch.12) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 18. " [370] ,IRQ370 (M.F.S Error ch.11) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 17. " [369] ,IRQ369 (M.F.S Error ch.10) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 16. " [368] ,IRQ368 (M.F.S Error ch.9) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 15. " [367] ,IRQ367 (M.F.S Error ch.8) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 14. " [366] ,IRQ366 (M.F.S TX ch.21) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [365] ,IRQ365 (M.F.S RX ch.21) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 12. " [364] ,IRQ364 (M.F.S TX ch.20) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " [363] ,IRQ363 (M.F.S RX ch.20) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 10. " [362] ,IRQ362 (M.F.S TX ch.19) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 9. " [361] ,IRQ361 (M.F.S RX ch.19) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [360] ,IRQ360 (M.F.S TX ch.18) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [359] ,IRQ359 (M.F.S RX ch.18) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [358] ,IRQ358 (M.F.S TX ch.17) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [357] ,IRQ357 (M.F.S RX ch.17) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 4. " [356] ,IRQ356 (M.F.S TX ch.16) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [355] ,IRQ355 (M.F.S RX ch.16) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [354] ,IRQ354 (M.F.S TX ch.15) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [353] ,IRQ353 (M.F.S RX ch.15) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [352] ,IRQ352 (M.F.S TX ch.14) hold status bit" "Not applied,Applied"
|
|
endif
|
|
rgroup.long 0xC80++0x3
|
|
line.long 0x00 "IRQHS12,IRC IRQ Hold Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 22. " [406] ,IRQ406 (Sound Generator ch.2) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 21. " [405] ,IRQ405 (Sound Generator ch.1) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 20. " [404] ,IRQ404 (Sound Generator ch.0) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " [400] ,IRQ400 (A/D unit.1 Range Compare) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 15. " [399] ,IRQ399 (A/D unit.1 A/D Conversion End) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 14. " [398] ,IRQ398 (A/D unit.1 Scan Conversion End) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 13. " [397] ,IRQ397 (A/D unit.0 Range Compare) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 12. " [396] ,IRQ396 (A/D unit.0 A/D Conversion End) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 11. " [395] ,IRQ395 (A/D unit.0 Scan Conversion End) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [394] ,IRQ394 (Base Timer ch.29) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 9. " [393] ,IRQ393 (Base Timer ch.28) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 8. " [392] ,IRQ392 (Base Timer ch.27) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 7. " [391] ,IRQ391 (Base Timer ch.26) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 6. " [390] ,IRQ390 (Base Timer ch.25) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 5. " [389] ,IRQ389 (Base Timer ch.24) hold status bit" "Not applied,Applied"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [388] ,IRQ388 (Base Timer ch.19) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 3. " [387] ,IRQ387 (Base Timer ch.18) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 2. " [386] ,IRQ386 (Base Timer ch.17) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 1. " [385] ,IRQ385 (Base Timer ch.16) hold status bit" "Not applied,Applied"
|
|
bitfld.long 0x00 0. " [384] ,IRQ384 (Base Timer ch.15) hold status bit" "Not applied,Applied"
|
|
tree.end
|
|
textline ""
|
|
width 9.
|
|
group.long 0xC90++0x3
|
|
line.long 0x00 "IRQPLM,IRC IRQ Priority Level Mask Register"
|
|
bitfld.long 0x00 0.--5. " IRQPLM ,IRQ priority level mask bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC98++0x3
|
|
line.long 0x00 "CSR,IRC Control/Status Register"
|
|
rbitfld.long 0x00 16. " LST ,Interrupt controler lock status" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " IRQEN ,IRQ processing block enable/disable setting bit" "Disabled,Enabled"
|
|
textline ""
|
|
rgroup.long 0xCA8++0x3
|
|
line.long 0x00 "NMIRS,IRC NMI RAW Status Register"
|
|
bitfld.long 0x00 18. " NMIRS_[18] ,RAW status bit for NMI18 (TPU(s) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [15] ,RAW status bit for NMI15 (SHE MPU)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,RAW status bit for NMI13 (DMAC MPU #0 protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,RAW status bit for NMI12 (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [11] ,RAW status bit for NMI11 (Backup RAM 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,RAW status bit for NMI8 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,RAW status bit for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,RAW status bit for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,RAW status bit for NMI5 (CSV/Profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,RAW status bit for NMI4 (LVDs IRQ)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,RAW status bit for NMI0 (NMIX pin (Ext-IRC))" "No interrupt,Interrupt"
|
|
rgroup.long 0xCAC++0x3
|
|
line.long 0x00 "NMIPS,IRC NMI Preprocessed Status Register"
|
|
bitfld.long 0x00 18. " NMIPS_[18] ,Preprocessed status bits for NMI18 (TPU(s) protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [15] ,Preprocessed status bits for NMI15 (SHE MPU)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Preprocessed status bits for NMI13 (DMAC MPU #0 protection violation)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Preprocessed status bits for NMI12 (CAN-FD RAMs 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [11] ,Preprocessed status bits for NMI11 (Backup RAM 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Preprocessed status bits for NMI8 (IRC 2-bit ECC error detection)" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Preprocessed status bits for NMI7 (SW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Preprocessed status bits for NMI6 (HW-WDT)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Preprocessed status bits for NMI5 (CSV/Profile)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Preprocessed status bits for NMI4 (LVDs IRQ)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Preprocessed status bits for NMI0 (NMIX pin (Ext-IRC))" "No interrupt,Interrupt"
|
|
tree "IRQRS 0--511"
|
|
rgroup.long 0xCB0++0x3
|
|
line.long 0x00 "IRQRS0,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 31. " IRQRS_[31] ,IRQ31 (External Interrupt Request ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,IRQ30 (External Interrupt Request ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,IRQ29 (External Interrupt Request ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,IRQ28 (External Interrupt Request ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [27] ,IRQ27 (External Interrupt Request ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,IRQ26 (External Interrupt Request ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,IRQ25 (External Interrupt Request ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,IRQ24 (External Interrupt Request ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [23] ,IRQ23 (EICU) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,IRQ20 (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [19] ,IRQ19 (Debugger Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,IRQ16 (IRC0 Vector Address RAM Single Bit Error Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,IRQ15 (Backup RAM / CAN FD RAMs Single Bit Error Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,IRQ14 (Scratch Pad RAM Single Bit Error Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,IRQ10 (Work FLASH HANG Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,IRQ8 (TCFLASH Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [3] ,IRQ3 (SW-WDT Pre-warning Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,IRQ2 (HW-WDT Pre-warning Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,IRQ1 (System Control Status Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCB4++0x3
|
|
line.long 0x00 "IRQRS1,IRC IRQ RAW Status Resister"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 26. " [58] ,IRQ58 (CAN-FD ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [39] ,IRQ39 (External Interrupt Request ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [38] ,IRQ38 (External Interrupt Request ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [37] ,IRQ37 (External Interrupt Request ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [36] ,IRQ36 (External Interrupt Request ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [35] ,IRQ35 (External Interrupt Request ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [34] ,IRQ34 (External Interrupt Request ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [33] ,IRQ33 (External Interrupt Request ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [32] ,IRQ32 (External Interrupt Request ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCB8++0x3
|
|
line.long 0x00 "IRQRS2,IRC IRQ RAW Status Resister"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 25. " [89] ,IRQ89 (M.F.S TX ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [88] ,IRQ88 (M.F.S Rx ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [87] ,IRQ87 (M.F.S TX ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [86] ,IRQ86 (M.F.S Rx ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [85] ,IRQ85 (M.F.S TX ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [84] ,IRQ84 (M.F.S Rx ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [83] ,IRQ83 (M.F.S TX ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [82] ,IRQ82 (M.F.S Rx ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [81] ,IRQ81 (M.F.S TX ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [80] ,IRQ80 (M.F.S Rx ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 15. " [79] ,IRQ79 (M.F.S TX ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [78] ,IRQ78 (M.F.S Rx ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [77] ,IRQ77 (M.F.S TX ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [76] ,IRQ76 (M.F.S Rx ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [75] ,IRQ75 (M.F.S TX ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [74] ,IRQ74 (M.F.S Rx ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [71] ,IRQ71 (M.F.S TX ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [70] ,IRQ70 (M.F.S Rx ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [69] ,IRQ69 (M.F.S TX ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [68] ,IRQ68 (M.F.S Rx ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [67] ,IRQ67 (M.F.S TX ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [66] ,IRQ66 (M.F.S Rx ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [65] ,IRQ65 (M.F.S TX ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [64] ,IRQ64 (M.F.S RX ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCBC++0x3
|
|
line.long 0x00 "IRQRS3,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 21. " [117] ,IRQ117 (CR calibration IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [116] ,IRQ116 (RTC+Calibration IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [112] ,IRQ112 (Backup RAM diag) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [110] ,IRQ110 (TCRAM diag) RAW status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 5. " [103] ,IRQ103 (DDR_HSSPI ch.0 TX) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [102] ,IRQ102 (DDR_HSSPI ch.0 RX) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xCC0++0x3
|
|
line.long 0x00 "IRQRS4,IRC IRQ RAW Status Resister"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 27. " [155] ,IRQ155 (Reload Timer ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [154] ,IRQ154 (Reload Timer ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [153] ,IRQ153 (Reload Timer ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [152] ,IRQ152 (Reload Timer ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [135] ,IRQ135 (Base Timer ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [134] ,IRQ134 (Base Timer ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [133] ,IRQ133 (Base Timer ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [132] ,IRQ132 (Base Timer ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [131] ,IRQ131 (Base Timer ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [130] ,IRQ130 (Base Timer ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [129] ,IRQ129 (Base Timer ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [128] ,IRQ128 (Base Timer ch.0/8/9/10/11) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCC4++0x3
|
|
line.long 0x00 "IRQRS5,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 21. " [181] ,IRQ181 (FRT ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [180] ,IRQ180 (FRT ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [179] ,IRQ179 (FRT ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [178] ,IRQ178 (FRT ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [177] ,IRQ177 (FRT ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [176] ,IRQ176 (FRT ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 9. " [169] ,IRQ169 (Reload Timer ch.33) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [168] ,IRQ168 (Reload Timer ch.32) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [163] ,IRQ163 (Reload Timer ch.19) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [162] ,IRQ162 (Reload Timer ch.18) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [161] ,IRQ161 (Reload Timer ch.17) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [160] ,IRQ160 (Reload Timer ch.16) RAW status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xCC8++0x3
|
|
line.long 0x00 "IRQRS6,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 21. " [213] ,IRQ213 (OCU ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [212] ,IRQ212 (OCU ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [211] ,IRQ211 (OCU ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [210] ,IRQ210 (OCU ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [209] ,IRQ209 (OCU ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [208] ,IRQ208 (OCU ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [197] ,IRQ197 (ICU ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [196] ,IRQ196 (ICU ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [195] ,IRQ195 (ICU ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [194] ,IRQ194 (ICU ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [193] ,IRQ193 (ICU ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [192] ,IRQ192 (ICU ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCCC++0x3
|
|
line.long 0x00 "IRQRS7,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 21. " [245] ,IRQ245 (ICU ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [244] ,IRQ244 (ICU ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [243] ,IRQ243 (ICU ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [242] ,IRQ242 (ICU ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [241] ,IRQ241 (ICU ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [240] ,IRQ240 (ICU ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 19. " [233] ,IRQ233 (QPRC ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [232] ,IRQ232 (QPRC ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xCD0++0x3
|
|
line.long 0x00 "IRQRS8,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 31. " [287] ,IRQ287 (DMA Completion Interrupt Request ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [286] ,IRQ286 (DMA Completion Interrupt Request ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [285] ,IRQ285 (DMA Completion Interrupt Request ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [282] ,IRQ282 (DMAC RLT ch.0/1/2/3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [280] ,IRQ280 (DMA Completion Interrupt Request ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [279] ,IRQ279 (DMA Completion Interrupt Request ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [278] ,IRQ278 (DMA Completion Interrupt Request ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [277] ,IRQ277 (DMA Completion Interrupt Request ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [276] ,IRQ276 (DMA Completion Interrupt Request ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [275] ,IRQ275 (DMA Completion Interrupt Request ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [274] ,IRQ274 (DMA Completion Interrupt Request ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [273] ,IRQ273 (DMA Completion Interrupt Request ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [272] ,IRQ272 (DMA Error Interrupt Request) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [261] ,IRQ261 (OCU ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [260] ,IRQ260 (OCU ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [259] ,IRQ259 (OCU ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [258] ,IRQ258 (OCU ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [257] ,IRQ257 (OCU ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [256] ,IRQ256 (OCU ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCD4++0x3
|
|
line.long 0x00 "IRQRS9,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 25. " [313] ,IRQ313 (BPC IRQs) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [312] ,IRQ312 (CR5 Performance Monitor Unit IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [310] ,IRQ310 (SCT Main OSC IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [309] ,IRQ309 (SCT SRC IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [308] ,IRQ308 (SCT RC IRQ) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [292] ,IRQ292 (DMA Completion Interrupt Request ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [291] ,IRQ291 (DMA Completion Interrupt Request ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [290] ,IRQ290 (DMA Completion Interrupt Request ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [289] ,IRQ289 (DMA Completion Interrupt Request ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [288] ,IRQ288 (DMA Completion Interrupt Request ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCD8++0x3
|
|
line.long 0x00 "IRQRS10,IRC IRQ RAW Status Resister"
|
|
sif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 31. " [351] ,IRQ351 (M.F.S RX ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [350] ,IRQ350 (M.F.S TX ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [349] ,IRQ349 (M.F.S RX ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [348] ,IRQ348 (M.F.S TX ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [347] ,IRQ347 (M.F.S RX ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [346] ,IRQ346 (M.F.S TX ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [345] ,IRQ345 (M.F.S RX ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [344] ,IRQ344 (M.F.S TX ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [343] ,IRQ343 (M.F.S RX ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [342] ,IRQ342 (M.F.S TX ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [341] ,IRQ341 (M.F.S RX ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [340] ,IRQ340 (M.F.S TX ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [339] ,IRQ339 (M.F.S RX ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " [327] ,IRQ327 (M.F.S Error ch.7) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [326] ,IRQ326 (M.F.S Error ch.6) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [325] ,IRQ325 (M.F.S Error ch.5) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [324] ,IRQ324 (M.F.S Error ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 12. " [332] ,IRQ332 (M.F.S RX ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [331] ,IRQ331 (M.F.S Error ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [330] ,IRQ330 (M.F.S Error ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [329] ,IRQ329 (M.F.S Error ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [328] ,IRQ328 (M.F.S Error ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [324] ,IRQ324 (M.F.S Error ch.4) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " [323] ,IRQ323 (M.F.S Error ch.3) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [322] ,IRQ322 (M.F.S Error ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [321] ,IRQ321 (M.F.S Error ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [320] ,IRQ320 (M.F.S Error ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCDC++0x3
|
|
line.long 0x00 "IRQRS11,IRC IRQ RAW Status Resister"
|
|
bitfld.long 0x00 31. " [383] ,IRQ383 (Base Timer ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [382] ,IRQ382 (Base Timer ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [381] ,IRQ381 (Base Timer ch.12/20/21/22/23) RAW status bit" "No interrupt,Interrupt"
|
|
sif (cpuis("S6J311?JAA"))
|
|
textline " "
|
|
bitfld.long 0x00 28. " [380] ,IRQ380 (M.F.S Error ch.21) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [379] ,IRQ379 (M.F.S Error ch.20) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [378] ,IRQ378 (M.F.S Error ch.19) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [377] ,IRQ377 (M.F.S Error ch.18) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [376] ,IRQ376 (M.F.S Error ch.17) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [375] ,IRQ375 (M.F.S Error ch.16) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [374] ,IRQ374 (M.F.S Error ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [373] ,IRQ373 (M.F.S Error ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [372] ,IRQ372 (M.F.S Error ch.13) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [371] ,IRQ371 (M.F.S Error ch.12) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [370] ,IRQ370 (M.F.S Error ch.11) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [369] ,IRQ369 (M.F.S Error ch.10) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [368] ,IRQ368 (M.F.S Error ch.9) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [367] ,IRQ367 (M.F.S Error ch.8) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [366] ,IRQ366 (M.F.S TX ch.21) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [365] ,IRQ365 (M.F.S RX ch.21) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [364] ,IRQ364 (M.F.S TX ch.20) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [363] ,IRQ363 (M.F.S RX ch.20) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [362] ,IRQ362 (M.F.S TX ch.19) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [361] ,IRQ361 (M.F.S RX ch.19) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [360] ,IRQ360 (M.F.S TX ch.18) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [359] ,IRQ359 (M.F.S RX ch.18) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [358] ,IRQ358 (M.F.S TX ch.17) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [357] ,IRQ357 (M.F.S RX ch.17) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [356] ,IRQ356 (M.F.S TX ch.16) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [355] ,IRQ355 (M.F.S RX ch.16) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [354] ,IRQ354 (M.F.S TX ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [353] ,IRQ353 (M.F.S RX ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [352] ,IRQ352 (M.F.S TX ch.14) RAW status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xCE0++0x3
|
|
line.long 0x00 "IRQRS12,IRC IRQ RAW Status Resister"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 22. " [406] ,IRQ406 (Sound Generator ch.2) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [405] ,IRQ405 (Sound Generator ch.1) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [404] ,IRQ404 (Sound Generator ch.0) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " [400] ,IRQ400 (A/D unit.1 Range Compare) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [399] ,IRQ399 (A/D unit.1 A/D Conversion End) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [398] ,IRQ398 (A/D unit.1 Scan Conversion End) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [397] ,IRQ397 (A/D unit.0 Range Compare) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [396] ,IRQ396 (A/D unit.0 A/D Conversion End) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [395] ,IRQ395 (A/D unit.0 Scan Conversion End) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [394] ,IRQ394 (Base Timer ch.29) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [393] ,IRQ393 (Base Timer ch.28) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [392] ,IRQ392 (Base Timer ch.27) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " [391] ,IRQ391 (Base Timer ch.26) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [390] ,IRQ390 (Base Timer ch.25) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [389] ,IRQ389 (Base Timer ch.24) RAW status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [388] ,IRQ388 (Base Timer ch.19) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [387] ,IRQ387 (Base Timer ch.18) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [386] ,IRQ386 (Base Timer ch.17) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [385] ,IRQ385 (Base Timer ch.16) RAW status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [384] ,IRQ384 (Base Timer ch.15) RAW status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree "IRQPS 0--511"
|
|
rgroup.long 0xCF0++0x3
|
|
line.long 0x00 "IRQPS0,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 31. " IRQPS_[31] ,IRQ31 (External Interrupt Request ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,IRQ30 (External Interrupt Request ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,IRQ29 (External Interrupt Request ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,IRQ28 (External Interrupt Request ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [27] ,IRQ27 (External Interrupt Request ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,IRQ26 (External Interrupt Request ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,IRQ25 (External Interrupt Request ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,IRQ24 (External Interrupt Request ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [23] ,IRQ23 (EICU) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,IRQ20 (Work FLASH RDY Interrupt Request/Single Bit Error Interrupt Request/WE Release Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [19] ,IRQ19 (Debugger Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,IRQ16 (IRC0 Vector Address RAM Single Bit Error Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,IRQ15 (Backup RAM / CAN FD RAMs Single Bit Error Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,IRQ14 (Scratch Pad RAM Single Bit Error Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,IRQ10 (Work FLASH HANG Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,IRQ8 (TCFLASH Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [3] ,IRQ3 (SW-WDT Pre-warning Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,IRQ2 (HW-WDT Pre-warning Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,IRQ1 (System Control Status Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCF4++0x3
|
|
line.long 0x00 "IRQPS1,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 26. " [58] ,IRQ58 (CAN-FD ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 25. " [57] ,IRQ57 (CAN-FD ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,IRQ56 (CAN-FD ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 25. " [56] ,IRQ57 (CAN-FD ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [39] ,IRQ39 (External Interrupt Request ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [38] ,IRQ38 (External Interrupt Request ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [37] ,IRQ37 (External Interrupt Request ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [36] ,IRQ36 (External Interrupt Request ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [35] ,IRQ35 (External Interrupt Request ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [34] ,IRQ34 (External Interrupt Request ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [33] ,IRQ33 (External Interrupt Request ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [32] ,IRQ32 (External Interrupt Request ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCF8++0x3
|
|
line.long 0x00 "IRQPS2,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 25. " [89] ,IRQ89 (M.F.S TX ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [88] ,IRQ88 (M.F.S Rx ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [87] ,IRQ87 (M.F.S TX ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [86] ,IRQ86 (M.F.S Rx ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [85] ,IRQ85 (M.F.S TX ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [84] ,IRQ84 (M.F.S Rx ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [83] ,IRQ83 (M.F.S TX ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [82] ,IRQ82 (M.F.S Rx ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [81] ,IRQ81 (M.F.S TX ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [80] ,IRQ80 (M.F.S Rx ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 15. " [79] ,IRQ79 (M.F.S TX ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [78] ,IRQ78 (M.F.S Rx ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [77] ,IRQ77 (M.F.S TX ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [76] ,IRQ76 (M.F.S Rx ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [75] ,IRQ75 (M.F.S TX ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [74] ,IRQ74 (M.F.S Rx ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [73] ,IRQ73 (M.F.S TX ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [72] ,IRQ72 (M.F.S Rx ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [71] ,IRQ71 (M.F.S TX ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [70] ,IRQ70 (M.F.S Rx ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [69] ,IRQ69 (M.F.S TX ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [68] ,IRQ68 (M.F.S Rx ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [67] ,IRQ67 (M.F.S TX ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [66] ,IRQ66 (M.F.S Rx ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [65] ,IRQ65 (M.F.S TX ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [64] ,IRQ64 (M.F.S RX ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xCFC++0x3
|
|
line.long 0x00 "IRQPS3,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 21. " [117] ,IRQ117 (CR calibration IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [116] ,IRQ116 (RTC+Calibration IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [112] ,IRQ112 (Backup RAM diag) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [110] ,IRQ110 (TCRAM diag) preprocessed status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 5. " [103] ,IRQ103 (DDR_HSSPI ch.0 TX) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [102] ,IRQ102 (DDR_HSSPI ch.0 RX) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 5. " [101] ,IRQ101 (SHE IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [100] ,IRQ100 (SHE Err IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xD00++0x3
|
|
line.long 0x00 "IRQPS4,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 27. " [155] ,IRQ155 (Reload Timer ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [154] ,IRQ154 (Reload Timer ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [153] ,IRQ153 (Reload Timer ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [152] ,IRQ152 (Reload Timer ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " [135] ,IRQ135 (Base Timer ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [134] ,IRQ134 (Base Timer ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [133] ,IRQ133 (Base Timer ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [132] ,IRQ132 (Base Timer ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [131] ,IRQ131 (Base Timer ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [130] ,IRQ130 (Base Timer ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [129] ,IRQ129 (Base Timer ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [128] ,IRQ128 (Base Timer ch.0/8/9/10/11) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xD04++0x3
|
|
line.long 0x00 "IRQPS5,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 21. " [181] ,IRQ181 (FRT ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [180] ,IRQ180 (FRT ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [179] ,IRQ179 (FRT ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [178] ,IRQ178 (FRT ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [177] ,IRQ177 (FRT ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [176] ,IRQ176 (FRT ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 9. " [169] ,IRQ169 (Reload Timer ch.33) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [168] ,IRQ168 (Reload Timer ch.32) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [163] ,IRQ163 (Reload Timer ch.19) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [162] ,IRQ162 (Reload Timer ch.18) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [161] ,IRQ161 (Reload Timer ch.17) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [160] ,IRQ160 (Reload Timer ch.16) preprocessed status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xD08++0x3
|
|
line.long 0x00 "IRQPS6,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 21. " [213] ,IRQ213 (OCU ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [212] ,IRQ212 (OCU ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [211] ,IRQ211 (OCU ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [210] ,IRQ210 (OCU ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [209] ,IRQ209 (OCU ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [208] ,IRQ208 (OCU ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [197] ,IRQ197 (ICU ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [196] ,IRQ196 (ICU ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [195] ,IRQ195 (ICU ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [194] ,IRQ194 (ICU ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [193] ,IRQ193 (ICU ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [192] ,IRQ192 (ICU ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xD0C++0x3
|
|
line.long 0x00 "IRQPS7,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 21. " [245] ,IRQ245 (ICU ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [244] ,IRQ244 (ICU ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [243] ,IRQ243 (ICU ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [242] ,IRQ242 (ICU ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [241] ,IRQ241 (ICU ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [240] ,IRQ240 (ICU ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
sif cpuis("S6J312?HAA")
|
|
textline " "
|
|
bitfld.long 0x00 19. " [233] ,IRQ233 (QPRC ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [232] ,IRQ232 (QPRC ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xD10++0x3
|
|
line.long 0x00 "IRQPS8,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 31. " [287] ,IRQ287 (DMA Completion Interrupt Request ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [286] ,IRQ286 (DMA Completion Interrupt Request ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [285] ,IRQ285 (DMA Completion Interrupt Request ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [282] ,IRQ282 (DMAC RLT ch.0/1/2/3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [280] ,IRQ280 (DMA Completion Interrupt Request ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [279] ,IRQ279 (DMA Completion Interrupt Request ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [278] ,IRQ278 (DMA Completion Interrupt Request ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [277] ,IRQ277 (DMA Completion Interrupt Request ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [276] ,IRQ276 (DMA Completion Interrupt Request ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " [275] ,IRQ275 (DMA Completion Interrupt Request ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [274] ,IRQ274 (DMA Completion Interrupt Request ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [273] ,IRQ273 (DMA Completion Interrupt Request ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [272] ,IRQ272 (DMA Error Interrupt Request) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [261] ,IRQ261 (OCU ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [260] ,IRQ260 (OCU ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [259] ,IRQ259 (OCU ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [258] ,IRQ258 (OCU ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [257] ,IRQ257 (OCU ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [256] ,IRQ256 (OCU ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xD14++0x3
|
|
line.long 0x00 "IRQPS9,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 25. " [313] ,IRQ313 (BPC IRQs) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [312] ,IRQ312 (CR5 Performance Monitor Unit IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [310] ,IRQ310 (SCT Main OSC IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [309] ,IRQ309 (SCT SRC IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [308] ,IRQ308 (SCT RC IRQ) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [292] ,IRQ292 (DMA Completion Interrupt Request ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [291] ,IRQ291 (DMA Completion Interrupt Request ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [290] ,IRQ290 (DMA Completion Interrupt Request ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [289] ,IRQ289 (DMA Completion Interrupt Request ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [288] ,IRQ288 (DMA Completion Interrupt Request ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xD18++0x3
|
|
line.long 0x00 "IRQPS10,IRC IRQ Preprocessed Status Register"
|
|
sif (cpuis("S6J311?JAA"))
|
|
bitfld.long 0x00 31. " [351] ,IRQ351 (M.F.S RX ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [350] ,IRQ350 (M.F.S TX ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [349] ,IRQ349 (M.F.S RX ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [348] ,IRQ348 (M.F.S TX ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [347] ,IRQ347 (M.F.S RX ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [346] ,IRQ346 (M.F.S TX ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [345] ,IRQ345 (M.F.S RX ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [344] ,IRQ344 (M.F.S TX ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [343] ,IRQ343 (M.F.S RX ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [342] ,IRQ342 (M.F.S TX ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [341] ,IRQ341 (M.F.S RX ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [340] ,IRQ340 (M.F.S TX ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [339] ,IRQ339 (M.F.S RX ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " [327] ,IRQ327 (M.F.S Error ch.7) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [326] ,IRQ326 (M.F.S Error ch.6) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [325] ,IRQ325 (M.F.S Error ch.5) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [324] ,IRQ324 (M.F.S Error ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
elif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " [332] ,IRQ332 (M.F.S RX ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [331] ,IRQ331 (M.F.S Error ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [330] ,IRQ330 (M.F.S Error ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [329] ,IRQ329 (M.F.S Error ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [328] ,IRQ328 (M.F.S Error ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [324] ,IRQ324 (M.F.S Error ch.4) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " [323] ,IRQ323 (M.F.S Error ch.3) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [322] ,IRQ322 (M.F.S Error ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [321] ,IRQ321 (M.F.S Error ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [320] ,IRQ320 (M.F.S Error ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
rgroup.long 0xD1C++0x3
|
|
line.long 0x00 "IRQPS11,IRC IRQ Preprocessed Status Register"
|
|
bitfld.long 0x00 31. " [383] ,IRQ383 (Base Timer ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [382] ,IRQ382 (Base Timer ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [381] ,IRQ381 (Base Timer ch.12/20/21/22/23) preprocessed status bit" "No interrupt,Interrupt"
|
|
sif (cpuis("S6J311?JAA"))
|
|
textline " "
|
|
bitfld.long 0x00 28. " [380] ,IRQ380 (M.F.S Error ch.21) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " [379] ,IRQ379 (M.F.S Error ch.20) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [378] ,IRQ378 (M.F.S Error ch.19) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [377] ,IRQ377 (M.F.S Error ch.18) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [376] ,IRQ376 (M.F.S Error ch.17) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " [375] ,IRQ375 (M.F.S Error ch.16) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [374] ,IRQ374 (M.F.S Error ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [373] ,IRQ373 (M.F.S Error ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [372] ,IRQ372 (M.F.S Error ch.13) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [371] ,IRQ371 (M.F.S Error ch.12) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [370] ,IRQ370 (M.F.S Error ch.11) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [369] ,IRQ369 (M.F.S Error ch.10) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [368] ,IRQ368 (M.F.S Error ch.9) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [367] ,IRQ367 (M.F.S Error ch.8) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [366] ,IRQ366 (M.F.S TX ch.21) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [365] ,IRQ365 (M.F.S RX ch.21) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [364] ,IRQ364 (M.F.S TX ch.20) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [363] ,IRQ363 (M.F.S RX ch.20) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [362] ,IRQ362 (M.F.S TX ch.19) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [361] ,IRQ361 (M.F.S RX ch.19) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [360] ,IRQ360 (M.F.S TX ch.18) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [359] ,IRQ359 (M.F.S RX ch.18) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [358] ,IRQ358 (M.F.S TX ch.17) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [357] ,IRQ357 (M.F.S RX ch.17) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [356] ,IRQ356 (M.F.S TX ch.16) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [355] ,IRQ355 (M.F.S RX ch.16) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [354] ,IRQ354 (M.F.S TX ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [353] ,IRQ353 (M.F.S RX ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [352] ,IRQ352 (M.F.S TX ch.14) preprocessed status bit" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0xD20++0x3
|
|
line.long 0x00 "IRQPS12,IRC IRQ Preprocessed Status Register"
|
|
sif cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 16. " [406] ,IRQ406 (Sound Generator ch.2) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [405] ,IRQ405 (Sound Generator ch.1) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [404] ,IRQ404 (Sound Generator ch.0) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " [400] ,IRQ400 (A/D unit.1 Range Compare) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " [399] ,IRQ399 (A/D unit.1 A/D Conversion End) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [398] ,IRQ398 (A/D unit.1 Scan Conversion End) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [397] ,IRQ397 (A/D unit.0 Range Compare) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [396] ,IRQ396 (A/D unit.0 A/D Conversion End) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " [395] ,IRQ395 (A/D unit.0 Scan Conversion End) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [394] ,IRQ394 (Base Timer ch.29) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [393] ,IRQ393 (Base Timer ch.28) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [392] ,IRQ392 (Base Timer ch.27) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " [391] ,IRQ391 (Base Timer ch.26) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [390] ,IRQ390 (Base Timer ch.25) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [389] ,IRQ389 (Base Timer ch.24) preprocessed status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " [388] ,IRQ388 (Base Timer ch.19) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " [387] ,IRQ387 (Base Timer ch.18) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [386] ,IRQ386 (Base Timer ch.17) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [385] ,IRQ385 (Base Timer ch.16) preprocessed status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [384] ,IRQ384 (Base Timer ch.15) preprocessed status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline ""
|
|
group.long 0xD30++0x3
|
|
line.long 0x00 "UNLOCK,IRC Unlock Register"
|
|
group.long 0xD3C++0x3
|
|
line.long 0x00 "IRQEEVA,IRC ECC Error Vector Address Register"
|
|
group.long 0xD40++0x3
|
|
line.long 0x00 "EEI,IRC ECC Error Interrupt Register"
|
|
rbitfld.long 0x00 24. " EEIS ,ECC error IRQ status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " EEIC ,ECC error IRQ clear bit" "No effect,Cleared"
|
|
rbitfld.long 0x00 8. " EENS ,ECC error NMI status bit" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " EENC ,ECC error NMI clear bit" "No effect,Cleared"
|
|
rgroup.long 0xD44++0x3
|
|
line.long 0x00 "EAN,IRC ECC Address Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EAN ,ECC error occurrence address bits"
|
|
group.long 0xD48++0x3
|
|
line.long 0x00 "ET,IRC ECC Test Register"
|
|
bitfld.long 0x00 0. " ET ,ECC test enable/disable setting bit" "Disabled,Enabled"
|
|
group.long 0xD4C++0x3
|
|
line.long 0x00 "EEB0,IRC ECC Bit Register"
|
|
hexmask.long 0x00 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
group.long 0xD50++0x3
|
|
line.long 0x00 "EEB1,IRC ECC Bit Register"
|
|
hexmask.long 0x00 2.--31. 1. " EEB ,ECC error occurrence bits"
|
|
group.long 0xD54++0x3
|
|
line.long 0x00 "EEB2,IRC ECC Bit Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " EEBO ,ECC error occurrence bits"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EEBE ,ECC error occurrence bits"
|
|
width 15.
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
base ad:0xFFFEE3FC
|
|
rgroup.long 0x00++0x03 "Register Memory Layout of Interrupt Controler (HSEL2)"
|
|
line.long 0x00 "IRC_NMIVASBR,IRC NMI Vector Address Status Register"
|
|
rgroup.long 0x1800++0x03 "Register Memory Layout of Interrupt Controler (HSEL3)"
|
|
line.long 0x00 "IRC0_NMIVASBR,IRC NMI Vector Address Status Mirror Register"
|
|
else
|
|
rgroup.long 0x3F8++0x03 "Register Memory Layout of Interrupt Controler (HSEL2)"
|
|
line.long 0x00 "IRC_NMIVASBR,IRC NMI Vector Address Status Register"
|
|
rgroup.long 0x3FC++0x03 "Register Memory Layout of Interrupt Controler (HSEL3)"
|
|
line.long 0x00 "IRC0_NMIVASBR,IRC NMI Vector Address Status Mirror Register"
|
|
endif
|
|
tree.end
|
|
tree "TPU (TIME PROTECTION)"
|
|
base ad:0xB0408000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TPU0_UNLOCK,TPU Lock Release Register"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TPU0_LST,TPU Lock Status Register"
|
|
bitfld.long 0x00 0. " LST ,Lock status of the time" "Unlocked,Locked"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TPU0_CFG,TPU Configuration Register"
|
|
bitfld.long 0x00 24. " DBGE ,Debug mode enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " GLBPSE ,Global prescaler enable/disable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--21. " GLBPS ,Global prescaler division setting bit" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
bitfld.long 0x00 0. " INTE ,Time protection unit interrupt enable setting bit" "Disabled,Enabled"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "TPU0_TIR,TPU Timer Interrupt Request Register"
|
|
bitfld.long 0x00 7. " IR[7] ,Timer 7 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " IR[6] ,Timer 6 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " IR[5] ,Timer 5 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IR[4] ,Timer 4 interrupt request bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " IR[3] ,Timer 3 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IR[2] ,Timer 2 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IR[1] ,Timer 1 interrupt request bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IR[0] ,Timer 0 interrupt request bit" "No interrupt,Interrupt"
|
|
line.long 0x04 "TPU0_TST,TPU Timer Status Register"
|
|
bitfld.long 0x04 7. " ST[7] ,Timer 7 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 6. " ST[6] ,Timer 6 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 5. " ST[5] ,Timer 5 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 4. " ST[4] ,Timer 4 status bit" "Stopped,Running"
|
|
newline
|
|
bitfld.long 0x04 3. " ST[3] ,Timer 3 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 2. " ST[2] ,Timer 2 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 1. " ST[1] ,Timer 1 status bit" "Stopped,Running"
|
|
bitfld.long 0x04 0. " ST[0] ,Timer 0 status bit" "Stopped,Running"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TPU0_TIE,TPU Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 7. " IE[7] ,Timer 7 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IE[6] ,Timer 6 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IE[5] ,Timer 5 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IE[4] ,Timer 4 interrupt enable setting bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " IE[3] ,Timer 3 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IE[2] ,Timer 2 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE[1] ,Timer 1 interrupt enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IE[0] ,Timer 0 interrupt enable setting bit" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TPU0_TCN00,TPU Timer 0 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TPU0_TCN01,TPU Timer 1 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TPU0_TCN02,TPU Timer 2 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TPU0_TCN03,TPU Timer 3 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TPU0_TCN04,TPU Timer 4 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TPU0_TCN05,TPU Timer 5 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TPU0_TCN06,TPU Timer 6 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TPU0_TCN07,TPU Timer 7 Control Register 0"
|
|
bitfld.long 0x00 31. " START ,Timer operation start bit" "No effect,Start"
|
|
bitfld.long 0x00 30. " STOP ,Timer operation stop bit" "No effect,Stop"
|
|
bitfld.long 0x00 29. " CONT ,Timer operation restart bit" "No effect,Restart"
|
|
newline
|
|
bitfld.long 0x00 28. " IES ,Timer interrupt enable set bit" "No effect,Enable"
|
|
bitfld.long 0x00 27. " IEC ,Timer interrupt enable clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 26. " IRC ,Timer interrupt request clear bit" "No effect,Clear"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECPL ,End count/preload value setting bits"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TPU0_TCN10,TPU Timer 0 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TPU0_TCN11,TPU Timer 1 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TPU0_TCN12,TPU Timer 2 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TPU0_TCN13,TPU Timer 3 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TPU0_TCN14,TPU Timer 4 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TPU0_TCN15,TPU Timer 5 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TPU0_TCN16,TPU Timer 6 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TPU0_TCN17,TPU Timer 7 Control Register 1"
|
|
bitfld.long 0x00 4. " PL ,Preload function enable/disable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRT ,Free-run function enable setting bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TMOD ,Timer operation mode setting bit" "Normal,Overflow"
|
|
bitfld.long 0x00 0.--1. " PS ,Individual prescaler division setting bit" "/1,/2,/4,/16"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TPU0_TCC0,TPU Timer 0 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TPU0_TCC1,TPU Timer 1 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "TPU0_TCC2,TPU Timer 2 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "TPU0_TCC3,TPU Timer 3 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "TPU0_TCC4,TPU Timer 4 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "TPU0_TCC5,TPU Timer 5 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "TPU0_TCC6,TPU Timer 6 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "TPU0_TCC7,TPU Timer 7 Current Count Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCC ,Timer current count value bits"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SHE (SECURE HARDWARE EXTENSION)"
|
|
base ad:0xB2000000
|
|
width 17.
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x00++0x03 "Configuration Registers For The Command Interface"
|
|
hide.long 0x00 "SHE_CMD,Command Register"
|
|
elif (((per.l(ad:0xB2000000+0x0C))&0x01)==0x01)||(((per.l(ad:0xB2000000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x00++0x03 "Configuration Registers For The Command Interface"
|
|
line.long 0x00 "SHE_CMD,Command Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode"
|
|
else
|
|
group.long 0x0++0x03 "Configuration Registers For The Command Interface"
|
|
line.long 0x00 "SHE_CMD,Command Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command opcode"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SHE_CMDCANCEL,Command Cancel Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SHE_CMDCANCEL,Command Cancel Register"
|
|
bitfld.long 0x00 0. " CANCELREQ ,Cancel request bit" "Not cancelled,Cancelled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SHE_CLKCTRL,Clock Control Register"
|
|
bitfld.long 0x00 16. " DISREQ ,Clock disable request bit" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " ENREQ ,Clock enable request bit" "No effect,Enabled"
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x0C++0x03 "Status Registers For The Command Interface"
|
|
hide.long 0x00 "SHE_STATUS,Status Register"
|
|
else
|
|
rgroup.long 0x0C++0x03 "Status Registers For The Command Interface"
|
|
line.long 0x00 "SHE_STATUS,Status Register"
|
|
bitfld.long 0x00 24. " FATALERR ,Fatal error flag" "No error,Error"
|
|
bitfld.long 0x00 19. " FLASHDED ,Flash double bit ECC error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " FLASHSEC ,Flash single bit ECC warning flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 17. " RAMDED ,RAM double bit ECC error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " RAMSEC ,RAM single bit ECC warning flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " INITDONE ,SHE initialization status flag" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x00 8. " DONE ,Done status flag" "No error,Error"
|
|
bitfld.long 0x00 7. " INTDEBUGGER ,Internal debugger status flag" "Not activated,Activated"
|
|
bitfld.long 0x00 6. " EXTDEBUGGER ,External debugger status flag" "Not connected,Connected"
|
|
newline
|
|
bitfld.long 0x00 5. " RNDINIT ,Random seed initialization status flag" "Not initialized,Initialized"
|
|
bitfld.long 0x00 4. " BOOTOK ,Boot OK status flag" "Failed,Succeed"
|
|
bitfld.long 0x00 3. " BOOTFINISHED ,Boot finished status flag" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 2. " BOOTINIT ,Boot initialization status flag" "Not personalized,Personalized"
|
|
bitfld.long 0x00 1. " SECUREBOOT ,Secure boot activated status flag" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " BUSY ,Busy status flag" "Not busy,Busy"
|
|
endif
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SHE_ERC,Error Code Register"
|
|
in
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SHE_CLKSTAT,Clock Status Register"
|
|
bitfld.long 0x00 0. " CLKOFF ,Clock disabled flag" "No,Yes"
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "SHE_MID,Module ID Register"
|
|
hgroup.long 0x1C++0x03 "Interrupt Registers For Command Interface"
|
|
hide.long 0x00 "SHE_IRQ_SET/CLR,Interrupt Request Register"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SHE_MID,Module ID Register"
|
|
group.long 0x1C++0x03 "Interrupt Registers For Command Interface"
|
|
line.long 0x00 "SHE_IRQ_SET/CLR,Interrupt Request Register"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " FATALERR ,Fatal error interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " IFIFOLOCKERR ,Write to locked input FIFO interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " OMSTIFSELERR ,Output data channel interface selection error interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " IMSTIFSELERR ,Input data channel interface selection error interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OMSTERR ,Output channel master error interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " IMSTERR ,Input channel master error interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " OFIFORDERR ,Read from empty output FIFO error interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " IFIFOWRERR ,Write to full input FIFO error interrupt flag" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 05. 0x04 05. 0x08 05. " OFIFORDTH ,Output FIFO above threshold interrupt flag" "Not greater,Greater"
|
|
newline
|
|
setclrfld.long 0x00 04. 0x04 04. 0x08 04. " IFIFOWRTH ,Input FIFO below threshold interrupt flag" "Not less,Less"
|
|
setclrfld.long 0x00 03. 0x04 03. 0x08 03. " OMSTIDLE ,Output channel master idle interrupt flag" "Not idle,Idle"
|
|
setclrfld.long 0x00 02. 0x04 02. 0x08 02. " IMSTIDLE ,Input channel master idle interrupt" "Not idle,Idle"
|
|
newline
|
|
setclrfld.long 0x00 01. 0x04 01. 0x08 01. " DONE ,Command execution done interrupt flag" "Not finished,Finished"
|
|
setclrfld.long 0x00 00. 0x04 00. 0x08 00. " COMPAREMATCH ,Compare match interrupt flag" "Not transferred,Transferred"
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x28++0x03 "Configuration Registers For The Data Interface"
|
|
hide.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register"
|
|
else
|
|
group.long 0x28++0x03 "Configuration Registers For The Data Interface"
|
|
line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x28++0x03 "Configuration Registers For The Data Interface"
|
|
hide.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register"
|
|
elif (((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)!=0x00)
|
|
rgroup.long 0x28++0x03 "Configuration Registers For The Data Interface"
|
|
line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register"
|
|
else
|
|
group.long 0x28++0x03 "Configuration Registers For The Data Interface"
|
|
line.long 0x00 "SHE_IMSTADDR,Input Channel Master Start Address Register"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register"
|
|
elif (((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)!=0x00)
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SHE_OMSTADDR,Output Channel Master Start Address Register"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SHE_IMSTCNT,Input Channel Master Data Transfer Counter"
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "SHE_OMSTCNT,Out Channel Master Data Transfer Counter"
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "SHE_IMSTSTART,Input Channel Master Start Trigger"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "SHE_OMSTSTART,Output Channel Master Start Trigger"
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "SHE_IMSTCNT,Input Channel Master Data Transfer Counter"
|
|
hexmask.long 0x00 0.--28. 1. " IMSTCNT ,Input channel master data transfer counter"
|
|
line.long 0x04 "SHE_OMSTCNT,Out Channel Master Data Transfer Counter"
|
|
hexmask.long 0x04 0.--28. 1. " OMSTCNT ,Output channel master data transfer counter"
|
|
line.long 0x08 "SHE_IMSTSTART,Input Channel Master Start Trigger"
|
|
bitfld.long 0x08 0. " IMSTSTART ,Input channel master start trigger" "No effect,Started"
|
|
line.long 0x0C "SHE_OMSTSTART,Output Channel Master Start Trigger"
|
|
bitfld.long 0x0C 0. " OMSTSTART ,Output channel master start trigger" "No effect,Started"
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register"
|
|
bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register"
|
|
bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register"
|
|
elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register"
|
|
bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x30))&0x1FFFFFFF)!=0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SHE_IFIFOCFG,Input FIFO Configuration Register"
|
|
rbitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " WRTHRESHOLD ,Programmable write threshold of input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register"
|
|
elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register"
|
|
bitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
elif (((per.l(ad:0xB2000000+0x08))&0x10000)==0x00)&&(((per.l(ad:0xB2000000+0x34))&0x1FFFFFFF)!=0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SHE_OFIFOCFG,Output FIFO Configuration Register"
|
|
rbitfld.long 0x00 16. " IFSEL ,Interface selection bit" "Data,Command"
|
|
bitfld.long 0x00 0.--5. " RDTHRESHOLD ,Programmable read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SHE_COMPARE1,Input FIFO Compare Value Register"
|
|
elif (((per.l(ad:0xB2000000+0x50))&0x01)==0x00)
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register"
|
|
line.long 0x04 "SHE_COMPARE1,Input FIFO Compare Value Register"
|
|
hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register"
|
|
else
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "SHE_COMPARE0,Input FIFO Compare Value Register"
|
|
line.long 0x04 "SHE_COMPARE1,Input FIFO Compare Value Register"
|
|
hexmask.long 0x04 0.--26. 1. " COMPARE ,Most significant bits of the compare register"
|
|
endif
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x50++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_COMPACC,Access Status Register"
|
|
hgroup.long 0x54++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_MSTSTATUS,Data Master Status Register"
|
|
hgroup.long 0x58++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_IMSTERRADDR,Input Channel Master Error Response Address Register"
|
|
hgroup.long 0x5C++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_OMSTERRADDR,Output Channel Master Error Response Address Register"
|
|
hgroup.long 0x60++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_FIFOSTATUS,FIFO Status Register"
|
|
hgroup.long 0x64++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_FIFOLOAD,FIFO Load Register"
|
|
hgroup.long 0x68++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_DATACNT0,Input FIFO Data Counter Register"
|
|
hgroup.long 0x6C++0x03 "Status Registers For Data Interface"
|
|
hide.long 0x00 "SHE_DATACNT1,Input FIFO Data Counter Register"
|
|
else
|
|
rgroup.long 0x50++0x1F "Status Registers For Data Interface"
|
|
line.long 0x00 "SHE_COMPACC,Access Status Register"
|
|
bitfld.long 0x00 0. " CPUEN ,CPU write access enabled status flag" "Not allowed,Allowed"
|
|
line.long 0x04 "SHE_MSTSTATUS,Data Master Status Register"
|
|
bitfld.long 0x04 25.--26. " OMSTERRRESP ,Output data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x04 24. " OMSTERR ,Output data channel master error response flag" "No error,Error"
|
|
bitfld.long 0x04 17. " OMSTLOCK ,Output data channel master lock enabled flag" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x04 16. " OMSTIDLE ,Output data channel master idle flag" "Started,Idle"
|
|
bitfld.long 0x04 9.--10. " IMSTERRRESP ,Input data channel master error response code" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x04 8. " IMSTERR ,Input data channel master error response flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 1. " IMSTLOCK ,Input data channel master lock enabled flag" "Unlocked,Locked"
|
|
bitfld.long 0x04 0. " IMSTIDLE ,Input data channel master idle flag" "Started,Idle"
|
|
line.long 0x08 "SHE_IMSTERRADDR,Input Channel Master Error Response Address Register"
|
|
line.long 0x0C "SHE_OMSTERRADDR,Output Channel Master Error Response Address Register"
|
|
line.long 0x10 "SHE_FIFOSTATUS,FIFO Status Register"
|
|
bitfld.long 0x10 16. " COMPAREMATCH ,Compare march event flag" "Not transferred,Transferred"
|
|
bitfld.long 0x10 8. " OFIFORDTH ,Output FIFO above threshold flag" "Not greater,Greater"
|
|
bitfld.long 0x10 0. " IFIFOWRTH ,Input FIFO below threshold flag" "Not less,Less"
|
|
line.long 0x14 "SHE_FIFOLOAD,FIFO Load Register"
|
|
bitfld.long 0x14 24.--29. " OFIFOLOAD ,Amount of data stored in the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 16.--21. " OFIFOFREE ,Amount of data which can be written into the output FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x14 8.--13. " IFIFOLOAD ,Amount of data stored in the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x14 0.--5. " IFIFOFREE ,Amount of data which can be written into the input FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x18 "SHE_DATACNT0,Input FIFO Data Counter Register"
|
|
line.long 0x1C "SHE_DATACNT1,Input FIFO Data Counter Register"
|
|
hexmask.long 0x1C 0.--26. 1. " DATACNT ,Most significant bits of the data counter register"
|
|
endif
|
|
width 19.
|
|
tree "Data transfer registers"
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x15C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x174++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x178++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x17C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register"
|
|
in
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x184++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x188++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x194++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x198++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x19C++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1A4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1A8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1AC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1B4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1B8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1BC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1C8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1CC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1D4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1D8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1DC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1E4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1E8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1EC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1F4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1F8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register"
|
|
in
|
|
hgroup.long 0x1FC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register"
|
|
in
|
|
else
|
|
if (((per.l(ad:0xB2000000+0x08))&0x10000)==0x10000)
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register"
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register"
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register"
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register"
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register"
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register"
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register"
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register"
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register"
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register"
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register"
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register"
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register"
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register"
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register"
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register"
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register"
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register"
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register"
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register"
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register"
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register"
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register"
|
|
hgroup.long 0x15C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register"
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register"
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register"
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register"
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register"
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register"
|
|
hgroup.long 0x174++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register"
|
|
hgroup.long 0x178++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register"
|
|
hgroup.long 0x17C++0x03
|
|
hide.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register"
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register"
|
|
hgroup.long 0x184++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register"
|
|
hgroup.long 0x188++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register"
|
|
hgroup.long 0x18C++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register"
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register"
|
|
hgroup.long 0x194++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register"
|
|
hgroup.long 0x198++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register"
|
|
hgroup.long 0x19C++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register"
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register"
|
|
hgroup.long 0x1A4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register"
|
|
hgroup.long 0x1A8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register"
|
|
hgroup.long 0x1AC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register"
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register"
|
|
hgroup.long 0x1B4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register"
|
|
hgroup.long 0x1B8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register"
|
|
hgroup.long 0x1BC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register"
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register"
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register"
|
|
hgroup.long 0x1C8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register"
|
|
hgroup.long 0x1CC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register"
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register"
|
|
hgroup.long 0x1D4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register"
|
|
hgroup.long 0x1D8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register"
|
|
hgroup.long 0x1DC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register"
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register"
|
|
hgroup.long 0x1E4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register"
|
|
hgroup.long 0x1E8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register"
|
|
hgroup.long 0x1EC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register"
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register"
|
|
hgroup.long 0x1F4++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register"
|
|
hgroup.long 0x1F8++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register"
|
|
hgroup.long 0x1FC++0x03
|
|
hide.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA0,Input FIFO Write Data Register"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA1,Input FIFO Write Data Register"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA2,Input FIFO Write Data Register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA3,Input FIFO Write Data Register"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA4,Input FIFO Write Data Register"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA5,Input FIFO Write Data Register"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA6,Input FIFO Write Data Register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA7,Input FIFO Write Data Register"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA8,Input FIFO Write Data Register"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA9,Input FIFO Write Data Register"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA10,Input FIFO Write Data Register"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA11,Input FIFO Write Data Register"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA12,Input FIFO Write Data Register"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA13,Input FIFO Write Data Register"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA14,Input FIFO Write Data Register"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA15,Input FIFO Write Data Register"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA16,Input FIFO Write Data Register"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA17,Input FIFO Write Data Register"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA18,Input FIFO Write Data Register"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA19,Input FIFO Write Data Register"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA20,Input FIFO Write Data Register"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA21,Input FIFO Write Data Register"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA22,Input FIFO Write Data Register"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA23,Input FIFO Write Data Register"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA24,Input FIFO Write Data Register"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA25,Input FIFO Write Data Register"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA26,Input FIFO Write Data Register"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA27,Input FIFO Write Data Register"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA28,Input FIFO Write Data Register"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA29,Input FIFO Write Data Register"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA30,Input FIFO Write Data Register"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "SHE_IFIFOWRDATA31,Input FIFO Write Data Register"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA0,Output FIFO Read Data Register"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA1,Output FIFO Read Data Register"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA2,Output FIFO Read Data Register"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA3,Output FIFO Read Data Register"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA4,Output FIFO Read Data Register"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA5,Output FIFO Read Data Register"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA6,Output FIFO Read Data Register"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA7,Output FIFO Read Data Register"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA8,Output FIFO Read Data Register"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA9,Output FIFO Read Data Register"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA10,Output FIFO Read Data Register"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA11,Output FIFO Read Data Register"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA12,Output FIFO Read Data Register"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA13,Output FIFO Read Data Register"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA14,Output FIFO Read Data Register"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA15,Output FIFO Read Data Register"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA16,Output FIFO Read Data Register"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA17,Output FIFO Read Data Register"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA18,Output FIFO Read Data Register"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA19,Output FIFO Read Data Register"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA20,Output FIFO Read Data Register"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA21,Output FIFO Read Data Register"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA22,Output FIFO Read Data Register"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA23,Output FIFO Read Data Register"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA24,Output FIFO Read Data Register"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA25,Output FIFO Read Data Register"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA26,Output FIFO Read Data Register"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA27,Output FIFO Read Data Register"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA28,Output FIFO Read Data Register"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA29,Output FIFO Read Data Register"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA30,Output FIFO Read Data Register"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "SHE_OFIFORDDATA31,Output FIFO Read Data Register"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA CONTROLLER"
|
|
base ad:0xB4700000
|
|
sif cpuis("S6J312?HAA")
|
|
width 13.
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMA0_R,DMA Controller Global Configuration Register"
|
|
bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round robin,?..."
|
|
bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted"
|
|
bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continues,Halted,Stopped,?..."
|
|
newline
|
|
rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "DMA0_DIRQ1,DMA Controller Global Completion Interrupt 1 Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
bitfld.long 0x00 31. " DIRQ_[31] ,Global Completion interrupt 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,Global Completion interrupt 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,Global Completion interrupt 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,Global Completion interrupt 28" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global Completion interrupt 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,Global Completion interrupt 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,Global Completion interrupt 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,Global Completion interrupt 24" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global Completion interrupt 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,Global Completion interrupt 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,Global Completion interrupt 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,Global Completion interrupt 20" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global Completion interrupt 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,Global Completion interrupt 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,Global Completion interrupt 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,Global Completion interrupt 16" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " [15] ,Global Completion interrupt 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Global Completion interrupt 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Global Completion interrupt 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Global Completion interrupt 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global Completion interrupt 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Global Completion interrupt 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Global Completion interrupt 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Global Completion interrupt 8" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global Completion interrupt 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Global Completion interrupt 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Global Completion interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Global Completion interrupt 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global Completion interrupt 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Global Completion interrupt 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Global Completion interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Global Completion interrupt 0" "No interrupt,Interrupt"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "DMA0_DIRQ2,DMA Controller Global Completion Interrupt 2 Register"
|
|
bitfld.long 0x00 31. " DIRQ_[63] ,Global Completion interrupt 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [62] ,Global Completion interrupt 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [61] ,Global Completion interrupt 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [60] ,Global Completion interrupt 60" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [59] ,Global Completion interrupt 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [58] ,Global Completion interrupt 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [57] ,Global Completion interrupt 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,Global Completion interrupt 56" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [55] ,Global Completion interrupt 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [54] ,Global Completion interrupt 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [53] ,Global Completion interrupt 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [52] ,Global Completion interrupt 52" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [51] ,Global Completion interrupt 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [50] ,Global Completion interrupt 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [49] ,Global Completion interrupt 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [48] ,Global Completion interrupt 48" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " [47] ,Global Completion interrupt 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [46] ,Global Completion interrupt 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [45] ,Global Completion interrupt 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [44] ,Global Completion interrupt 44" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [43] ,Global Completion interrupt 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [42] ,Global Completion interrupt 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [41] ,Global Completion interrupt 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [40] ,Global Completion interrupt 40" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [39] ,Global Completion interrupt 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [38] ,Global Completion interrupt 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [37] ,Global Completion interrupt 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [36] ,Global Completion interrupt 36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [35] ,Global Completion interrupt 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [34] ,Global Completion interrupt 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [33] ,Global Completion interrupt 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [32] ,Global Completion interrupt 32" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "DMA0_EDIRQ1,DMA Controller Global Error Interrupt 1 Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
bitfld.long 0x00 31. " EDIRQ_[31] ,Global error interrupt 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Global error interrupt 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Global error interrupt 29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Global error interrupt 28" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global error interrupt 27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [26] ,Global error interrupt 26" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Global error interrupt 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Global error interrupt 24" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global error interrupt 23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Global error interrupt 22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [21] ,Global error interrupt 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Global error interrupt 20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global error interrupt 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Global error interrupt 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Global error interrupt 17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [16] ,Global error interrupt 16" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " [15] ,Global error interrupt 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Global error interrupt 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Global error interrupt 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Global error interrupt 12" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global error interrupt 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Global error interrupt 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Global error interrupt 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Global error interrupt 8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global error interrupt 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [6] ,Global error interrupt 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Global error interrupt 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Global error interrupt 4" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global error interrupt 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Global error interrupt 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [1] ,Global error interrupt 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Global error interrupt 0" "Not occurred,Occurred"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "DMA0_EDIRQ2,DMA Controller Global Error Interrupt 2 Register"
|
|
bitfld.long 0x00 31. " EDIRQ_[63] ,Global error interrupt 63" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [62] ,Global error interrupt 62" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [61] ,Global error interrupt 61" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [60] ,Global error interrupt 60" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " [59] ,Global error interrupt 59" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [58] ,Global error interrupt 58" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [57] ,Global error interrupt 57" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [56] ,Global error interrupt 56" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 23. " [55] ,Global error interrupt 55" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [54] ,Global error interrupt 54" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [53] ,Global error interrupt 53" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [52] ,Global error interrupt 52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " [51] ,Global error interrupt 51" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [50] ,Global error interrupt 50" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [49] ,Global error interrupt 49" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [48] ,Global error interrupt 48" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 15. " [47] ,Global error interrupt 47" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [46] ,Global error interrupt 46" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [45] ,Global error interrupt 45" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [44] ,Global error interrupt 44" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [43] ,Global error interrupt 43" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [42] ,Global error interrupt 42" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [41] ,Global error interrupt 41" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [40] ,Global error interrupt 40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " [39] ,Global error interrupt 39" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [38] ,Global error interrupt 38" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [37] ,Global error interrupt 37" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [36] ,Global error interrupt 36" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " [35] ,Global error interrupt 35" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [34] ,Global error interrupt 34" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [33] ,Global error interrupt 33" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [32] ,Global error interrupt 32" "Not occurred,Occurred"
|
|
endif
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "DMA0_ID,DMA Controller ID Register"
|
|
width 12.
|
|
tree "DMA_A 0--15"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "DMA0_A0,DMA Controller Channel Configuration A Register Channel 0"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA0_A1,DMA Controller Channel Configuration A Register Channel 1"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DMA0_A2,DMA Controller Channel Configuration A Register Channel 2"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DMA0_A3,DMA Controller Channel Configuration A Register Channel 3"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DMA0_A4,DMA Controller Channel Configuration A Register Channel 4"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DMA0_A5,DMA Controller Channel Configuration A Register Channel 5"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DMA0_A6,DMA Controller Channel Configuration A Register Channel 6"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DMA0_A7,DMA Controller Channel Configuration A Register Channel 7"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DMA0_A8,DMA Controller Channel Configuration A Register Channel 8"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMA0_A9,DMA Controller Channel Configuration A Register Channel 9"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DMA0_A10,DMA Controller Channel Configuration A Register Channel 10"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "DMA0_A11,DMA Controller Channel Configuration A Register Channel 11"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DMA0_A12,DMA Controller Channel Configuration A Register Channel 12"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DMA0_A13,DMA Controller Channel Configuration A Register Channel 13"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DMA0_A14,DMA Controller Channel Configuration A Register Channel 14"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DMA0_A15,DMA Controller Channel Configuration A Register Channel 15"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
tree.end
|
|
tree "DMA_B 0--15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "DMA0_B0,DMA Controller Channel Configuration B Register Channel 0"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DMA0_B1,DMA Controller Channel Configuration B Register Channel 1"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "DMA0_B2,DMA Controller Channel Configuration B Register Channel 2"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DMA0_B3,DMA Controller Channel Configuration B Register Channel 3"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DMA0_B4,DMA Controller Channel Configuration B Register Channel 4"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DMA0_B5,DMA Controller Channel Configuration B Register Channel 5"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "DMA0_B6,DMA Controller Channel Configuration B Register Channel 6"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "DMA0_B7,DMA Controller Channel Configuration B Register Channel 7"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DMA0_B8,DMA Controller Channel Configuration B Register Channel 8"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DMA0_B9,DMA Controller Channel Configuration B Register Channel 9"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "DMA0_B10,DMA Controller Channel Configuration B Register Channel 10"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "DMA0_B11,DMA Controller Channel Configuration B Register Channel 11"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DMA0_B12,DMA Controller Channel Configuration B Register Channel 12"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "DMA0_B13,DMA Controller Channel Configuration B Register Channel 13"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "DMA0_B14,DMA Controller Channel Configuration B Register Channel 14"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "DMA0_B15,DMA Controller Channel Configuration B Register Channel 15"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
tree.end
|
|
tree "DMA_SA 0--15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15"
|
|
tree.end
|
|
tree "DMA_DA 0--15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15"
|
|
tree.end
|
|
tree "DMA_C 0--15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DMA0_C0,DMA Controller Channel Configuration C Register Channel 0"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DMA0_C1,DMA Controller Channel Configuration C Register Channel 1"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DMA0_C2,DMA Controller Channel Configuration C Register Channel 2"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DMA0_C3,DMA Controller Channel Configuration C Register Channel 3"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DMA0_C4,DMA Controller Channel Configuration C Register Channel 4"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DMA0_C5,DMA Controller Channel Configuration C Register Channel 5"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "DMA0_C6,DMA Controller Channel Configuration C Register Channel 6"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "DMA0_C7,DMA Controller Channel Configuration C Register Channel 7"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DMA0_C8,DMA Controller Channel Configuration C Register Channel 8"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "DMA0_C9,DMA Controller Channel Configuration C Register Channel 9"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "DMA0_C10,DMA Controller Channel Configuration C Register Channel 10"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "DMA0_C11,DMA Controller Channel Configuration C Register Channel 11"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DMA0_C12,DMA Controller Channel Configuration C Register Channel 12"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "DMA0_C13,DMA Controller Channel Configuration C Register Channel 13"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DMA0_C14,DMA Controller Channel Configuration C Register Channel 14"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "DMA0_C15,DMA Controller Channel Configuration C Register Channel 15"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
tree.end
|
|
tree "DMA_D 0--15"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif !cpuis("S6J320CKSA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J336*")&&!cpuis("S6J337*")
|
|
tree "DMA_E 0--15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA0_E0,DMA Controller Channel Configuration E Register Channel 0"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DMA0_E1,DMA Controller Channel Configuration E Register Channel 1"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DMA0_E2,DMA Controller Channel Configuration E Register Channel 2"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA0_E3,DMA Controller Channel Configuration E Register Channel 3"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DMA0_E4,DMA Controller Channel Configuration E Register Channel 4"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "DMA0_E5,DMA Controller Channel Configuration E Register Channel 5"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "DMA0_E6,DMA Controller Channel Configuration E Register Channel 6"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "DMA0_E7,DMA Controller Channel Configuration E Register Channel 7"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DMA0_E8,DMA Controller Channel Configuration E Register Channel 8"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMA0_E9,DMA Controller Channel Configuration E Register Channel 9"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "DMA0_E10,DMA Controller Channel Configuration E Register Channel 10"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "DMA0_E11,DMA Controller Channel Configuration E Register Channel 11"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DMA0_E12,DMA Controller Channel Configuration E Register Channel 12"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "DMA0_E13,DMA Controller Channel Configuration E Register Channel 13"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "DMA0_E14,DMA Controller Channel Configuration E Register Channel 14"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "DMA0_E15,DMA Controller Channel Configuration E Register Channel 15"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 15.
|
|
tree "DMA_SASHDW DMA_DASHDW 0-15"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DMA0_SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "DMA0_SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "DMA0_SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "DMA0_SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "DMA0_SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "DMA0_SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "DMA0_SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "DMA0_SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "DMA0_SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "DMA0_SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "DMA0_SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "DMA0_SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "DMA0_SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14"
|
|
rgroup.long 0x3D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DMA0_DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "DMA0_DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "DMA0_DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "DMA0_DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "DMA0_DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "DMA0_DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "DMA0_DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "DMA0_DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "DMA0_DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "DMA0_DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "DMA0_DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "DMA0_DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13"
|
|
rgroup.long 0x39C++0x03
|
|
line.long 0x00 "DMA0_DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14"
|
|
rgroup.long 0x3DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15"
|
|
tree.end
|
|
tree "CMICIC"
|
|
sif (cpuis("S6J336*")||cpuis("S6J337*"))
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2028++0x03
|
|
line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x202C++0x03
|
|
line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2030++0x03
|
|
line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2034++0x03
|
|
line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2038++0x03
|
|
line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x203C++0x03
|
|
line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2054++0x03
|
|
line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2058++0x03
|
|
line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x205C++0x03
|
|
line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2060++0x03
|
|
line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2068++0x03
|
|
line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x206C++0x03
|
|
line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2070++0x03
|
|
line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2074++0x03
|
|
line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2078++0x03
|
|
line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x207C++0x03
|
|
line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2080++0x03
|
|
line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2084++0x03
|
|
line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x208C++0x03
|
|
line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2094++0x03
|
|
line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2098++0x03
|
|
line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x209C++0x03
|
|
line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2110++0x03
|
|
line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2114++0x03
|
|
line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2118++0x03
|
|
line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2120++0x03
|
|
line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2124++0x03
|
|
line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2128++0x03
|
|
line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x212C++0x03
|
|
line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2130++0x03
|
|
line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2134++0x03
|
|
line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2138++0x03
|
|
line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x213C++0x03
|
|
line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2140++0x03
|
|
line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2144++0x03
|
|
line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2148++0x03
|
|
line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x214C++0x03
|
|
line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2150++0x03
|
|
line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2154++0x03
|
|
line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2158++0x03
|
|
line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x215C++0x03
|
|
line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2160++0x03
|
|
line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2164++0x03
|
|
line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2168++0x03
|
|
line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x216C++0x03
|
|
line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2170++0x03
|
|
line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2174++0x03
|
|
line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2178++0x03
|
|
line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x218C++0x03
|
|
line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2190++0x03
|
|
line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2194++0x03
|
|
line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2198++0x03
|
|
line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x219C++0x03
|
|
line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC126,DMA Controller Client Matrix Internal Client Interface Configuration Register 126"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x21FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC127,DMA Controller Client Matrix Internal Client Interface Configuration Register 127"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2200++0x03
|
|
line.long 0x00 "DMA0_CMICIC128,DMA Controller Client Matrix Internal Client Interface Configuration Register 128"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2204++0x03
|
|
line.long 0x00 "DMA0_CMICIC129,DMA Controller Client Matrix Internal Client Interface Configuration Register 129"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2208++0x03
|
|
line.long 0x00 "DMA0_CMICIC130,DMA Controller Client Matrix Internal Client Interface Configuration Register 130"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x220C++0x03
|
|
line.long 0x00 "DMA0_CMICIC131,DMA Controller Client Matrix Internal Client Interface Configuration Register 131"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2210++0x03
|
|
line.long 0x00 "DMA0_CMICIC132,DMA Controller Client Matrix Internal Client Interface Configuration Register 132"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2214++0x03
|
|
line.long 0x00 "DMA0_CMICIC133,DMA Controller Client Matrix Internal Client Interface Configuration Register 133"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2218++0x03
|
|
line.long 0x00 "DMA0_CMICIC134,DMA Controller Client Matrix Internal Client Interface Configuration Register 134"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x221C++0x03
|
|
line.long 0x00 "DMA0_CMICIC135,DMA Controller Client Matrix Internal Client Interface Configuration Register 135"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2220++0x03
|
|
line.long 0x00 "DMA0_CMICIC136,DMA Controller Client Matrix Internal Client Interface Configuration Register 136"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2224++0x03
|
|
line.long 0x00 "DMA0_CMICIC137,DMA Controller Client Matrix Internal Client Interface Configuration Register 137"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2228++0x03
|
|
line.long 0x00 "DMA0_CMICIC138,DMA Controller Client Matrix Internal Client Interface Configuration Register 138"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x222C++0x03
|
|
line.long 0x00 "DMA0_CMICIC139,DMA Controller Client Matrix Internal Client Interface Configuration Register 139"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2230++0x03
|
|
line.long 0x00 "DMA0_CMICIC140,DMA Controller Client Matrix Internal Client Interface Configuration Register 140"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2234++0x03
|
|
line.long 0x00 "DMA0_CMICIC141,DMA Controller Client Matrix Internal Client Interface Configuration Register 141"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2238++0x03
|
|
line.long 0x00 "DMA0_CMICIC142,DMA Controller Client Matrix Internal Client Interface Configuration Register 142"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x223C++0x03
|
|
line.long 0x00 "DMA0_CMICIC143,DMA Controller Client Matrix Internal Client Interface Configuration Register 143"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2240++0x03
|
|
line.long 0x00 "DMA0_CMICIC144,DMA Controller Client Matrix Internal Client Interface Configuration Register 144"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2244++0x03
|
|
line.long 0x00 "DMA0_CMICIC145,DMA Controller Client Matrix Internal Client Interface Configuration Register 145"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2248++0x03
|
|
line.long 0x00 "DMA0_CMICIC146,DMA Controller Client Matrix Internal Client Interface Configuration Register 146"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x224C++0x03
|
|
line.long 0x00 "DMA0_CMICIC147,DMA Controller Client Matrix Internal Client Interface Configuration Register 147"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2250++0x03
|
|
line.long 0x00 "DMA0_CMICIC148,DMA Controller Client Matrix Internal Client Interface Configuration Register 148"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2254++0x03
|
|
line.long 0x00 "DMA0_CMICIC149,DMA Controller Client Matrix Internal Client Interface Configuration Register 149"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2258++0x03
|
|
line.long 0x00 "DMA0_CMICIC150,DMA Controller Client Matrix Internal Client Interface Configuration Register 150"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x225C++0x03
|
|
line.long 0x00 "DMA0_CMICIC151,DMA Controller Client Matrix Internal Client Interface Configuration Register 151"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2260++0x03
|
|
line.long 0x00 "DMA0_CMICIC152,DMA Controller Client Matrix Internal Client Interface Configuration Register 152"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2264++0x03
|
|
line.long 0x00 "DMA0_CMICIC153,DMA Controller Client Matrix Internal Client Interface Configuration Register 153"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2268++0x03
|
|
line.long 0x00 "DMA0_CMICIC154,DMA Controller Client Matrix Internal Client Interface Configuration Register 154"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x226C++0x03
|
|
line.long 0x00 "DMA0_CMICIC155,DMA Controller Client Matrix Internal Client Interface Configuration Register 155"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2270++0x03
|
|
line.long 0x00 "DMA0_CMICIC156,DMA Controller Client Matrix Internal Client Interface Configuration Register 156"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2274++0x03
|
|
line.long 0x00 "DMA0_CMICIC157,DMA Controller Client Matrix Internal Client Interface Configuration Register 157"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2278++0x03
|
|
line.long 0x00 "DMA0_CMICIC158,DMA Controller Client Matrix Internal Client Interface Configuration Register 158"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x227C++0x03
|
|
line.long 0x00 "DMA0_CMICIC159,DMA Controller Client Matrix Internal Client Interface Configuration Register 159"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2280++0x03
|
|
line.long 0x00 "DMA0_CMICIC160,DMA Controller Client Matrix Internal Client Interface Configuration Register 160"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2284++0x03
|
|
line.long 0x00 "DMA0_CMICIC161,DMA Controller Client Matrix Internal Client Interface Configuration Register 161"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2288++0x03
|
|
line.long 0x00 "DMA0_CMICIC162,DMA Controller Client Matrix Internal Client Interface Configuration Register 162"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x228C++0x03
|
|
line.long 0x00 "DMA0_CMICIC163,DMA Controller Client Matrix Internal Client Interface Configuration Register 163"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2290++0x03
|
|
line.long 0x00 "DMA0_CMICIC164,DMA Controller Client Matrix Internal Client Interface Configuration Register 164"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2294++0x03
|
|
line.long 0x00 "DMA0_CMICIC165,DMA Controller Client Matrix Internal Client Interface Configuration Register 165"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2298++0x03
|
|
line.long 0x00 "DMA0_CMICIC166,DMA Controller Client Matrix Internal Client Interface Configuration Register 166"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x229C++0x03
|
|
line.long 0x00 "DMA0_CMICIC167,DMA Controller Client Matrix Internal Client Interface Configuration Register 167"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC168,DMA Controller Client Matrix Internal Client Interface Configuration Register 168"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC169,DMA Controller Client Matrix Internal Client Interface Configuration Register 169"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC170,DMA Controller Client Matrix Internal Client Interface Configuration Register 170"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC171,DMA Controller Client Matrix Internal Client Interface Configuration Register 171"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC172,DMA Controller Client Matrix Internal Client Interface Configuration Register 172"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC173,DMA Controller Client Matrix Internal Client Interface Configuration Register 173"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC174,DMA Controller Client Matrix Internal Client Interface Configuration Register 174"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC175,DMA Controller Client Matrix Internal Client Interface Configuration Register 175"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC176,DMA Controller Client Matrix Internal Client Interface Configuration Register 176"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC177,DMA Controller Client Matrix Internal Client Interface Configuration Register 177"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC178,DMA Controller Client Matrix Internal Client Interface Configuration Register 178"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC179,DMA Controller Client Matrix Internal Client Interface Configuration Register 179"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC180,DMA Controller Client Matrix Internal Client Interface Configuration Register 180"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC181,DMA Controller Client Matrix Internal Client Interface Configuration Register 181"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC182,DMA Controller Client Matrix Internal Client Interface Configuration Register 182"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC183,DMA Controller Client Matrix Internal Client Interface Configuration Register 183"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC184,DMA Controller Client Matrix Internal Client Interface Configuration Register 184"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC185,DMA Controller Client Matrix Internal Client Interface Configuration Register 185"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC186,DMA Controller Client Matrix Internal Client Interface Configuration Register 186"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC187,DMA Controller Client Matrix Internal Client Interface Configuration Register 187"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC188,DMA Controller Client Matrix Internal Client Interface Configuration Register 188"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC189,DMA Controller Client Matrix Internal Client Interface Configuration Register 189"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC190,DMA Controller Client Matrix Internal Client Interface Configuration Register 190"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x22FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC191,DMA Controller Client Matrix Internal Client Interface Configuration Register 191"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2300++0x03
|
|
line.long 0x00 "DMA0_CMICIC192,DMA Controller Client Matrix Internal Client Interface Configuration Register 192"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2304++0x03
|
|
line.long 0x00 "DMA0_CMICIC193,DMA Controller Client Matrix Internal Client Interface Configuration Register 193"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2308++0x03
|
|
line.long 0x00 "DMA0_CMICIC194,DMA Controller Client Matrix Internal Client Interface Configuration Register 194"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x230C++0x03
|
|
line.long 0x00 "DMA0_CMICIC195,DMA Controller Client Matrix Internal Client Interface Configuration Register 195"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2310++0x03
|
|
line.long 0x00 "DMA0_CMICIC196,DMA Controller Client Matrix Internal Client Interface Configuration Register 196"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2314++0x03
|
|
line.long 0x00 "DMA0_CMICIC197,DMA Controller Client Matrix Internal Client Interface Configuration Register 197"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2318++0x03
|
|
line.long 0x00 "DMA0_CMICIC198,DMA Controller Client Matrix Internal Client Interface Configuration Register 198"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x231C++0x03
|
|
line.long 0x00 "DMA0_CMICIC199,DMA Controller Client Matrix Internal Client Interface Configuration Register 199"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2320++0x03
|
|
line.long 0x00 "DMA0_CMICIC200,DMA Controller Client Matrix Internal Client Interface Configuration Register 200"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2324++0x03
|
|
line.long 0x00 "DMA0_CMICIC201,DMA Controller Client Matrix Internal Client Interface Configuration Register 201"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2328++0x03
|
|
line.long 0x00 "DMA0_CMICIC202,DMA Controller Client Matrix Internal Client Interface Configuration Register 202"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x232C++0x03
|
|
line.long 0x00 "DMA0_CMICIC203,DMA Controller Client Matrix Internal Client Interface Configuration Register 203"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2330++0x03
|
|
line.long 0x00 "DMA0_CMICIC204,DMA Controller Client Matrix Internal Client Interface Configuration Register 204"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2334++0x03
|
|
line.long 0x00 "DMA0_CMICIC205,DMA Controller Client Matrix Internal Client Interface Configuration Register 205"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2338++0x03
|
|
line.long 0x00 "DMA0_CMICIC206,DMA Controller Client Matrix Internal Client Interface Configuration Register 206"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x233C++0x03
|
|
line.long 0x00 "DMA0_CMICIC207,DMA Controller Client Matrix Internal Client Interface Configuration Register 207"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2340++0x03
|
|
line.long 0x00 "DMA0_CMICIC208,DMA Controller Client Matrix Internal Client Interface Configuration Register 208"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2344++0x03
|
|
line.long 0x00 "DMA0_CMICIC209,DMA Controller Client Matrix Internal Client Interface Configuration Register 209"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2348++0x03
|
|
line.long 0x00 "DMA0_CMICIC210,DMA Controller Client Matrix Internal Client Interface Configuration Register 210"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x234C++0x03
|
|
line.long 0x00 "DMA0_CMICIC211,DMA Controller Client Matrix Internal Client Interface Configuration Register 211"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2350++0x03
|
|
line.long 0x00 "DMA0_CMICIC212,DMA Controller Client Matrix Internal Client Interface Configuration Register 212"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2354++0x03
|
|
line.long 0x00 "DMA0_CMICIC213,DMA Controller Client Matrix Internal Client Interface Configuration Register 213"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2358++0x03
|
|
line.long 0x00 "DMA0_CMICIC214,DMA Controller Client Matrix Internal Client Interface Configuration Register 214"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x235C++0x03
|
|
line.long 0x00 "DMA0_CMICIC215,DMA Controller Client Matrix Internal Client Interface Configuration Register 215"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2360++0x03
|
|
line.long 0x00 "DMA0_CMICIC216,DMA Controller Client Matrix Internal Client Interface Configuration Register 216"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2364++0x03
|
|
line.long 0x00 "DMA0_CMICIC217,DMA Controller Client Matrix Internal Client Interface Configuration Register 217"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2368++0x03
|
|
line.long 0x00 "DMA0_CMICIC218,DMA Controller Client Matrix Internal Client Interface Configuration Register 218"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x236C++0x03
|
|
line.long 0x00 "DMA0_CMICIC219,DMA Controller Client Matrix Internal Client Interface Configuration Register 219"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2370++0x03
|
|
line.long 0x00 "DMA0_CMICIC220,DMA Controller Client Matrix Internal Client Interface Configuration Register 220"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2374++0x03
|
|
line.long 0x00 "DMA0_CMICIC221,DMA Controller Client Matrix Internal Client Interface Configuration Register 221"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2378++0x03
|
|
line.long 0x00 "DMA0_CMICIC222,DMA Controller Client Matrix Internal Client Interface Configuration Register 222"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x237C++0x03
|
|
line.long 0x00 "DMA0_CMICIC223,DMA Controller Client Matrix Internal Client Interface Configuration Register 223"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2380++0x03
|
|
line.long 0x00 "DMA0_CMICIC224,DMA Controller Client Matrix Internal Client Interface Configuration Register 224"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2384++0x03
|
|
line.long 0x00 "DMA0_CMICIC225,DMA Controller Client Matrix Internal Client Interface Configuration Register 225"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2388++0x03
|
|
line.long 0x00 "DMA0_CMICIC226,DMA Controller Client Matrix Internal Client Interface Configuration Register 226"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x238C++0x03
|
|
line.long 0x00 "DMA0_CMICIC227,DMA Controller Client Matrix Internal Client Interface Configuration Register 227"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2390++0x03
|
|
line.long 0x00 "DMA0_CMICIC228,DMA Controller Client Matrix Internal Client Interface Configuration Register 228"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2394++0x03
|
|
line.long 0x00 "DMA0_CMICIC229,DMA Controller Client Matrix Internal Client Interface Configuration Register 229"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2398++0x03
|
|
line.long 0x00 "DMA0_CMICIC230,DMA Controller Client Matrix Internal Client Interface Configuration Register 230"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x239C++0x03
|
|
line.long 0x00 "DMA0_CMICIC231,DMA Controller Client Matrix Internal Client Interface Configuration Register 231"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC232,DMA Controller Client Matrix Internal Client Interface Configuration Register 232"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC233,DMA Controller Client Matrix Internal Client Interface Configuration Register 233"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC234,DMA Controller Client Matrix Internal Client Interface Configuration Register 234"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC235,DMA Controller Client Matrix Internal Client Interface Configuration Register 235"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC236,DMA Controller Client Matrix Internal Client Interface Configuration Register 236"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC237,DMA Controller Client Matrix Internal Client Interface Configuration Register 237"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC238,DMA Controller Client Matrix Internal Client Interface Configuration Register 238"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC239,DMA Controller Client Matrix Internal Client Interface Configuration Register 239"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC240,DMA Controller Client Matrix Internal Client Interface Configuration Register 240"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC241,DMA Controller Client Matrix Internal Client Interface Configuration Register 241"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC242,DMA Controller Client Matrix Internal Client Interface Configuration Register 242"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC243,DMA Controller Client Matrix Internal Client Interface Configuration Register 243"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC244,DMA Controller Client Matrix Internal Client Interface Configuration Register 244"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC245,DMA Controller Client Matrix Internal Client Interface Configuration Register 245"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC246,DMA Controller Client Matrix Internal Client Interface Configuration Register 246"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC247,DMA Controller Client Matrix Internal Client Interface Configuration Register 247"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC248,DMA Controller Client Matrix Internal Client Interface Configuration Register 248"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC249,DMA Controller Client Matrix Internal Client Interface Configuration Register 249"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC250,DMA Controller Client Matrix Internal Client Interface Configuration Register 250"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC251,DMA Controller Client Matrix Internal Client Interface Configuration Register 251"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC252,DMA Controller Client Matrix Internal Client Interface Configuration Register 252"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC253,DMA Controller Client Matrix Internal Client Interface Configuration Register 253"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC254,DMA Controller Client Matrix Internal Client Interface Configuration Register 254"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x23FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC255,DMA Controller Client Matrix Internal Client Interface Configuration Register 255"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2400++0x03
|
|
line.long 0x00 "DMA0_CMICIC256,DMA Controller Client Matrix Internal Client Interface Configuration Register 256"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2404++0x03
|
|
line.long 0x00 "DMA0_CMICIC257,DMA Controller Client Matrix Internal Client Interface Configuration Register 257"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2408++0x03
|
|
line.long 0x00 "DMA0_CMICIC258,DMA Controller Client Matrix Internal Client Interface Configuration Register 258"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x240C++0x03
|
|
line.long 0x00 "DMA0_CMICIC259,DMA Controller Client Matrix Internal Client Interface Configuration Register 259"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2410++0x03
|
|
line.long 0x00 "DMA0_CMICIC260,DMA Controller Client Matrix Internal Client Interface Configuration Register 260"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2414++0x03
|
|
line.long 0x00 "DMA0_CMICIC261,DMA Controller Client Matrix Internal Client Interface Configuration Register 261"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2418++0x03
|
|
line.long 0x00 "DMA0_CMICIC262,DMA Controller Client Matrix Internal Client Interface Configuration Register 262"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x241C++0x03
|
|
line.long 0x00 "DMA0_CMICIC263,DMA Controller Client Matrix Internal Client Interface Configuration Register 263"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2420++0x03
|
|
line.long 0x00 "DMA0_CMICIC264,DMA Controller Client Matrix Internal Client Interface Configuration Register 264"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2424++0x03
|
|
line.long 0x00 "DMA0_CMICIC265,DMA Controller Client Matrix Internal Client Interface Configuration Register 265"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2428++0x03
|
|
line.long 0x00 "DMA0_CMICIC266,DMA Controller Client Matrix Internal Client Interface Configuration Register 266"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x242C++0x03
|
|
line.long 0x00 "DMA0_CMICIC267,DMA Controller Client Matrix Internal Client Interface Configuration Register 267"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2430++0x03
|
|
line.long 0x00 "DMA0_CMICIC268,DMA Controller Client Matrix Internal Client Interface Configuration Register 268"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2434++0x03
|
|
line.long 0x00 "DMA0_CMICIC269,DMA Controller Client Matrix Internal Client Interface Configuration Register 269"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2438++0x03
|
|
line.long 0x00 "DMA0_CMICIC270,DMA Controller Client Matrix Internal Client Interface Configuration Register 270"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x243C++0x03
|
|
line.long 0x00 "DMA0_CMICIC271,DMA Controller Client Matrix Internal Client Interface Configuration Register 271"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2440++0x03
|
|
line.long 0x00 "DMA0_CMICIC272,DMA Controller Client Matrix Internal Client Interface Configuration Register 272"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2444++0x03
|
|
line.long 0x00 "DMA0_CMICIC273,DMA Controller Client Matrix Internal Client Interface Configuration Register 273"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2448++0x03
|
|
line.long 0x00 "DMA0_CMICIC274,DMA Controller Client Matrix Internal Client Interface Configuration Register 274"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x244C++0x03
|
|
line.long 0x00 "DMA0_CMICIC275,DMA Controller Client Matrix Internal Client Interface Configuration Register 275"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2450++0x03
|
|
line.long 0x00 "DMA0_CMICIC276,DMA Controller Client Matrix Internal Client Interface Configuration Register 276"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2454++0x03
|
|
line.long 0x00 "DMA0_CMICIC277,DMA Controller Client Matrix Internal Client Interface Configuration Register 277"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2458++0x03
|
|
line.long 0x00 "DMA0_CMICIC278,DMA Controller Client Matrix Internal Client Interface Configuration Register 278"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x245C++0x03
|
|
line.long 0x00 "DMA0_CMICIC279,DMA Controller Client Matrix Internal Client Interface Configuration Register 279"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2460++0x03
|
|
line.long 0x00 "DMA0_CMICIC280,DMA Controller Client Matrix Internal Client Interface Configuration Register 280"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2464++0x03
|
|
line.long 0x00 "DMA0_CMICIC281,DMA Controller Client Matrix Internal Client Interface Configuration Register 281"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2468++0x03
|
|
line.long 0x00 "DMA0_CMICIC282,DMA Controller Client Matrix Internal Client Interface Configuration Register 282"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x246C++0x03
|
|
line.long 0x00 "DMA0_CMICIC283,DMA Controller Client Matrix Internal Client Interface Configuration Register 283"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2470++0x03
|
|
line.long 0x00 "DMA0_CMICIC284,DMA Controller Client Matrix Internal Client Interface Configuration Register 284"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2474++0x03
|
|
line.long 0x00 "DMA0_CMICIC285,DMA Controller Client Matrix Internal Client Interface Configuration Register 285"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2478++0x03
|
|
line.long 0x00 "DMA0_CMICIC286,DMA Controller Client Matrix Internal Client Interface Configuration Register 286"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x247C++0x03
|
|
line.long 0x00 "DMA0_CMICIC287,DMA Controller Client Matrix Internal Client Interface Configuration Register 287"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2480++0x03
|
|
line.long 0x00 "DMA0_CMICIC288,DMA Controller Client Matrix Internal Client Interface Configuration Register 288"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2484++0x03
|
|
line.long 0x00 "DMA0_CMICIC289,DMA Controller Client Matrix Internal Client Interface Configuration Register 289"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2488++0x03
|
|
line.long 0x00 "DMA0_CMICIC290,DMA Controller Client Matrix Internal Client Interface Configuration Register 290"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x248C++0x03
|
|
line.long 0x00 "DMA0_CMICIC291,DMA Controller Client Matrix Internal Client Interface Configuration Register 291"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2490++0x03
|
|
line.long 0x00 "DMA0_CMICIC292,DMA Controller Client Matrix Internal Client Interface Configuration Register 292"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2494++0x03
|
|
line.long 0x00 "DMA0_CMICIC293,DMA Controller Client Matrix Internal Client Interface Configuration Register 293"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2498++0x03
|
|
line.long 0x00 "DMA0_CMICIC294,DMA Controller Client Matrix Internal Client Interface Configuration Register 294"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x249C++0x03
|
|
line.long 0x00 "DMA0_CMICIC295,DMA Controller Client Matrix Internal Client Interface Configuration Register 295"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC296,DMA Controller Client Matrix Internal Client Interface Configuration Register 296"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC297,DMA Controller Client Matrix Internal Client Interface Configuration Register 297"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC298,DMA Controller Client Matrix Internal Client Interface Configuration Register 298"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC299,DMA Controller Client Matrix Internal Client Interface Configuration Register 299"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC300,DMA Controller Client Matrix Internal Client Interface Configuration Register 300"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC301,DMA Controller Client Matrix Internal Client Interface Configuration Register 301"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC302,DMA Controller Client Matrix Internal Client Interface Configuration Register 302"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC303,DMA Controller Client Matrix Internal Client Interface Configuration Register 303"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC304,DMA Controller Client Matrix Internal Client Interface Configuration Register 304"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC305,DMA Controller Client Matrix Internal Client Interface Configuration Register 305"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC306,DMA Controller Client Matrix Internal Client Interface Configuration Register 306"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC307,DMA Controller Client Matrix Internal Client Interface Configuration Register 307"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC308,DMA Controller Client Matrix Internal Client Interface Configuration Register 308"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC309,DMA Controller Client Matrix Internal Client Interface Configuration Register 309"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC310,DMA Controller Client Matrix Internal Client Interface Configuration Register 310"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC311,DMA Controller Client Matrix Internal Client Interface Configuration Register 311"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC312,DMA Controller Client Matrix Internal Client Interface Configuration Register 312"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC313,DMA Controller Client Matrix Internal Client Interface Configuration Register 313"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC314,DMA Controller Client Matrix Internal Client Interface Configuration Register 314"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC315,DMA Controller Client Matrix Internal Client Interface Configuration Register 315"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC316,DMA Controller Client Matrix Internal Client Interface Configuration Register 316"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC317,DMA Controller Client Matrix Internal Client Interface Configuration Register 317"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC318,DMA Controller Client Matrix Internal Client Interface Configuration Register 318"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x24FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC319,DMA Controller Client Matrix Internal Client Interface Configuration Register 319"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2500++0x03
|
|
line.long 0x00 "DMA0_CMICIC320,DMA Controller Client Matrix Internal Client Interface Configuration Register 320"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2504++0x03
|
|
line.long 0x00 "DMA0_CMICIC321,DMA Controller Client Matrix Internal Client Interface Configuration Register 321"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2508++0x03
|
|
line.long 0x00 "DMA0_CMICIC322,DMA Controller Client Matrix Internal Client Interface Configuration Register 322"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x250C++0x03
|
|
line.long 0x00 "DMA0_CMICIC323,DMA Controller Client Matrix Internal Client Interface Configuration Register 323"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2510++0x03
|
|
line.long 0x00 "DMA0_CMICIC324,DMA Controller Client Matrix Internal Client Interface Configuration Register 324"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2514++0x03
|
|
line.long 0x00 "DMA0_CMICIC325,DMA Controller Client Matrix Internal Client Interface Configuration Register 325"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2518++0x03
|
|
line.long 0x00 "DMA0_CMICIC326,DMA Controller Client Matrix Internal Client Interface Configuration Register 326"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x251C++0x03
|
|
line.long 0x00 "DMA0_CMICIC327,DMA Controller Client Matrix Internal Client Interface Configuration Register 327"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2520++0x03
|
|
line.long 0x00 "DMA0_CMICIC328,DMA Controller Client Matrix Internal Client Interface Configuration Register 328"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2524++0x03
|
|
line.long 0x00 "DMA0_CMICIC329,DMA Controller Client Matrix Internal Client Interface Configuration Register 329"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2528++0x03
|
|
line.long 0x00 "DMA0_CMICIC330,DMA Controller Client Matrix Internal Client Interface Configuration Register 330"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x252C++0x03
|
|
line.long 0x00 "DMA0_CMICIC331,DMA Controller Client Matrix Internal Client Interface Configuration Register 331"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2530++0x03
|
|
line.long 0x00 "DMA0_CMICIC332,DMA Controller Client Matrix Internal Client Interface Configuration Register 332"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2020++0x03
|
|
line.long 0x00 "DMA0_CMICIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2028++0x03
|
|
line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x202C++0x03
|
|
line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2030++0x03
|
|
line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2034++0x03
|
|
line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2038++0x03
|
|
line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x203C++0x03
|
|
line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2054++0x03
|
|
line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2058++0x03
|
|
line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x205C++0x03
|
|
line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2060++0x03
|
|
line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2068++0x03
|
|
line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x206C++0x03
|
|
line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2070++0x03
|
|
line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2074++0x03
|
|
line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2078++0x03
|
|
line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x207C++0x03
|
|
line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2080++0x03
|
|
line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2084++0x03
|
|
line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x208C++0x03
|
|
line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2094++0x03
|
|
line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2098++0x03
|
|
line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x209C++0x03
|
|
line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC46,DMA Controller Client Matrix Internal Client Interface Configuration Register 46"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC47,DMA Controller Client Matrix Internal Client Interface Configuration Register 47"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC48,DMA Controller Client Matrix Internal Client Interface Configuration Register 48"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC49,DMA Controller Client Matrix Internal Client Interface Configuration Register 49"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC50,DMA Controller Client Matrix Internal Client Interface Configuration Register 50"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC51,DMA Controller Client Matrix Internal Client Interface Configuration Register 51"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC52,DMA Controller Client Matrix Internal Client Interface Configuration Register 52"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC53,DMA Controller Client Matrix Internal Client Interface Configuration Register 53"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC54,DMA Controller Client Matrix Internal Client Interface Configuration Register 54"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC55,DMA Controller Client Matrix Internal Client Interface Configuration Register 55"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2110++0x03
|
|
line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2114++0x03
|
|
line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2118++0x03
|
|
line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2120++0x03
|
|
line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2124++0x03
|
|
line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2128++0x03
|
|
line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x212C++0x03
|
|
line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2130++0x03
|
|
line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2134++0x03
|
|
line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2138++0x03
|
|
line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x213C++0x03
|
|
line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2140++0x03
|
|
line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2144++0x03
|
|
line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2148++0x03
|
|
line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x214C++0x03
|
|
line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2150++0x03
|
|
line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2154++0x03
|
|
line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2158++0x03
|
|
line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x215C++0x03
|
|
line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2160++0x03
|
|
line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2164++0x03
|
|
line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2168++0x03
|
|
line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x216C++0x03
|
|
line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2170++0x03
|
|
line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2174++0x03
|
|
line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2178++0x03
|
|
line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x217C++0x03
|
|
line.long 0x00 "DMA0_CMICIC95,DMA Controller Client Matrix Internal Client Interface Configuration Register 95"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2180++0x03
|
|
line.long 0x00 "DMA0_CMICIC96,DMA Controller Client Matrix Internal Client Interface Configuration Register 96"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2184++0x03
|
|
line.long 0x00 "DMA0_CMICIC97,DMA Controller Client Matrix Internal Client Interface Configuration Register 97"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2188++0x03
|
|
line.long 0x00 "DMA0_CMICIC98,DMA Controller Client Matrix Internal Client Interface Configuration Register 98"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x218C++0x03
|
|
line.long 0x00 "DMA0_CMICIC99,DMA Controller Client Matrix Internal Client Interface Configuration Register 99"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2190++0x03
|
|
line.long 0x00 "DMA0_CMICIC100,DMA Controller Client Matrix Internal Client Interface Configuration Register 100"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2194++0x03
|
|
line.long 0x00 "DMA0_CMICIC101,DMA Controller Client Matrix Internal Client Interface Configuration Register 101"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2198++0x03
|
|
line.long 0x00 "DMA0_CMICIC102,DMA Controller Client Matrix Internal Client Interface Configuration Register 102"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x219C++0x03
|
|
line.long 0x00 "DMA0_CMICIC103,DMA Controller Client Matrix Internal Client Interface Configuration Register 103"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC104,DMA Controller Client Matrix Internal Client Interface Configuration Register 104"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC105,DMA Controller Client Matrix Internal Client Interface Configuration Register 105"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC106,DMA Controller Client Matrix Internal Client Interface Configuration Register 106"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC107,DMA Controller Client Matrix Internal Client Interface Configuration Register 107"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC108,DMA Controller Client Matrix Internal Client Interface Configuration Register 108"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC109,DMA Controller Client Matrix Internal Client Interface Configuration Register 109"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC110,DMA Controller Client Matrix Internal Client Interface Configuration Register 110"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC111,DMA Controller Client Matrix Internal Client Interface Configuration Register 111"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC112,DMA Controller Client Matrix Internal Client Interface Configuration Register 112"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC113,DMA Controller Client Matrix Internal Client Interface Configuration Register 113"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC114,DMA Controller Client Matrix Internal Client Interface Configuration Register 114"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC115,DMA Controller Client Matrix Internal Client Interface Configuration Register 115"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC116,DMA Controller Client Matrix Internal Client Interface Configuration Register 116"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC117,DMA Controller Client Matrix Internal Client Interface Configuration Register 117"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC118,DMA Controller Client Matrix Internal Client Interface Configuration Register 118"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC119,DMA Controller Client Matrix Internal Client Interface Configuration Register 119"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC120,DMA Controller Client Matrix Internal Client Interface Configuration Register 120"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC121,DMA Controller Client Matrix Internal Client Interface Configuration Register 121"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC122,DMA Controller Client Matrix Internal Client Interface Configuration Register 122"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC123,DMA Controller Client Matrix Internal Client Interface Configuration Register 123"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC124,DMA Controller Client Matrix Internal Client Interface Configuration Register 124"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC125,DMA Controller Client Matrix Internal Client Interface Configuration Register 125"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC126,DMA Controller Client Matrix Internal Client Interface Configuration Register 126"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x21FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC127,DMA Controller Client Matrix Internal Client Interface Configuration Register 127"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2200++0x03
|
|
line.long 0x00 "DMA0_CMICIC128,DMA Controller Client Matrix Internal Client Interface Configuration Register 128"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2204++0x03
|
|
line.long 0x00 "DMA0_CMICIC129,DMA Controller Client Matrix Internal Client Interface Configuration Register 129"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2208++0x03
|
|
line.long 0x00 "DMA0_CMICIC130,DMA Controller Client Matrix Internal Client Interface Configuration Register 130"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x220C++0x03
|
|
line.long 0x00 "DMA0_CMICIC131,DMA Controller Client Matrix Internal Client Interface Configuration Register 131"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2210++0x03
|
|
line.long 0x00 "DMA0_CMICIC132,DMA Controller Client Matrix Internal Client Interface Configuration Register 132"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2214++0x03
|
|
line.long 0x00 "DMA0_CMICIC133,DMA Controller Client Matrix Internal Client Interface Configuration Register 133"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2218++0x03
|
|
line.long 0x00 "DMA0_CMICIC134,DMA Controller Client Matrix Internal Client Interface Configuration Register 134"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x221C++0x03
|
|
line.long 0x00 "DMA0_CMICIC135,DMA Controller Client Matrix Internal Client Interface Configuration Register 135"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2220++0x03
|
|
line.long 0x00 "DMA0_CMICIC136,DMA Controller Client Matrix Internal Client Interface Configuration Register 136"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2224++0x03
|
|
line.long 0x00 "DMA0_CMICIC137,DMA Controller Client Matrix Internal Client Interface Configuration Register 137"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2228++0x03
|
|
line.long 0x00 "DMA0_CMICIC138,DMA Controller Client Matrix Internal Client Interface Configuration Register 138"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x222C++0x03
|
|
line.long 0x00 "DMA0_CMICIC139,DMA Controller Client Matrix Internal Client Interface Configuration Register 139"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2230++0x03
|
|
line.long 0x00 "DMA0_CMICIC140,DMA Controller Client Matrix Internal Client Interface Configuration Register 140"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2234++0x03
|
|
line.long 0x00 "DMA0_CMICIC141,DMA Controller Client Matrix Internal Client Interface Configuration Register 141"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2238++0x03
|
|
line.long 0x00 "DMA0_CMICIC142,DMA Controller Client Matrix Internal Client Interface Configuration Register 142"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x223C++0x03
|
|
line.long 0x00 "DMA0_CMICIC143,DMA Controller Client Matrix Internal Client Interface Configuration Register 143"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2240++0x03
|
|
line.long 0x00 "DMA0_CMICIC144,DMA Controller Client Matrix Internal Client Interface Configuration Register 144"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2244++0x03
|
|
line.long 0x00 "DMA0_CMICIC145,DMA Controller Client Matrix Internal Client Interface Configuration Register 145"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2248++0x03
|
|
line.long 0x00 "DMA0_CMICIC146,DMA Controller Client Matrix Internal Client Interface Configuration Register 146"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x224C++0x03
|
|
line.long 0x00 "DMA0_CMICIC147,DMA Controller Client Matrix Internal Client Interface Configuration Register 147"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2250++0x03
|
|
line.long 0x00 "DMA0_CMICIC148,DMA Controller Client Matrix Internal Client Interface Configuration Register 148"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2254++0x03
|
|
line.long 0x00 "DMA0_CMICIC149,DMA Controller Client Matrix Internal Client Interface Configuration Register 149"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2258++0x03
|
|
line.long 0x00 "DMA0_CMICIC150,DMA Controller Client Matrix Internal Client Interface Configuration Register 150"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x225C++0x03
|
|
line.long 0x00 "DMA0_CMICIC151,DMA Controller Client Matrix Internal Client Interface Configuration Register 151"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2260++0x03
|
|
line.long 0x00 "DMA0_CMICIC152,DMA Controller Client Matrix Internal Client Interface Configuration Register 152"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2264++0x03
|
|
line.long 0x00 "DMA0_CMICIC153,DMA Controller Client Matrix Internal Client Interface Configuration Register 153"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2268++0x03
|
|
line.long 0x00 "DMA0_CMICIC154,DMA Controller Client Matrix Internal Client Interface Configuration Register 154"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x226C++0x03
|
|
line.long 0x00 "DMA0_CMICIC155,DMA Controller Client Matrix Internal Client Interface Configuration Register 155"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2270++0x03
|
|
line.long 0x00 "DMA0_CMICIC156,DMA Controller Client Matrix Internal Client Interface Configuration Register 156"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2274++0x03
|
|
line.long 0x00 "DMA0_CMICIC157,DMA Controller Client Matrix Internal Client Interface Configuration Register 157"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2278++0x03
|
|
line.long 0x00 "DMA0_CMICIC158,DMA Controller Client Matrix Internal Client Interface Configuration Register 158"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x227C++0x03
|
|
line.long 0x00 "DMA0_CMICIC159,DMA Controller Client Matrix Internal Client Interface Configuration Register 159"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2280++0x03
|
|
line.long 0x00 "DMA0_CMICIC160,DMA Controller Client Matrix Internal Client Interface Configuration Register 160"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2284++0x03
|
|
line.long 0x00 "DMA0_CMICIC161,DMA Controller Client Matrix Internal Client Interface Configuration Register 161"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2288++0x03
|
|
line.long 0x00 "DMA0_CMICIC162,DMA Controller Client Matrix Internal Client Interface Configuration Register 162"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x228C++0x03
|
|
line.long 0x00 "DMA0_CMICIC163,DMA Controller Client Matrix Internal Client Interface Configuration Register 163"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2290++0x03
|
|
line.long 0x00 "DMA0_CMICIC164,DMA Controller Client Matrix Internal Client Interface Configuration Register 164"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2294++0x03
|
|
line.long 0x00 "DMA0_CMICIC165,DMA Controller Client Matrix Internal Client Interface Configuration Register 165"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2298++0x03
|
|
line.long 0x00 "DMA0_CMICIC166,DMA Controller Client Matrix Internal Client Interface Configuration Register 166"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x229C++0x03
|
|
line.long 0x00 "DMA0_CMICIC167,DMA Controller Client Matrix Internal Client Interface Configuration Register 167"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC168,DMA Controller Client Matrix Internal Client Interface Configuration Register 168"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC169,DMA Controller Client Matrix Internal Client Interface Configuration Register 169"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC170,DMA Controller Client Matrix Internal Client Interface Configuration Register 170"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC171,DMA Controller Client Matrix Internal Client Interface Configuration Register 171"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC172,DMA Controller Client Matrix Internal Client Interface Configuration Register 172"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC173,DMA Controller Client Matrix Internal Client Interface Configuration Register 173"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC174,DMA Controller Client Matrix Internal Client Interface Configuration Register 174"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC175,DMA Controller Client Matrix Internal Client Interface Configuration Register 175"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC176,DMA Controller Client Matrix Internal Client Interface Configuration Register 176"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC177,DMA Controller Client Matrix Internal Client Interface Configuration Register 177"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC178,DMA Controller Client Matrix Internal Client Interface Configuration Register 178"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC179,DMA Controller Client Matrix Internal Client Interface Configuration Register 179"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC180,DMA Controller Client Matrix Internal Client Interface Configuration Register 180"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC181,DMA Controller Client Matrix Internal Client Interface Configuration Register 181"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC182,DMA Controller Client Matrix Internal Client Interface Configuration Register 182"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC183,DMA Controller Client Matrix Internal Client Interface Configuration Register 183"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC184,DMA Controller Client Matrix Internal Client Interface Configuration Register 184"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC185,DMA Controller Client Matrix Internal Client Interface Configuration Register 185"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC186,DMA Controller Client Matrix Internal Client Interface Configuration Register 186"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC187,DMA Controller Client Matrix Internal Client Interface Configuration Register 187"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC188,DMA Controller Client Matrix Internal Client Interface Configuration Register 188"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC189,DMA Controller Client Matrix Internal Client Interface Configuration Register 189"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC190,DMA Controller Client Matrix Internal Client Interface Configuration Register 190"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x22FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC191,DMA Controller Client Matrix Internal Client Interface Configuration Register 191"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2300++0x03
|
|
line.long 0x00 "DMA0_CMICIC192,DMA Controller Client Matrix Internal Client Interface Configuration Register 192"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2304++0x03
|
|
line.long 0x00 "DMA0_CMICIC193,DMA Controller Client Matrix Internal Client Interface Configuration Register 193"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2308++0x03
|
|
line.long 0x00 "DMA0_CMICIC194,DMA Controller Client Matrix Internal Client Interface Configuration Register 194"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x230C++0x03
|
|
line.long 0x00 "DMA0_CMICIC195,DMA Controller Client Matrix Internal Client Interface Configuration Register 195"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2310++0x03
|
|
line.long 0x00 "DMA0_CMICIC196,DMA Controller Client Matrix Internal Client Interface Configuration Register 196"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2314++0x03
|
|
line.long 0x00 "DMA0_CMICIC197,DMA Controller Client Matrix Internal Client Interface Configuration Register 197"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2318++0x03
|
|
line.long 0x00 "DMA0_CMICIC198,DMA Controller Client Matrix Internal Client Interface Configuration Register 198"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x231C++0x03
|
|
line.long 0x00 "DMA0_CMICIC199,DMA Controller Client Matrix Internal Client Interface Configuration Register 199"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2320++0x03
|
|
line.long 0x00 "DMA0_CMICIC200,DMA Controller Client Matrix Internal Client Interface Configuration Register 200"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2324++0x03
|
|
line.long 0x00 "DMA0_CMICIC201,DMA Controller Client Matrix Internal Client Interface Configuration Register 201"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2328++0x03
|
|
line.long 0x00 "DMA0_CMICIC202,DMA Controller Client Matrix Internal Client Interface Configuration Register 202"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x232C++0x03
|
|
line.long 0x00 "DMA0_CMICIC203,DMA Controller Client Matrix Internal Client Interface Configuration Register 203"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2330++0x03
|
|
line.long 0x00 "DMA0_CMICIC204,DMA Controller Client Matrix Internal Client Interface Configuration Register 204"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2334++0x03
|
|
line.long 0x00 "DMA0_CMICIC205,DMA Controller Client Matrix Internal Client Interface Configuration Register 205"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2338++0x03
|
|
line.long 0x00 "DMA0_CMICIC206,DMA Controller Client Matrix Internal Client Interface Configuration Register 206"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x233C++0x03
|
|
line.long 0x00 "DMA0_CMICIC207,DMA Controller Client Matrix Internal Client Interface Configuration Register 207"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2340++0x03
|
|
line.long 0x00 "DMA0_CMICIC208,DMA Controller Client Matrix Internal Client Interface Configuration Register 208"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2344++0x03
|
|
line.long 0x00 "DMA0_CMICIC209,DMA Controller Client Matrix Internal Client Interface Configuration Register 209"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2348++0x03
|
|
line.long 0x00 "DMA0_CMICIC210,DMA Controller Client Matrix Internal Client Interface Configuration Register 210"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x234C++0x03
|
|
line.long 0x00 "DMA0_CMICIC211,DMA Controller Client Matrix Internal Client Interface Configuration Register 211"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2350++0x03
|
|
line.long 0x00 "DMA0_CMICIC212,DMA Controller Client Matrix Internal Client Interface Configuration Register 212"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2354++0x03
|
|
line.long 0x00 "DMA0_CMICIC213,DMA Controller Client Matrix Internal Client Interface Configuration Register 213"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2358++0x03
|
|
line.long 0x00 "DMA0_CMICIC214,DMA Controller Client Matrix Internal Client Interface Configuration Register 214"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x235C++0x03
|
|
line.long 0x00 "DMA0_CMICIC215,DMA Controller Client Matrix Internal Client Interface Configuration Register 215"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2360++0x03
|
|
line.long 0x00 "DMA0_CMICIC216,DMA Controller Client Matrix Internal Client Interface Configuration Register 216"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2364++0x03
|
|
line.long 0x00 "DMA0_CMICIC217,DMA Controller Client Matrix Internal Client Interface Configuration Register 217"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2368++0x03
|
|
line.long 0x00 "DMA0_CMICIC218,DMA Controller Client Matrix Internal Client Interface Configuration Register 218"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x236C++0x03
|
|
line.long 0x00 "DMA0_CMICIC219,DMA Controller Client Matrix Internal Client Interface Configuration Register 219"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2370++0x03
|
|
line.long 0x00 "DMA0_CMICIC220,DMA Controller Client Matrix Internal Client Interface Configuration Register 220"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2374++0x03
|
|
line.long 0x00 "DMA0_CMICIC221,DMA Controller Client Matrix Internal Client Interface Configuration Register 221"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2378++0x03
|
|
line.long 0x00 "DMA0_CMICIC222,DMA Controller Client Matrix Internal Client Interface Configuration Register 222"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x237C++0x03
|
|
line.long 0x00 "DMA0_CMICIC223,DMA Controller Client Matrix Internal Client Interface Configuration Register 223"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2380++0x03
|
|
line.long 0x00 "DMA0_CMICIC224,DMA Controller Client Matrix Internal Client Interface Configuration Register 224"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2384++0x03
|
|
line.long 0x00 "DMA0_CMICIC225,DMA Controller Client Matrix Internal Client Interface Configuration Register 225"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2388++0x03
|
|
line.long 0x00 "DMA0_CMICIC226,DMA Controller Client Matrix Internal Client Interface Configuration Register 226"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x238C++0x03
|
|
line.long 0x00 "DMA0_CMICIC227,DMA Controller Client Matrix Internal Client Interface Configuration Register 227"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2390++0x03
|
|
line.long 0x00 "DMA0_CMICIC228,DMA Controller Client Matrix Internal Client Interface Configuration Register 228"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2394++0x03
|
|
line.long 0x00 "DMA0_CMICIC229,DMA Controller Client Matrix Internal Client Interface Configuration Register 229"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2398++0x03
|
|
line.long 0x00 "DMA0_CMICIC230,DMA Controller Client Matrix Internal Client Interface Configuration Register 230"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x239C++0x03
|
|
line.long 0x00 "DMA0_CMICIC231,DMA Controller Client Matrix Internal Client Interface Configuration Register 231"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC232,DMA Controller Client Matrix Internal Client Interface Configuration Register 232"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC233,DMA Controller Client Matrix Internal Client Interface Configuration Register 233"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC234,DMA Controller Client Matrix Internal Client Interface Configuration Register 234"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC235,DMA Controller Client Matrix Internal Client Interface Configuration Register 235"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC236,DMA Controller Client Matrix Internal Client Interface Configuration Register 236"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC237,DMA Controller Client Matrix Internal Client Interface Configuration Register 237"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC238,DMA Controller Client Matrix Internal Client Interface Configuration Register 238"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC239,DMA Controller Client Matrix Internal Client Interface Configuration Register 239"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC240,DMA Controller Client Matrix Internal Client Interface Configuration Register 240"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC241,DMA Controller Client Matrix Internal Client Interface Configuration Register 241"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC242,DMA Controller Client Matrix Internal Client Interface Configuration Register 242"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC243,DMA Controller Client Matrix Internal Client Interface Configuration Register 243"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC244,DMA Controller Client Matrix Internal Client Interface Configuration Register 244"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC245,DMA Controller Client Matrix Internal Client Interface Configuration Register 245"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC246,DMA Controller Client Matrix Internal Client Interface Configuration Register 246"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC247,DMA Controller Client Matrix Internal Client Interface Configuration Register 247"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC248,DMA Controller Client Matrix Internal Client Interface Configuration Register 248"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC249,DMA Controller Client Matrix Internal Client Interface Configuration Register 249"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC250,DMA Controller Client Matrix Internal Client Interface Configuration Register 250"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC251,DMA Controller Client Matrix Internal Client Interface Configuration Register 251"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC252,DMA Controller Client Matrix Internal Client Interface Configuration Register 252"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC253,DMA Controller Client Matrix Internal Client Interface Configuration Register 253"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC254,DMA Controller Client Matrix Internal Client Interface Configuration Register 254"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x23FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC255,DMA Controller Client Matrix Internal Client Interface Configuration Register 255"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2400++0x03
|
|
line.long 0x00 "DMA0_CMICIC256,DMA Controller Client Matrix Internal Client Interface Configuration Register 256"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2404++0x03
|
|
line.long 0x00 "DMA0_CMICIC257,DMA Controller Client Matrix Internal Client Interface Configuration Register 257"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2408++0x03
|
|
line.long 0x00 "DMA0_CMICIC258,DMA Controller Client Matrix Internal Client Interface Configuration Register 258"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x240C++0x03
|
|
line.long 0x00 "DMA0_CMICIC259,DMA Controller Client Matrix Internal Client Interface Configuration Register 259"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2410++0x03
|
|
line.long 0x00 "DMA0_CMICIC260,DMA Controller Client Matrix Internal Client Interface Configuration Register 260"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2414++0x03
|
|
line.long 0x00 "DMA0_CMICIC261,DMA Controller Client Matrix Internal Client Interface Configuration Register 261"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2418++0x03
|
|
line.long 0x00 "DMA0_CMICIC262,DMA Controller Client Matrix Internal Client Interface Configuration Register 262"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x241C++0x03
|
|
line.long 0x00 "DMA0_CMICIC263,DMA Controller Client Matrix Internal Client Interface Configuration Register 263"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2420++0x03
|
|
line.long 0x00 "DMA0_CMICIC264,DMA Controller Client Matrix Internal Client Interface Configuration Register 264"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2424++0x03
|
|
line.long 0x00 "DMA0_CMICIC265,DMA Controller Client Matrix Internal Client Interface Configuration Register 265"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2428++0x03
|
|
line.long 0x00 "DMA0_CMICIC266,DMA Controller Client Matrix Internal Client Interface Configuration Register 266"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x242C++0x03
|
|
line.long 0x00 "DMA0_CMICIC267,DMA Controller Client Matrix Internal Client Interface Configuration Register 267"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2430++0x03
|
|
line.long 0x00 "DMA0_CMICIC268,DMA Controller Client Matrix Internal Client Interface Configuration Register 268"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2434++0x03
|
|
line.long 0x00 "DMA0_CMICIC269,DMA Controller Client Matrix Internal Client Interface Configuration Register 269"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2438++0x03
|
|
line.long 0x00 "DMA0_CMICIC270,DMA Controller Client Matrix Internal Client Interface Configuration Register 270"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x243C++0x03
|
|
line.long 0x00 "DMA0_CMICIC271,DMA Controller Client Matrix Internal Client Interface Configuration Register 271"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2440++0x03
|
|
line.long 0x00 "DMA0_CMICIC272,DMA Controller Client Matrix Internal Client Interface Configuration Register 272"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2444++0x03
|
|
line.long 0x00 "DMA0_CMICIC273,DMA Controller Client Matrix Internal Client Interface Configuration Register 273"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2448++0x03
|
|
line.long 0x00 "DMA0_CMICIC274,DMA Controller Client Matrix Internal Client Interface Configuration Register 274"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x244C++0x03
|
|
line.long 0x00 "DMA0_CMICIC275,DMA Controller Client Matrix Internal Client Interface Configuration Register 275"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2450++0x03
|
|
line.long 0x00 "DMA0_CMICIC276,DMA Controller Client Matrix Internal Client Interface Configuration Register 276"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2454++0x03
|
|
line.long 0x00 "DMA0_CMICIC277,DMA Controller Client Matrix Internal Client Interface Configuration Register 277"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2458++0x03
|
|
line.long 0x00 "DMA0_CMICIC278,DMA Controller Client Matrix Internal Client Interface Configuration Register 278"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x245C++0x03
|
|
line.long 0x00 "DMA0_CMICIC279,DMA Controller Client Matrix Internal Client Interface Configuration Register 279"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2460++0x03
|
|
line.long 0x00 "DMA0_CMICIC280,DMA Controller Client Matrix Internal Client Interface Configuration Register 280"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2464++0x03
|
|
line.long 0x00 "DMA0_CMICIC281,DMA Controller Client Matrix Internal Client Interface Configuration Register 281"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2468++0x03
|
|
line.long 0x00 "DMA0_CMICIC282,DMA Controller Client Matrix Internal Client Interface Configuration Register 282"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x246C++0x03
|
|
line.long 0x00 "DMA0_CMICIC283,DMA Controller Client Matrix Internal Client Interface Configuration Register 283"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2470++0x03
|
|
line.long 0x00 "DMA0_CMICIC284,DMA Controller Client Matrix Internal Client Interface Configuration Register 284"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2474++0x03
|
|
line.long 0x00 "DMA0_CMICIC285,DMA Controller Client Matrix Internal Client Interface Configuration Register 285"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2478++0x03
|
|
line.long 0x00 "DMA0_CMICIC286,DMA Controller Client Matrix Internal Client Interface Configuration Register 286"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x247C++0x03
|
|
line.long 0x00 "DMA0_CMICIC287,DMA Controller Client Matrix Internal Client Interface Configuration Register 287"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2480++0x03
|
|
line.long 0x00 "DMA0_CMICIC288,DMA Controller Client Matrix Internal Client Interface Configuration Register 288"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2484++0x03
|
|
line.long 0x00 "DMA0_CMICIC289,DMA Controller Client Matrix Internal Client Interface Configuration Register 289"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2488++0x03
|
|
line.long 0x00 "DMA0_CMICIC290,DMA Controller Client Matrix Internal Client Interface Configuration Register 290"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x248C++0x03
|
|
line.long 0x00 "DMA0_CMICIC291,DMA Controller Client Matrix Internal Client Interface Configuration Register 291"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2490++0x03
|
|
line.long 0x00 "DMA0_CMICIC292,DMA Controller Client Matrix Internal Client Interface Configuration Register 292"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2494++0x03
|
|
line.long 0x00 "DMA0_CMICIC293,DMA Controller Client Matrix Internal Client Interface Configuration Register 293"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2498++0x03
|
|
line.long 0x00 "DMA0_CMICIC294,DMA Controller Client Matrix Internal Client Interface Configuration Register 294"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x249C++0x03
|
|
line.long 0x00 "DMA0_CMICIC295,DMA Controller Client Matrix Internal Client Interface Configuration Register 295"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC296,DMA Controller Client Matrix Internal Client Interface Configuration Register 296"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC297,DMA Controller Client Matrix Internal Client Interface Configuration Register 297"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC298,DMA Controller Client Matrix Internal Client Interface Configuration Register 298"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC299,DMA Controller Client Matrix Internal Client Interface Configuration Register 299"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC300,DMA Controller Client Matrix Internal Client Interface Configuration Register 300"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC301,DMA Controller Client Matrix Internal Client Interface Configuration Register 301"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC302,DMA Controller Client Matrix Internal Client Interface Configuration Register 302"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC303,DMA Controller Client Matrix Internal Client Interface Configuration Register 303"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC304,DMA Controller Client Matrix Internal Client Interface Configuration Register 304"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC305,DMA Controller Client Matrix Internal Client Interface Configuration Register 305"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC306,DMA Controller Client Matrix Internal Client Interface Configuration Register 306"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC307,DMA Controller Client Matrix Internal Client Interface Configuration Register 307"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC308,DMA Controller Client Matrix Internal Client Interface Configuration Register 308"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC309,DMA Controller Client Matrix Internal Client Interface Configuration Register 309"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC310,DMA Controller Client Matrix Internal Client Interface Configuration Register 310"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC311,DMA Controller Client Matrix Internal Client Interface Configuration Register 311"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC312,DMA Controller Client Matrix Internal Client Interface Configuration Register 312"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC313,DMA Controller Client Matrix Internal Client Interface Configuration Register 313"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC314,DMA Controller Client Matrix Internal Client Interface Configuration Register 314"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC315,DMA Controller Client Matrix Internal Client Interface Configuration Register 315"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC316,DMA Controller Client Matrix Internal Client Interface Configuration Register 316"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC317,DMA Controller Client Matrix Internal Client Interface Configuration Register 317"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC318,DMA Controller Client Matrix Internal Client Interface Configuration Register 318"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x24FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC319,DMA Controller Client Matrix Internal Client Interface Configuration Register 319"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2500++0x03
|
|
line.long 0x00 "DMA0_CMICIC320,DMA Controller Client Matrix Internal Client Interface Configuration Register 320"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2504++0x03
|
|
line.long 0x00 "DMA0_CMICIC321,DMA Controller Client Matrix Internal Client Interface Configuration Register 321"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2508++0x03
|
|
line.long 0x00 "DMA0_CMICIC322,DMA Controller Client Matrix Internal Client Interface Configuration Register 322"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x250C++0x03
|
|
line.long 0x00 "DMA0_CMICIC323,DMA Controller Client Matrix Internal Client Interface Configuration Register 323"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2510++0x03
|
|
line.long 0x00 "DMA0_CMICIC324,DMA Controller Client Matrix Internal Client Interface Configuration Register 324"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2514++0x03
|
|
line.long 0x00 "DMA0_CMICIC325,DMA Controller Client Matrix Internal Client Interface Configuration Register 325"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2518++0x03
|
|
line.long 0x00 "DMA0_CMICIC326,DMA Controller Client Matrix Internal Client Interface Configuration Register 326"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x251C++0x03
|
|
line.long 0x00 "DMA0_CMICIC327,DMA Controller Client Matrix Internal Client Interface Configuration Register 327"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2520++0x03
|
|
line.long 0x00 "DMA0_CMICIC328,DMA Controller Client Matrix Internal Client Interface Configuration Register 328"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2524++0x03
|
|
line.long 0x00 "DMA0_CMICIC329,DMA Controller Client Matrix Internal Client Interface Configuration Register 329"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2528++0x03
|
|
line.long 0x00 "DMA0_CMICIC330,DMA Controller Client Matrix Internal Client Interface Configuration Register 330"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x252C++0x03
|
|
line.long 0x00 "DMA0_CMICIC331,DMA Controller Client Matrix Internal Client Interface Configuration Register 331"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
endif
|
|
tree.end
|
|
tree "CMCHIC 0-15"
|
|
group.long 0x2800++0x03
|
|
line.long 0x00 "DMA0_CMCHIC0,DMA Controller Client Matrix Channel Interface Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2804++0x03
|
|
line.long 0x00 "DMA0_CMCHIC1,DMA Controller Client Matrix Channel Interface Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2808++0x03
|
|
line.long 0x00 "DMA0_CMCHIC2,DMA Controller Client Matrix Channel Interface Configuration Register 2"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x280C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC3,DMA Controller Client Matrix Channel Interface Configuration Register 3"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2810++0x03
|
|
line.long 0x00 "DMA0_CMCHIC4,DMA Controller Client Matrix Channel Interface Configuration Register 4"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2814++0x03
|
|
line.long 0x00 "DMA0_CMCHIC5,DMA Controller Client Matrix Channel Interface Configuration Register 5"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2818++0x03
|
|
line.long 0x00 "DMA0_CMCHIC6,DMA Controller Client Matrix Channel Interface Configuration Register 6"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x281C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC7,DMA Controller Client Matrix Channel Interface Configuration Register 7"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2820++0x03
|
|
line.long 0x00 "DMA0_CMCHIC8,DMA Controller Client Matrix Channel Interface Configuration Register 8"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2824++0x03
|
|
line.long 0x00 "DMA0_CMCHIC9,DMA Controller Client Matrix Channel Interface Configuration Register 9"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2828++0x03
|
|
line.long 0x00 "DMA0_CMCHIC10,DMA Controller Client Matrix Channel Interface Configuration Register 10"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x282C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC11,DMA Controller Client Matrix Channel Interface Configuration Register 11"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2830++0x03
|
|
line.long 0x00 "DMA0_CMCHIC12,DMA Controller Client Matrix Channel Interface Configuration Register 12"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2834++0x03
|
|
line.long 0x00 "DMA0_CMCHIC13,DMA Controller Client Matrix Channel Interface Configuration Register 13"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2838++0x03
|
|
line.long 0x00 "DMA0_CMCHIC14,DMA Controller Client Matrix Channel Interface Configuration Register 14"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x283C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC15,DMA Controller Client Matrix Channel Interface Configuration Register 15"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "DMA0_R,DMA Controller Global Configuration Register"
|
|
bitfld.long 0x00 31. " DE ,DMA enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 30. " DSHR ,DMA stop/halt request flag" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " DBE ,Debug enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " PR ,Priority type" "Fixed,Dynamic,Round robin,?..."
|
|
bitfld.long 0x00 26. " DH ,DMA halt" "Not halted,Halted"
|
|
bitfld.long 0x00 24.--25. " DB ,Debug behavior" "Continues,Halted,Stopped,?..."
|
|
newline
|
|
rbitfld.long 0x00 0. " DSHS ,DMA stop/halt status flag" "Running,Halted"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "DMA0_DIRQ1,DMA Controller Global Completion Interrupt 1 Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
bitfld.long 0x00 31. " DIRQ_[31] ,Global Completion interrupt 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [30] ,Global Completion interrupt 30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [29] ,Global Completion interrupt 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [28] ,Global Completion interrupt 28" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global Completion interrupt 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [26] ,Global Completion interrupt 26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [25] ,Global Completion interrupt 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [24] ,Global Completion interrupt 24" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global Completion interrupt 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,Global Completion interrupt 22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,Global Completion interrupt 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,Global Completion interrupt 20" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global Completion interrupt 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,Global Completion interrupt 18" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,Global Completion interrupt 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,Global Completion interrupt 16" "No interrupt,Interrupt"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " [15] ,Global Completion interrupt 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,Global Completion interrupt 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,Global Completion interrupt 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,Global Completion interrupt 12" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global Completion interrupt 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,Global Completion interrupt 10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,Global Completion interrupt 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,Global Completion interrupt 8" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global Completion interrupt 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,Global Completion interrupt 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,Global Completion interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,Global Completion interrupt 4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global Completion interrupt 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Global Completion interrupt 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Global Completion interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Global Completion interrupt 0" "No interrupt,Interrupt"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
rgroup.long 0x1008++0x03
|
|
line.long 0x00 "DMA0_DIRQ2,DMA Controller Global Completion Interrupt 2 Register"
|
|
bitfld.long 0x00 31. " DIRQ_[63] ,Global Completion interrupt 63" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " [62] ,Global Completion interrupt 62" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " [61] ,Global Completion interrupt 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " [60] ,Global Completion interrupt 60" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. " [59] ,Global Completion interrupt 59" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " [58] ,Global Completion interrupt 58" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " [57] ,Global Completion interrupt 57" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " [56] ,Global Completion interrupt 56" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " [55] ,Global Completion interrupt 55" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [54] ,Global Completion interrupt 54" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [53] ,Global Completion interrupt 53" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [52] ,Global Completion interrupt 52" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [51] ,Global Completion interrupt 51" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [50] ,Global Completion interrupt 50" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [49] ,Global Completion interrupt 49" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [48] ,Global Completion interrupt 48" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " [47] ,Global Completion interrupt 47" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [46] ,Global Completion interrupt 46" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [45] ,Global Completion interrupt 45" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [44] ,Global Completion interrupt 44" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [43] ,Global Completion interrupt 43" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [42] ,Global Completion interrupt 42" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [41] ,Global Completion interrupt 41" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [40] ,Global Completion interrupt 40" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [39] ,Global Completion interrupt 39" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [38] ,Global Completion interrupt 38" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [37] ,Global Completion interrupt 37" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [36] ,Global Completion interrupt 36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [35] ,Global Completion interrupt 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [34] ,Global Completion interrupt 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [33] ,Global Completion interrupt 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [32] ,Global Completion interrupt 32" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0x100C++0x03
|
|
line.long 0x00 "DMA0_EDIRQ1,DMA Controller Global Error Interrupt 1 Register"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
bitfld.long 0x00 31. " EDIRQ_[31] ,Global error interrupt 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Global error interrupt 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Global error interrupt 29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Global error interrupt 28" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global error interrupt 27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [26] ,Global error interrupt 26" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Global error interrupt 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Global error interrupt 24" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global error interrupt 23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Global error interrupt 22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [21] ,Global error interrupt 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Global error interrupt 20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global error interrupt 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Global error interrupt 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Global error interrupt 17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [16] ,Global error interrupt 16" "Not occurred,Occurred"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " [15] ,Global error interrupt 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Global error interrupt 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Global error interrupt 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Global error interrupt 12" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global error interrupt 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Global error interrupt 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Global error interrupt 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Global error interrupt 8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global error interrupt 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [6] ,Global error interrupt 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Global error interrupt 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Global error interrupt 4" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global error interrupt 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Global error interrupt 2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [1] ,Global error interrupt 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Global error interrupt 0" "Not occurred,Occurred"
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")
|
|
rgroup.long 0x1010++0x03
|
|
line.long 0x00 "DMA0_EDIRQ2,DMA Controller Global Error Interrupt 2 Register"
|
|
bitfld.long 0x00 31. " EDIRQ_[63] ,Global error interrupt 63" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [62] ,Global error interrupt 62" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [61] ,Global error interrupt 61" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [60] ,Global error interrupt 60" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " [59] ,Global error interrupt 59" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [58] ,Global error interrupt 58" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [57] ,Global error interrupt 57" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [56] ,Global error interrupt 56" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 23. " [55] ,Global error interrupt 55" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [54] ,Global error interrupt 54" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [53] ,Global error interrupt 53" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [52] ,Global error interrupt 52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " [51] ,Global error interrupt 51" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [50] ,Global error interrupt 50" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [49] ,Global error interrupt 49" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [48] ,Global error interrupt 48" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 15. " [47] ,Global error interrupt 47" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [46] ,Global error interrupt 46" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [45] ,Global error interrupt 45" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [44] ,Global error interrupt 44" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [43] ,Global error interrupt 43" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [42] ,Global error interrupt 42" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [41] ,Global error interrupt 41" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [40] ,Global error interrupt 40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " [39] ,Global error interrupt 39" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [38] ,Global error interrupt 38" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [37] ,Global error interrupt 37" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [36] ,Global error interrupt 36" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " [35] ,Global error interrupt 35" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [34] ,Global error interrupt 34" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [33] ,Global error interrupt 33" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [32] ,Global error interrupt 32" "Not occurred,Occurred"
|
|
endif
|
|
rgroup.long 0x1014++0x03
|
|
line.long 0x00 "DMA0_ID,DMA Controller ID Register"
|
|
width 12.
|
|
tree "DMA_A 0--15"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "DMA0_A0,DMA Controller Channel Configuration A Register Channel 0"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DMA0_A1,DMA Controller Channel Configuration A Register Channel 1"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DMA0_A2,DMA Controller Channel Configuration A Register Channel 2"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DMA0_A3,DMA Controller Channel Configuration A Register Channel 3"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DMA0_A4,DMA Controller Channel Configuration A Register Channel 4"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DMA0_A5,DMA Controller Channel Configuration A Register Channel 5"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DMA0_A6,DMA Controller Channel Configuration A Register Channel 6"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "DMA0_A7,DMA Controller Channel Configuration A Register Channel 7"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DMA0_A8,DMA Controller Channel Configuration A Register Channel 8"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMA0_A9,DMA Controller Channel Configuration A Register Channel 9"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DMA0_A10,DMA Controller Channel Configuration A Register Channel 10"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "DMA0_A11,DMA Controller Channel Configuration A Register Channel 11"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DMA0_A12,DMA Controller Channel Configuration A Register Channel 12"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "DMA0_A13,DMA Controller Channel Configuration A Register Channel 13"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DMA0_A14,DMA Controller Channel Configuration A Register Channel 14"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "DMA0_A15,DMA Controller Channel Configuration A Register Channel 15"
|
|
bitfld.long 0x00 31. " EB ,Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PB ,Pause bit" "Not halted,Halted"
|
|
bitfld.long 0x00 29. " ST ,Software trigger" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27.--28. " IS ,Input select" "Software,Hardware,?..."
|
|
bitfld.long 0x00 26. " AL ,Alternate" "Contiguous,Alternate"
|
|
bitfld.long 0x00 24.--25. " BL ,Beat Limit" "Single,INCR4,INCR8,INCR16"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " BC ,Black count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer count"
|
|
tree.end
|
|
tree "DMA_B 0--15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "DMA0_B0,DMA Controller Channel Configuration B Register Channel 0"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DMA0_B1,DMA Controller Channel Configuration B Register Channel 1"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "DMA0_B2,DMA Controller Channel Configuration B Register Channel 2"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DMA0_B3,DMA Controller Channel Configuration B Register Channel 3"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DMA0_B4,DMA Controller Channel Configuration B Register Channel 4"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DMA0_B5,DMA Controller Channel Configuration B Register Channel 5"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "DMA0_B6,DMA Controller Channel Configuration B Register Channel 6"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "DMA0_B7,DMA Controller Channel Configuration B Register Channel 7"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DMA0_B8,DMA Controller Channel Configuration B Register Channel 8"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DMA0_B9,DMA Controller Channel Configuration B Register Channel 9"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "DMA0_B10,DMA Controller Channel Configuration B Register Channel 10"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "DMA0_B11,DMA Controller Channel Configuration B Register Channel 11"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DMA0_B12,DMA Controller Channel Configuration B Register Channel 12"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "DMA0_B13,DMA Controller Channel Configuration B Register Channel 13"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "DMA0_B14,DMA Controller Channel Configuration B Register Channel 14"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
group.long 0x3C4++0x03
|
|
line.long 0x00 "DMA0_B15,DMA Controller Channel Configuration B Register Channel 15"
|
|
rbitfld.long 0x00 31. " DQ ,Flag of DIRQ" "Not completed,Completed"
|
|
rbitfld.long 0x00 30. " EQ ,Flag of EDIRQ" "No error,Error"
|
|
bitfld.long 0x00 28.--29. " MS ,Mode select" "Block,Burst,?..."
|
|
newline
|
|
bitfld.long 0x00 26.--27. " TW ,Transfer width" "Byte,Half word,Word,Double word"
|
|
rbitfld.long 0x00 25. " SR ,Software trigger ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " EI ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " CI ,Completion interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16.--18. " SS ,Stop status" "None,,DSTP/Channel disable/DMA disable/Debug event,Source access error,Destination access error,Normal end,?..."
|
|
newline
|
|
bitfld.long 0x00 15. " SP[3] ,Source protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 14. " SP[2] ,Source protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 13. " SP[1] ,Source protection" "User access,Privileged access"
|
|
rbitfld.long 0x00 12. " SP[0] ,Source protection" "Instruction access,Data success"
|
|
newline
|
|
bitfld.long 0x00 11. " DP[3] ,Destination protection" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 10. " DP[2] ,Destination protection" "Not bufferable,bufferable"
|
|
bitfld.long 0x00 9. " DP[1] ,Destination protection" "User access,Privileged access"
|
|
newline
|
|
rbitfld.long 0x00 8. " DP[0] ,Destination protection" "Instruction access,Data success"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PN ,Priority number"
|
|
tree.end
|
|
tree "DMA_SA 0--15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "DMA0_SA0,DMA Controller Channel Configuration Source Address Register Channel 0"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DMA0_SA1,DMA Controller Channel Configuration Source Address Register Channel 1"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "DMA0_SA2,DMA Controller Channel Configuration Source Address Register Channel 2"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DMA0_SA3,DMA Controller Channel Configuration Source Address Register Channel 3"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DMA0_SA4,DMA Controller Channel Configuration Source Address Register Channel 4"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DMA0_SA5,DMA Controller Channel Configuration Source Address Register Channel 5"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "DMA0_SA6,DMA Controller Channel Configuration Source Address Register Channel 6"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "DMA0_SA7,DMA Controller Channel Configuration Source Address Register Channel 7"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DMA0_SA8,DMA Controller Channel Configuration Source Address Register Channel 8"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "DMA0_SA9,DMA Controller Channel Configuration Source Address Register Channel 9"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "DMA0_SA10,DMA Controller Channel Configuration Source Address Register Channel 10"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "DMA0_SA11,DMA Controller Channel Configuration Source Address Register Channel 11"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DMA0_SA12,DMA Controller Channel Configuration Source Address Register Channel 12"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "DMA0_SA13,DMA Controller Channel Configuration Source Address Register Channel 13"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "DMA0_SA14,DMA Controller Channel Configuration Source Address Register Channel 14"
|
|
group.long 0x3C8++0x03
|
|
line.long 0x00 "DMA0_SA15,DMA Controller Channel Configuration Source Address Register Channel 15"
|
|
tree.end
|
|
tree "DMA_DA 0--15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "DMA0_DA0,DMA Controller Channel Configuration Destination Address Register Channel 0"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "DMA0_DA1,DMA Controller Channel Configuration Destination Address Register Channel 1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "DMA0_DA2,DMA Controller Channel Configuration Destination Address Register Channel 2"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "DMA0_DA3,DMA Controller Channel Configuration Destination Address Register Channel 3"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DMA0_DA4,DMA Controller Channel Configuration Destination Address Register Channel 4"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DMA0_DA5,DMA Controller Channel Configuration Destination Address Register Channel 5"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "DMA0_DA6,DMA Controller Channel Configuration Destination Address Register Channel 6"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "DMA0_DA7,DMA Controller Channel Configuration Destination Address Register Channel 7"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DMA0_DA8,DMA Controller Channel Configuration Destination Address Register Channel 8"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "DMA0_DA9,DMA Controller Channel Configuration Destination Address Register Channel 9"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "DMA0_DA10,DMA Controller Channel Configuration Destination Address Register Channel 10"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "DMA0_DA11,DMA Controller Channel Configuration Destination Address Register Channel 11"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DMA0_DA12,DMA Controller Channel Configuration Destination Address Register Channel 12"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "DMA0_DA13,DMA Controller Channel Configuration Destination Address Register Channel 13"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "DMA0_DA14,DMA Controller Channel Configuration Destination Address Register Channel 14"
|
|
group.long 0x3CC++0x03
|
|
line.long 0x00 "DMA0_DA15,DMA Controller Channel Configuration Destination Address Register Channel 15"
|
|
tree.end
|
|
tree "DMA_C 0--15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DMA0_C0,DMA Controller Channel Configuration C Register Channel 0"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DMA0_C1,DMA Controller Channel Configuration C Register Channel 1"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DMA0_C2,DMA Controller Channel Configuration C Register Channel 2"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DMA0_C3,DMA Controller Channel Configuration C Register Channel 3"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DMA0_C4,DMA Controller Channel Configuration C Register Channel 4"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DMA0_C5,DMA Controller Channel Configuration C Register Channel 5"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "DMA0_C6,DMA Controller Channel Configuration C Register Channel 6"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "DMA0_C7,DMA Controller Channel Configuration C Register Channel 7"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DMA0_C8,DMA Controller Channel Configuration C Register Channel 8"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "DMA0_C9,DMA Controller Channel Configuration C Register Channel 9"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "DMA0_C10,DMA Controller Channel Configuration C Register Channel 10"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "DMA0_C11,DMA Controller Channel Configuration C Register Channel 11"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DMA0_C12,DMA Controller Channel Configuration C Register Channel 12"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "DMA0_C13,DMA Controller Channel Configuration C Register Channel 13"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DMA0_C14,DMA Controller Channel Configuration C Register Channel 14"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "DMA0_C15,DMA Controller Channel Configuration C Register Channel 15"
|
|
bitfld.long 0x00 8. " CE ,Clear EDIRQ" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CD ,Clear DIRQ" "No effect,Clear"
|
|
tree.end
|
|
tree "DMA_D 0--15"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x15))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x15))&0x80)==0x00)
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "DMA0_D0_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x55))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x55))&0x80)==0x00)
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "DMA0_D1_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x95))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x95))&0x80)==0x00)
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "DMA0_D2_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD5))&0x80)==0x00)
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "DMA0_D3_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x115))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x115))&0x80)==0x00)
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "DMA0_D4_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x155))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x155))&0x80)==0x00)
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "DMA0_D5_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x195))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x195))&0x80)==0x00)
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "DMA0_D6_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D5))&0x80)==0x00)
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "DMA0_D7_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x215))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x215))&0x80)==0x00)
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "DMA0_D8_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x255))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x255))&0x80)==0x00)
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "DMA0_D9_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x295))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x295))&0x80)==0x00)
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "DMA0_D10_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D5))&0x80)==0x00)
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "DMA0_D11_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x315))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x315))&0x80)==0x00)
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "DMA0_D12_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x355))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x355))&0x80)==0x00)
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "DMA0_D13_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x395))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x395))&0x80)==0x00)
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "DMA0_D14_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DED ,Decrement destination address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " UD ,Update destination address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D5))&0x80)==0x00)
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBD ,Fixed block destination address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "DMA0_D15_1,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FD ,Fixed destination address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+0.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x17))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x17))&0x80)==0x00)
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "DMA0_D0_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+1.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x57))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x57))&0x80)==0x00)
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "DMA0_D1_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+2.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x97))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x97))&0x80)==0x00)
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "DMA0_D2_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+3.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0xD7))&0x80)==0x00)
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "DMA0_D3_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+4.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x117))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x117))&0x80)==0x00)
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "DMA0_D4_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+5.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x157))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x157))&0x80)==0x00)
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "DMA0_D5_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+6.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x197))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x197))&0x80)==0x00)
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "DMA0_D6_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+7.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x1D7))&0x80)==0x00)
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "DMA0_D7_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+8.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x217))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x217))&0x80)==0x00)
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "DMA0_D8_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+9.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x257))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x257))&0x80)==0x00)
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "DMA0_D9_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+10.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x297))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x297))&0x80)==0x00)
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "DMA0_D10_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+11.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x2D7))&0x80)==0x00)
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "DMA0_D11_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+12.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x317))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x317))&0x80)==0x00)
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "DMA0_D12_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+13.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x357))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x357))&0x80)==0x00)
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "DMA0_D13_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+14.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x397))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x397))&0x80)==0x00)
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "DMA0_D14_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)&&(((per.l(ad:0xB4700000+0x04+15.*0x40))&0x30000000)<=0x10000000)
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
textfld " "
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
endif
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x10)==0x00)
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
bitfld.byte 0x00 6. " DES ,Decrement source address" "Incremented,Decremented"
|
|
newline
|
|
bitfld.byte 0x00 5. " US ,Update source address" "Not updated,Updated"
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4700000+0x3D7))&0x80)==0x00)
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
newline
|
|
bitfld.byte 0x00 4. " FBS ,Fixed block source address" "Not fixed,Fixed"
|
|
else
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "DMA0_D15_3,DMA Controller Channel Configuration D Register"
|
|
bitfld.byte 0x00 7. " FS ,Fixed source address" "Incremented,Kept fixed"
|
|
endif
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif !cpuis("S6J320CKSA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J336*")&&!cpuis("S6J337*")
|
|
tree "DMA_E 0--15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DMA0_E0,DMA Controller Channel Configuration E Register Channel 0"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DMA0_E1,DMA Controller Channel Configuration E Register Channel 1"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DMA0_E2,DMA Controller Channel Configuration E Register Channel 2"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA0_E3,DMA Controller Channel Configuration E Register Channel 3"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DMA0_E4,DMA Controller Channel Configuration E Register Channel 4"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "DMA0_E5,DMA Controller Channel Configuration E Register Channel 5"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "DMA0_E6,DMA Controller Channel Configuration E Register Channel 6"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "DMA0_E7,DMA Controller Channel Configuration E Register Channel 7"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "DMA0_E8,DMA Controller Channel Configuration E Register Channel 8"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMA0_E9,DMA Controller Channel Configuration E Register Channel 9"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "DMA0_E10,DMA Controller Channel Configuration E Register Channel 10"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "DMA0_E11,DMA Controller Channel Configuration E Register Channel 11"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DMA0_E12,DMA Controller Channel Configuration E Register Channel 12"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "DMA0_E13,DMA Controller Channel Configuration E Register Channel 13"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "DMA0_E14,DMA Controller Channel Configuration E Register Channel 14"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "DMA0_E15,DMA Controller Channel Configuration E Register Channel 15"
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")||cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 31. " EE ,EE" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 16.--30. 1. " DC ,DC"
|
|
hexmask.long.word 0x00 0.--15. 1. " IC ,IC"
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 15.
|
|
tree "DMA_SASHDW DMA_DASHDW 0-15"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "DMA0_SASHDW0,DMA Controller Channel Configuration Source Address Shadow Register Channel 0"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "DMA0_SASHDW1,DMA Controller Channel Configuration Source Address Shadow Register Channel 1"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "DMA0_SASHDW2,DMA Controller Channel Configuration Source Address Shadow Register Channel 2"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "DMA0_SASHDW3,DMA Controller Channel Configuration Source Address Shadow Register Channel 3"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "DMA0_SASHDW4,DMA Controller Channel Configuration Source Address Shadow Register Channel 4"
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "DMA0_SASHDW5,DMA Controller Channel Configuration Source Address Shadow Register Channel 5"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "DMA0_SASHDW6,DMA Controller Channel Configuration Source Address Shadow Register Channel 6"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW7,DMA Controller Channel Configuration Source Address Shadow Register Channel 7"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "DMA0_SASHDW8,DMA Controller Channel Configuration Source Address Shadow Register Channel 8"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "DMA0_SASHDW9,DMA Controller Channel Configuration Source Address Shadow Register Channel 9"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "DMA0_SASHDW10,DMA Controller Channel Configuration Source Address Shadow Register Channel 10"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW11,DMA Controller Channel Configuration Source Address Shadow Register Channel 11"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "DMA0_SASHDW12,DMA Controller Channel Configuration Source Address Shadow Register Channel 12"
|
|
rgroup.long 0x358++0x03
|
|
line.long 0x00 "DMA0_SASHDW13,DMA Controller Channel Configuration Source Address Shadow Register Channel 13"
|
|
rgroup.long 0x398++0x03
|
|
line.long 0x00 "DMA0_SASHDW14,DMA Controller Channel Configuration Source Address Shadow Register Channel 14"
|
|
rgroup.long 0x3D8++0x03
|
|
line.long 0x00 "DMA0_SASHDW15,DMA Controller Channel Configuration Source Address Shadow Register Channel 15"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DMA0_DASHDW0,DMA Controller Channel Configuration Destination Address Shadow Register Channel 0"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "DMA0_DASHDW1,DMA Controller Channel Configuration Destination Address Shadow Register Channel 1"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "DMA0_DASHDW2,DMA Controller Channel Configuration Destination Address Shadow Register Channel 2"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "DMA0_DASHDW3,DMA Controller Channel Configuration Destination Address Shadow Register Channel 3"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "DMA0_DASHDW4,DMA Controller Channel Configuration Destination Address Shadow Register Channel 4"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "DMA0_DASHDW5,DMA Controller Channel Configuration Destination Address Shadow Register Channel 5"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "DMA0_DASHDW6,DMA Controller Channel Configuration Destination Address Shadow Register Channel 6"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW7,DMA Controller Channel Configuration Destination Address Shadow Register Channel 7"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "DMA0_DASHDW8,DMA Controller Channel Configuration Destination Address Shadow Register Channel 8"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "DMA0_DASHDW9,DMA Controller Channel Configuration Destination Address Shadow Register Channel 9"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "DMA0_DASHDW10,DMA Controller Channel Configuration Destination Address Shadow Register Channel 10"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW11,DMA Controller Channel Configuration Destination Address Shadow Register Channel 11"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "DMA0_DASHDW12,DMA Controller Channel Configuration Destination Address Shadow Register Channel 12"
|
|
rgroup.long 0x35C++0x03
|
|
line.long 0x00 "DMA0_DASHDW13,DMA Controller Channel Configuration Destination Address Shadow Register Channel 13"
|
|
rgroup.long 0x39C++0x03
|
|
line.long 0x00 "DMA0_DASHDW14,DMA Controller Channel Configuration Destination Address Shadow Register Channel 14"
|
|
rgroup.long 0x3DC++0x03
|
|
line.long 0x00 "DMA0_DASHDW15,DMA Controller Channel Configuration Destination Address Shadow Register Channel 15"
|
|
tree.end
|
|
tree "CMICIC"
|
|
sif (cpuis("S6J336*")||cpuis("S6J337*"))
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2028++0x03
|
|
line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x202C++0x03
|
|
line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2030++0x03
|
|
line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2034++0x03
|
|
line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2038++0x03
|
|
line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x203C++0x03
|
|
line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2054++0x03
|
|
line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2058++0x03
|
|
line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x205C++0x03
|
|
line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2060++0x03
|
|
line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2068++0x03
|
|
line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x206C++0x03
|
|
line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2070++0x03
|
|
line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2074++0x03
|
|
line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2078++0x03
|
|
line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x207C++0x03
|
|
line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2080++0x03
|
|
line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2084++0x03
|
|
line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x208C++0x03
|
|
line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2094++0x03
|
|
line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2098++0x03
|
|
line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x209C++0x03
|
|
line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x20FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2110++0x03
|
|
line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2114++0x03
|
|
line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2118++0x03
|
|
line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2120++0x03
|
|
line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2124++0x03
|
|
line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2128++0x03
|
|
line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x212C++0x03
|
|
line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2130++0x03
|
|
line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2134++0x03
|
|
line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2138++0x03
|
|
line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x213C++0x03
|
|
line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2140++0x03
|
|
line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2144++0x03
|
|
line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2148++0x03
|
|
line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x214C++0x03
|
|
line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2150++0x03
|
|
line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2154++0x03
|
|
line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2158++0x03
|
|
line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x215C++0x03
|
|
line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2160++0x03
|
|
line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2164++0x03
|
|
line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2168++0x03
|
|
line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x216C++0x03
|
|
line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2170++0x03
|
|
line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2174++0x03
|
|
line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2178++0x03
|
|
line.long 0x00 "DMA0_CMICIC94,DMA Controller Client Matrix Internal Client Interface Configuration Register 94"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
else
|
|
group.long 0x2020++0x03
|
|
line.long 0x00 "DMA0_CMICIC8,DMA Controller Client Matrix Internal Client Interface Configuration Register 8"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2024++0x03
|
|
line.long 0x00 "DMA0_CMICIC9,DMA Controller Client Matrix Internal Client Interface Configuration Register 9"
|
|
bitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Disabled,Enabled"
|
|
group.long 0x2028++0x03
|
|
line.long 0x00 "DMA0_CMICIC10,DMA Controller Client Matrix Internal Client Interface Configuration Register 10"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x202C++0x03
|
|
line.long 0x00 "DMA0_CMICIC11,DMA Controller Client Matrix Internal Client Interface Configuration Register 11"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2030++0x03
|
|
line.long 0x00 "DMA0_CMICIC12,DMA Controller Client Matrix Internal Client Interface Configuration Register 12"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2034++0x03
|
|
line.long 0x00 "DMA0_CMICIC13,DMA Controller Client Matrix Internal Client Interface Configuration Register 13"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2038++0x03
|
|
line.long 0x00 "DMA0_CMICIC14,DMA Controller Client Matrix Internal Client Interface Configuration Register 14"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x203C++0x03
|
|
line.long 0x00 "DMA0_CMICIC15,DMA Controller Client Matrix Internal Client Interface Configuration Register 15"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "DMA0_CMICIC16,DMA Controller Client Matrix Internal Client Interface Configuration Register 16"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2044++0x03
|
|
line.long 0x00 "DMA0_CMICIC17,DMA Controller Client Matrix Internal Client Interface Configuration Register 17"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2048++0x03
|
|
line.long 0x00 "DMA0_CMICIC18,DMA Controller Client Matrix Internal Client Interface Configuration Register 18"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x204C++0x03
|
|
line.long 0x00 "DMA0_CMICIC19,DMA Controller Client Matrix Internal Client Interface Configuration Register 19"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2050++0x03
|
|
line.long 0x00 "DMA0_CMICIC20,DMA Controller Client Matrix Internal Client Interface Configuration Register 20"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2054++0x03
|
|
line.long 0x00 "DMA0_CMICIC21,DMA Controller Client Matrix Internal Client Interface Configuration Register 21"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2058++0x03
|
|
line.long 0x00 "DMA0_CMICIC22,DMA Controller Client Matrix Internal Client Interface Configuration Register 22"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x205C++0x03
|
|
line.long 0x00 "DMA0_CMICIC23,DMA Controller Client Matrix Internal Client Interface Configuration Register 23"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2060++0x03
|
|
line.long 0x00 "DMA0_CMICIC24,DMA Controller Client Matrix Internal Client Interface Configuration Register 24"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2064++0x03
|
|
line.long 0x00 "DMA0_CMICIC25,DMA Controller Client Matrix Internal Client Interface Configuration Register 25"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2068++0x03
|
|
line.long 0x00 "DMA0_CMICIC26,DMA Controller Client Matrix Internal Client Interface Configuration Register 26"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x206C++0x03
|
|
line.long 0x00 "DMA0_CMICIC27,DMA Controller Client Matrix Internal Client Interface Configuration Register 27"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2070++0x03
|
|
line.long 0x00 "DMA0_CMICIC28,DMA Controller Client Matrix Internal Client Interface Configuration Register 28"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2074++0x03
|
|
line.long 0x00 "DMA0_CMICIC29,DMA Controller Client Matrix Internal Client Interface Configuration Register 29"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2078++0x03
|
|
line.long 0x00 "DMA0_CMICIC30,DMA Controller Client Matrix Internal Client Interface Configuration Register 30"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x207C++0x03
|
|
line.long 0x00 "DMA0_CMICIC31,DMA Controller Client Matrix Internal Client Interface Configuration Register 31"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2080++0x03
|
|
line.long 0x00 "DMA0_CMICIC32,DMA Controller Client Matrix Internal Client Interface Configuration Register 32"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2084++0x03
|
|
line.long 0x00 "DMA0_CMICIC33,DMA Controller Client Matrix Internal Client Interface Configuration Register 33"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2088++0x03
|
|
line.long 0x00 "DMA0_CMICIC34,DMA Controller Client Matrix Internal Client Interface Configuration Register 34"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x208C++0x03
|
|
line.long 0x00 "DMA0_CMICIC35,DMA Controller Client Matrix Internal Client Interface Configuration Register 35"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2090++0x03
|
|
line.long 0x00 "DMA0_CMICIC36,DMA Controller Client Matrix Internal Client Interface Configuration Register 36"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2094++0x03
|
|
line.long 0x00 "DMA0_CMICIC37,DMA Controller Client Matrix Internal Client Interface Configuration Register 37"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2098++0x03
|
|
line.long 0x00 "DMA0_CMICIC38,DMA Controller Client Matrix Internal Client Interface Configuration Register 38"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x209C++0x03
|
|
line.long 0x00 "DMA0_CMICIC39,DMA Controller Client Matrix Internal Client Interface Configuration Register 39"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A0++0x03
|
|
line.long 0x00 "DMA0_CMICIC40,DMA Controller Client Matrix Internal Client Interface Configuration Register 40"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A4++0x03
|
|
line.long 0x00 "DMA0_CMICIC41,DMA Controller Client Matrix Internal Client Interface Configuration Register 41"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20A8++0x03
|
|
line.long 0x00 "DMA0_CMICIC42,DMA Controller Client Matrix Internal Client Interface Configuration Register 42"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20AC++0x03
|
|
line.long 0x00 "DMA0_CMICIC43,DMA Controller Client Matrix Internal Client Interface Configuration Register 43"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B0++0x03
|
|
line.long 0x00 "DMA0_CMICIC44,DMA Controller Client Matrix Internal Client Interface Configuration Register 44"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B4++0x03
|
|
line.long 0x00 "DMA0_CMICIC45,DMA Controller Client Matrix Internal Client Interface Configuration Register 45"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20B8++0x03
|
|
line.long 0x00 "DMA0_CMICIC46,DMA Controller Client Matrix Internal Client Interface Configuration Register 46"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20BC++0x03
|
|
line.long 0x00 "DMA0_CMICIC47,DMA Controller Client Matrix Internal Client Interface Configuration Register 47"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C0++0x03
|
|
line.long 0x00 "DMA0_CMICIC48,DMA Controller Client Matrix Internal Client Interface Configuration Register 48"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C4++0x03
|
|
line.long 0x00 "DMA0_CMICIC49,DMA Controller Client Matrix Internal Client Interface Configuration Register 49"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20C8++0x03
|
|
line.long 0x00 "DMA0_CMICIC50,DMA Controller Client Matrix Internal Client Interface Configuration Register 50"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20CC++0x03
|
|
line.long 0x00 "DMA0_CMICIC51,DMA Controller Client Matrix Internal Client Interface Configuration Register 51"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D0++0x03
|
|
line.long 0x00 "DMA0_CMICIC52,DMA Controller Client Matrix Internal Client Interface Configuration Register 52"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D4++0x03
|
|
line.long 0x00 "DMA0_CMICIC53,DMA Controller Client Matrix Internal Client Interface Configuration Register 53"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20D8++0x03
|
|
line.long 0x00 "DMA0_CMICIC54,DMA Controller Client Matrix Internal Client Interface Configuration Register 54"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20DC++0x03
|
|
line.long 0x00 "DMA0_CMICIC55,DMA Controller Client Matrix Internal Client Interface Configuration Register 55"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E0++0x03
|
|
line.long 0x00 "DMA0_CMICIC56,DMA Controller Client Matrix Internal Client Interface Configuration Register 56"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E4++0x03
|
|
line.long 0x00 "DMA0_CMICIC57,DMA Controller Client Matrix Internal Client Interface Configuration Register 57"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20E8++0x03
|
|
line.long 0x00 "DMA0_CMICIC58,DMA Controller Client Matrix Internal Client Interface Configuration Register 58"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20EC++0x03
|
|
line.long 0x00 "DMA0_CMICIC59,DMA Controller Client Matrix Internal Client Interface Configuration Register 59"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F0++0x03
|
|
line.long 0x00 "DMA0_CMICIC60,DMA Controller Client Matrix Internal Client Interface Configuration Register 60"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F4++0x03
|
|
line.long 0x00 "DMA0_CMICIC61,DMA Controller Client Matrix Internal Client Interface Configuration Register 61"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20F8++0x03
|
|
line.long 0x00 "DMA0_CMICIC62,DMA Controller Client Matrix Internal Client Interface Configuration Register 62"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x20FC++0x03
|
|
line.long 0x00 "DMA0_CMICIC63,DMA Controller Client Matrix Internal Client Interface Configuration Register 63"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2100++0x03
|
|
line.long 0x00 "DMA0_CMICIC64,DMA Controller Client Matrix Internal Client Interface Configuration Register 64"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2104++0x03
|
|
line.long 0x00 "DMA0_CMICIC65,DMA Controller Client Matrix Internal Client Interface Configuration Register 65"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2108++0x03
|
|
line.long 0x00 "DMA0_CMICIC66,DMA Controller Client Matrix Internal Client Interface Configuration Register 66"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x210C++0x03
|
|
line.long 0x00 "DMA0_CMICIC67,DMA Controller Client Matrix Internal Client Interface Configuration Register 67"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2110++0x03
|
|
line.long 0x00 "DMA0_CMICIC68,DMA Controller Client Matrix Internal Client Interface Configuration Register 68"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2114++0x03
|
|
line.long 0x00 "DMA0_CMICIC69,DMA Controller Client Matrix Internal Client Interface Configuration Register 69"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2118++0x03
|
|
line.long 0x00 "DMA0_CMICIC70,DMA Controller Client Matrix Internal Client Interface Configuration Register 70"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x211C++0x03
|
|
line.long 0x00 "DMA0_CMICIC71,DMA Controller Client Matrix Internal Client Interface Configuration Register 71"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2120++0x03
|
|
line.long 0x00 "DMA0_CMICIC72,DMA Controller Client Matrix Internal Client Interface Configuration Register 72"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2124++0x03
|
|
line.long 0x00 "DMA0_CMICIC73,DMA Controller Client Matrix Internal Client Interface Configuration Register 73"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2128++0x03
|
|
line.long 0x00 "DMA0_CMICIC74,DMA Controller Client Matrix Internal Client Interface Configuration Register 74"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x212C++0x03
|
|
line.long 0x00 "DMA0_CMICIC75,DMA Controller Client Matrix Internal Client Interface Configuration Register 75"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2130++0x03
|
|
line.long 0x00 "DMA0_CMICIC76,DMA Controller Client Matrix Internal Client Interface Configuration Register 76"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2134++0x03
|
|
line.long 0x00 "DMA0_CMICIC77,DMA Controller Client Matrix Internal Client Interface Configuration Register 77"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2138++0x03
|
|
line.long 0x00 "DMA0_CMICIC78,DMA Controller Client Matrix Internal Client Interface Configuration Register 78"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x213C++0x03
|
|
line.long 0x00 "DMA0_CMICIC79,DMA Controller Client Matrix Internal Client Interface Configuration Register 79"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2140++0x03
|
|
line.long 0x00 "DMA0_CMICIC80,DMA Controller Client Matrix Internal Client Interface Configuration Register 80"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2144++0x03
|
|
line.long 0x00 "DMA0_CMICIC81,DMA Controller Client Matrix Internal Client Interface Configuration Register 81"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2148++0x03
|
|
line.long 0x00 "DMA0_CMICIC82,DMA Controller Client Matrix Internal Client Interface Configuration Register 82"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x214C++0x03
|
|
line.long 0x00 "DMA0_CMICIC83,DMA Controller Client Matrix Internal Client Interface Configuration Register 83"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2150++0x03
|
|
line.long 0x00 "DMA0_CMICIC84,DMA Controller Client Matrix Internal Client Interface Configuration Register 84"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2154++0x03
|
|
line.long 0x00 "DMA0_CMICIC85,DMA Controller Client Matrix Internal Client Interface Configuration Register 85"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2158++0x03
|
|
line.long 0x00 "DMA0_CMICIC86,DMA Controller Client Matrix Internal Client Interface Configuration Register 86"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x215C++0x03
|
|
line.long 0x00 "DMA0_CMICIC87,DMA Controller Client Matrix Internal Client Interface Configuration Register 87"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2160++0x03
|
|
line.long 0x00 "DMA0_CMICIC88,DMA Controller Client Matrix Internal Client Interface Configuration Register 88"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2164++0x03
|
|
line.long 0x00 "DMA0_CMICIC89,DMA Controller Client Matrix Internal Client Interface Configuration Register 89"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2168++0x03
|
|
line.long 0x00 "DMA0_CMICIC90,DMA Controller Client Matrix Internal Client Interface Configuration Register 90"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x216C++0x03
|
|
line.long 0x00 "DMA0_CMICIC91,DMA Controller Client Matrix Internal Client Interface Configuration Register 91"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2170++0x03
|
|
line.long 0x00 "DMA0_CMICIC92,DMA Controller Client Matrix Internal Client Interface Configuration Register 92"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
group.long 0x2174++0x03
|
|
line.long 0x00 "DMA0_CMICIC93,DMA Controller Client Matrix Internal Client Interface Configuration Register 93"
|
|
rbitfld.long 0x00 27. " BEHSTPACK ,Behavior stop acknowledge" "Output inactive,Connects directly"
|
|
bitfld.long 0x00 25. " BEHREQACK ,Behavior request acknowledge" "Output inactive/Disabled,Connects directly/Enabled"
|
|
endif
|
|
tree.end
|
|
tree "CMCHIC 0-15"
|
|
group.long 0x2800++0x03
|
|
line.long 0x00 "DMA0_CMCHIC0,DMA Controller Client Matrix Channel Interface Configuration Register 0"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2804++0x03
|
|
line.long 0x00 "DMA0_CMCHIC1,DMA Controller Client Matrix Channel Interface Configuration Register 1"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2808++0x03
|
|
line.long 0x00 "DMA0_CMCHIC2,DMA Controller Client Matrix Channel Interface Configuration Register 2"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x280C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC3,DMA Controller Client Matrix Channel Interface Configuration Register 3"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2810++0x03
|
|
line.long 0x00 "DMA0_CMCHIC4,DMA Controller Client Matrix Channel Interface Configuration Register 4"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2814++0x03
|
|
line.long 0x00 "DMA0_CMCHIC5,DMA Controller Client Matrix Channel Interface Configuration Register 5"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2818++0x03
|
|
line.long 0x00 "DMA0_CMCHIC6,DMA Controller Client Matrix Channel Interface Configuration Register 6"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x281C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC7,DMA Controller Client Matrix Channel Interface Configuration Register 7"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2820++0x03
|
|
line.long 0x00 "DMA0_CMCHIC8,DMA Controller Client Matrix Channel Interface Configuration Register 8"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2824++0x03
|
|
line.long 0x00 "DMA0_CMCHIC9,DMA Controller Client Matrix Channel Interface Configuration Register 9"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2828++0x03
|
|
line.long 0x00 "DMA0_CMCHIC10,DMA Controller Client Matrix Channel Interface Configuration Register 10"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x282C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC11,DMA Controller Client Matrix Channel Interface Configuration Register 11"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2830++0x03
|
|
line.long 0x00 "DMA0_CMCHIC12,DMA Controller Client Matrix Channel Interface Configuration Register 12"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2834++0x03
|
|
line.long 0x00 "DMA0_CMCHIC13,DMA Controller Client Matrix Channel Interface Configuration Register 13"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x2838++0x03
|
|
line.long 0x00 "DMA0_CMCHIC14,DMA Controller Client Matrix Channel Interface Configuration Register 14"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
group.long 0x283C++0x03
|
|
line.long 0x00 "DMA0_CMCHIC15,DMA Controller Client Matrix Channel Interface Configuration Register 15"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,Reload event selection replacement" "Disabled,,,,Reload ch. 0,Reload ch. 1,Reload ch. 2,Reload ch. 3,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,BSTART ch. 0,BSTART ch. 1,BSTART ch. 2,BSTART ch. 3,BSTART ch. 4,BSTART ch. 5,BSTART ch. 6,BSTART ch. 7,BSTART ch. 8,BSTART ch. 9,BSTART ch. 10,BSTART ch. 11,BSTART ch. 12,BSTART ch. 13,BSTART ch. 14,BSTART ch. 15,BDONE ch. 0,BDONE ch. 1,BDONE ch. 2,BDONE ch. 3,BDONE ch. 4,BDONE ch. 5,BDONE ch. 6,BDONE ch.7,BDONE ch.8,BDONE ch.9,BDONE ch. 10,BDONE ch. 11,BDONE ch. 12,BDONE ch. 13,BDONE ch. 14,BDONE ch. 15,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,Reload Slot Replacement" "CHCHICRDB0,CHCHICRDB1,CHCHICRDB2,CHCHICRDB3,CHCHICRDB4,CHCHICRDB5,CHCHICRDB6,CHCHICRDB7"
|
|
newline
|
|
sif cpuis("S6J311?HAA")||cpuis("S6J311?JAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,Client interface"
|
|
newline
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,Client interface"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "DMA COMPLEX SUBSYSTEM"
|
|
base ad:0xB4714000
|
|
width 12.
|
|
rgroup.long 0x000++0x07
|
|
line.long 0x00 "ASR0,DMA Additional Control Additional Status Register 0"
|
|
bitfld.long 0x00 0. " HBUSREQ ,HBUSREQ status" "Completed,Started"
|
|
line.long 0x04 "ASR1,DMA Additional Control Additional Status Register 1"
|
|
bitfld.long 0x04 16.--21. " BC_READ ,Block count for reading" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 0.--5. " BC_WRITE ,Block count for writing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x008++0x07
|
|
line.long 0x00 "ASR2,DMA Additional Control Additional Status Register 2"
|
|
bitfld.long 0x00 15. " SELECTED_[15] ,Current selected channel by DMA arbiter 15" "Not selected,Selected"
|
|
bitfld.long 0x00 14. " [14] ,Current selected channel by DMA arbiter 14" "Not selected,Selected"
|
|
bitfld.long 0x00 13. " [13] ,Current selected channel by DMA arbiter 13" "Not selected,Selected"
|
|
bitfld.long 0x00 12. " [12] ,Current selected channel by DMA arbiter 12" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Current selected channel by DMA arbiter 11" "Not selected,Selected"
|
|
bitfld.long 0x00 10. " [10] ,Current selected channel by DMA arbiter 10" "Not selected,Selected"
|
|
bitfld.long 0x00 9. " [9] ,Current selected channel by DMA arbiter 9" "Not selected,Selected"
|
|
bitfld.long 0x00 8. " [8] ,Current selected channel by DMA arbiter 8" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Current selected channel by DMA arbiter 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,Current selected channel by DMA arbiter 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,Current selected channel by DMA arbiter 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,Current selected channel by DMA arbiter 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Current selected channel by DMA arbiter 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,Current selected channel by DMA arbiter 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,Current selected channel by DMA arbiter 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,Current selected channel by DMA arbiter 0" "Not selected,Selected"
|
|
line.long 0x04 "ASR3,DMA Additional Control Additional Status Register 3"
|
|
bitfld.long 0x04 15. " REQ_[15] ,Request bit 15" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [14] ,Request bit 14" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " [13] ,Request bit 13" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [12] ,Request bit 12" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Request bit 11" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [10] ,Request bit 10" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " [9] ,Request bit 9" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [8] ,Request bit 8" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Request bit 7" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [6] ,Request bit 6" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " [5] ,Request bit 5" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [4] ,Request bit 4" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Request bit 3" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [2] ,Request bit 2" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " [1] ,Request bit 1" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [0] ,Request bit 0" "Not requested,Requested"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ASR4,DMA Additional Control Additional Status Register 4"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 0"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "ASR5,DMA Additional Control Additional Status Register 5"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 1"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ASR6,DMA Additional Control Additional Status Register 6"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 2"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ASR7,DMA Additional Control Additional Status Register 7"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 3"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ASR8,DMA Additional Control Additional Status Register 8"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 4"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ASR9,DMA Additional Control Additional Status Register 9"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 5"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "ASR10,DMA Additional Control Additional Status Register 10"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 6"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "ASR11,DMA Additional Control Additional Status Register 11"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 7"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ASR12,DMA Additional Control Additional Status Register 12"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 8"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "ASR13,DMA Additional Control Additional Status Register 13"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 9"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ASR14,DMA Additional Control Additional Status Register 14"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 10"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "ASR15,DMA Additional Control Additional Status Register 15"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 11"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ASR16,DMA Additional Control Additional Status Register 16"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 12"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "ASR17,DMA Additional Control Additional Status Register 17"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 13"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ASR18,DMA Additional Control Additional Status Register 18"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 14"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ASR19,DMA Additional Control Additional Status Register 19"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TC_SHDW ,Number of resting of transfers in DMA channel 15"
|
|
newline
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CMCHICRDB0,DMA Additional Control CMCHIC Reload Data Bank Register 0"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CMCHICRDB1,DMA Additional Control CMCHIC Reload Data Bank Register 1"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CMCHICRDB2,DMA Additional Control CMCHIC Reload Data Bank Register 2"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CMCHICRDB3,DMA Additional Control CMCHIC Reload Data Bank Register 3"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CMCHICRDB4,DMA Additional Control CMCHIC Reload Data Bank Register 4"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CMCHICRDB5,DMA Additional Control CMCHIC Reload Data Bank Register 5"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CMCHICRDB6,DMA Additional Control CMCHIC Reload Data Bank Register 6"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CMCHICRDB7,DMA Additional Control CMCHIC Reload Data Bank Register 7"
|
|
bitfld.long 0x00 24.--29. " RLESEL ,RLESEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--18. " RLSLOT ,RLSLOT" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hexmask.long.byte 0x00 0.--7. 1. " CI ,CI"
|
|
else
|
|
hexmask.long.word 0x00 0.--8. 1. " CI ,CI"
|
|
endif
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "RTTSR,DMA Additional Control Reload Timer Trigger Select Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. " RLT3TS ,Reload timer 3 trigger select"
|
|
hexmask.long.byte 0x00 16.--22. 1. " RLT2TS ,Reload timer 2 trigger select"
|
|
hexmask.long.byte 0x00 8.--14. 1. " RLT1TS ,Reload timer 1 trigger select"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RLT0TS ,Reload timer 0 trigger select"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "RTSSSR,DMA Additional Control Reload Timer Synchronous Software Start Register"
|
|
bitfld.long 0x00 3. " SSSR3 ,Synchronous software start register" "No effect,Give 0->1->0 pulse"
|
|
bitfld.long 0x00 2. " SSSR2 ,Synchronous software start register" "No effect,Give 0->1->0 pulse"
|
|
bitfld.long 0x00 1. " SSSR1 ,Synchronous software start register" "No effect,Give 0->1->0 pulse"
|
|
bitfld.long 0x00 0. " SSSR0 ,Synchronous software start register" "No effect,Give 0->1->0 pulse"
|
|
width 0x0B
|
|
tree "DMAA0_RLT0"
|
|
base ad:0xB4714800
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT0_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714800+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4714800+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT0_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT0_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAA0_RLT1"
|
|
base ad:0xB4714820
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT1_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714820+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4714820+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT1_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT1_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAA0_RLT2"
|
|
base ad:0xB4714840
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT2_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714840+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4714840+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT2_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT2_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAA0_RLT3"
|
|
base ad:0xB4714860
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT3_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4714860+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4714860+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT3_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT3_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "MPUH (Memory Protection Unit for the AMBA Advanced High Speed Bus)"
|
|
base ad:0xB4710000
|
|
width 15.
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x10000)
|
|
group.long 0x000++0x03
|
|
line.long 0x00 "MPUH0_CTRL0,MPU16 AHB Control Register"
|
|
rbitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged mode,Privileged mode"
|
|
rbitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x000++0x03
|
|
line.long 0x00 "MPUH0_CTRL0,MPU16 AHB Control Register"
|
|
bitfld.long 0x00 24.--26. " AP ,Access permissions for background region" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " MPUENC ,MPU AHB enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 16. " MPUEN ,MPU AHB enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PROT ,Privileged mode attribute" "Non-privileged mode,Privileged mode"
|
|
bitfld.long 0x00 11. " POEN ,Privileged mode overwrite feature enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " LST ,MPU lock status" "Unlocked,Locked"
|
|
newline
|
|
bitfld.long 0x00 1. " NMICL ,NMI interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 0. " NMI ,NMI interrupt flag" "Not occurred,Occurred"
|
|
endif
|
|
group.long 0x004++0x03
|
|
line.long 0x00 "MPUH0_NMIEN,MPU16 AHB NMI Enable Register"
|
|
bitfld.long 0x00 0. " NMIEN ,NMI interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x008++0x07
|
|
line.long 0x00 "MPUH0_MERRC,MPU16 AHB Memory Error Control Register"
|
|
bitfld.long 0x00 1. " HPROT ,AHB transfer privileged mode" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " HWRITE ,AHB transfer mode" "Not detected,Detected"
|
|
line.long 0x04 "MPUH0_MERRA,MPU AHB Memory Error Address Register"
|
|
newline
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x10))&0x01)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPUH0_CTRL1,MPU16 AHB Region Control Register 1"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MPUH0_CTRL1,MPU16 AHB Region Control Register 1"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x1C))&0x01)==0x01)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MPUH0_CTRL2,MPU16 AHB Region Control Register 2"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MPUH0_CTRL2,MPU16 AHB Region Control Register 2"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x28))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MPUH0_CTRL3,MPU16 AHB Region Control Register 3"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MPUH0_CTRL3,MPU16 AHB Region Control Register 3"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x34))&0x01)==0x01)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MPUH0_CTRL4,MPU16 AHB Region Control Register 4"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "MPUH0_CTRL4,MPU16 AHB Region Control Register 4"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x40))&0x01)==0x01)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MPUH0_CTRL5,MPU16 AHB Region Control Register 5"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MPUH0_CTRL5,MPU16 AHB Region Control Register 5"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x4C))&0x01)==0x01)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MPUH0_CTRL6,MPU16 AHB Region Control Register 6"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MPUH0_CTRL6,MPU16 AHB Region Control Register 6"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x58))&0x01)==0x01)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MPUH0_CTRL7,MPU16 AHB Region Control Register 7"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MPUH0_CTRL7,MPU16 AHB Region Control Register 7"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x64))&0x01)==0x01)
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MPUH0_CTRL8,MPU16 AHB Region Control Register 8"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MPUH0_CTRL8,MPU16 AHB Region Control Register 8"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x110))&0x01)==0x01)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPUH0_CTRL9,MPU16 AHB Region Control Register 9"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MPUH0_CTRL9,MPU16 AHB Region Control Register 9"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x11C))&0x01)==0x01)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPUH0_CTRL10,MPU16 AHB Region Control Register 10"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MPUH0_CTRL10,MPU16 AHB Region Control Register 10"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x128))&0x01)==0x01)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPUH0_CTRL11,MPU16 AHB Region Control Register 11"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "MPUH0_CTRL11,MPU16 AHB Region Control Register 11"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x134))&0x01)==0x01)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPUH0_CTRL12,MPU16 AHB Region Control Register 12"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "MPUH0_CTRL12,MPU16 AHB Region Control Register 12"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x140))&0x01)==0x01)
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPUH0_CTRL13,MPU16 AHB Region Control Register 13"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MPUH0_CTRL13,MPU16 AHB Region Control Register 13"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x14C))&0x01)==0x01)
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPUH0_CTRL14,MPU16 AHB Region Control Register 14"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "MPUH0_CTRL14,MPU16 AHB Region Control Register 14"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x158))&0x01)==0x01)
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPUH0_CTRL15,MPU16 AHB Region Control Register 15"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "MPUH0_CTRL15,MPU16 AHB Region Control Register 15"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0xB4710000+0x164))&0x01)==0x01)
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPUH0_CTRL16,MPU16 AHB Region Control Register 16"
|
|
rbitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "MPUH0_CTRL16,MPU16 AHB Region Control Register 16"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "MPUH0_CTRL1_0,MPU16 AHB Region Control Register 1"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL1_1,MPU16 AHB Region Control Register 1"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL2_0,MPU16 AHB Region Control Register 2"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL2_1,MPU16 AHB Region Control Register 2"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "MPUH0_CTRL3_0,MPU16 AHB Region Control Register 3"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL3_1,MPU16 AHB Region Control Register 3"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "MPUH0_CTRL4_0,MPU16 AHB Region Control Register 4"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL4_1,MPU16 AHB Region Control Register 4"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x40++0x01
|
|
line.byte 0x00 "MPUH0_CTRL5_0,MPU16 AHB Region Control Register 5"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL5_1,MPU16 AHB Region Control Register 5"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x4C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL6_0,MPU16 AHB Region Control Register 6"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL6_1,MPU16 AHB Region Control Register 6"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "MPUH0_CTRL7_0,MPU16 AHB Region Control Register 7"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL7_1,MPU16 AHB Region Control Register 7"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x64++0x01
|
|
line.byte 0x00 "MPUH0_CTRL8_0,MPU16 AHB Region Control Register 8"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL8_1,MPU16 AHB Region Control Register 8"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x110++0x01
|
|
line.byte 0x00 "MPUH0_CTRL9_0,MPU16 AHB Region Control Register 9"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL9_1,MPU16 AHB Region Control Register 9"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x11C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL10_0,MPU16 AHB Region Control Register 10"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL10_1,MPU16 AHB Region Control Register 10"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x128++0x01
|
|
line.byte 0x00 "MPUH0_CTRL11_0,MPU16 AHB Region Control Register 11"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL11_1,MPU16 AHB Region Control Register 11"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x134++0x01
|
|
line.byte 0x00 "MPUH0_CTRL12_0,MPU16 AHB Region Control Register 12"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL12_1,MPU16 AHB Region Control Register 12"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x140++0x01
|
|
line.byte 0x00 "MPUH0_CTRL13_0,MPU16 AHB Region Control Register 13"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL13_1,MPU16 AHB Region Control Register 13"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x14C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL14_0,MPU16 AHB Region Control Register 14"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL14_1,MPU16 AHB Region Control Register 14"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x158++0x01
|
|
line.byte 0x00 "MPUH0_CTRL15_0,MPU16 AHB Region Control Register 15"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL15_1,MPU16 AHB Region Control Register 15"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x164++0x01
|
|
line.byte 0x00 "MPUH0_CTRL16_0,MPU16 AHB Region Control Register 16"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL16_1,MPU16 AHB Region Control Register 16"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "MPUH0_CTRL1_1,MPU16 AHB Region Control Register 1"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL1_2,MPU16 AHB Region Control Register 1"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x1C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL2_1,MPU16 AHB Region Control Register 2"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL2_2,MPU16 AHB Region Control Register 2"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x28++0x01
|
|
line.byte 0x00 "MPUH0_CTRL3_1,MPU16 AHB Region Control Register 3"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL3_2,MPU16 AHB Region Control Register 3"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x34++0x01
|
|
line.byte 0x00 "MPUH0_CTRL4_1,MPU16 AHB Region Control Register 4"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL4_2,MPU16 AHB Region Control Register 4"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x40++0x01
|
|
line.byte 0x00 "MPUH0_CTRL5_1,MPU16 AHB Region Control Register 5"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL5_2,MPU16 AHB Region Control Register 5"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x4C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL6_1,MPU16 AHB Region Control Register 6"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL6_2,MPU16 AHB Region Control Register 6"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x58++0x01
|
|
line.byte 0x00 "MPUH0_CTRL7_1,MPU16 AHB Region Control Register 7"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL7_2,MPU16 AHB Region Control Register 7"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x64++0x01
|
|
line.byte 0x00 "MPUH0_CTRL8_1,MPU16 AHB Region Control Register 8"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL8_2,MPU16 AHB Region Control Register 8"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x110++0x01
|
|
line.byte 0x00 "MPUH0_CTRL9_1,MPU16 AHB Region Control Register 9"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL9_2,MPU16 AHB Region Control Register 9"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x11C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL10_1,MPU16 AHB Region Control Register 10"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL10_2,MPU16 AHB Region Control Register 10"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x128++0x01
|
|
line.byte 0x00 "MPUH0_CTRL11_1,MPU16 AHB Region Control Register 11"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL11_2,MPU16 AHB Region Control Register 11"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x134++0x01
|
|
line.byte 0x00 "MPUH0_CTRL12_1,MPU16 AHB Region Control Register 12"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL12_2,MPU16 AHB Region Control Register 12"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x140++0x01
|
|
line.byte 0x00 "MPUH0_CTRL13_1,MPU16 AHB Region Control Register 13"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL13_2,MPU16 AHB Region Control Register 13"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x14C++0x01
|
|
line.byte 0x00 "MPUH0_CTRL14_1,MPU16 AHB Region Control Register 14"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL14_2,MPU16 AHB Region Control Register 14"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x158++0x01
|
|
line.byte 0x00 "MPUH0_CTRL15_1,MPU16 AHB Region Control Register 15"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL15_2,MPU16 AHB Region Control Register 15"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
group.byte 0x164++0x01
|
|
line.byte 0x00 "MPUH0_CTRL16_1,MPU16 AHB Region Control Register 16"
|
|
bitfld.byte 0x00 1. " MPUENC ,Enable control bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " MPUEN ,Enable status" "Disabled,Enabled"
|
|
line.byte 0x01 "MPUH0_CTRL16_2,MPU16 AHB Region Control Register 16"
|
|
bitfld.byte 0x01 0.--2. " AP ,Access permission" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x14-0x04))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x14-0x04))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MPUH0_SADDR1,MPU16 AHB Start Address Register 1"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x20-0x04))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x20-0x04))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "MPUH0_SADDR2,MPU16 AHB Start Address Register 2"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x2C-0x04))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x2C-0x04))&0x01)==0x00)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3"
|
|
else
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "MPUH0_SADDR3,MPU16 AHB Start Address Register 3"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x38-0x04))&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x38-0x04))&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "MPUH0_SADDR4,MPU16 AHB Start Address Register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x44-0x04))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x44-0x04))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "MPUH0_SADDR5,MPU16 AHB Start Address Register 5"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x50-0x04))&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x50-0x04))&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MPUH0_SADDR6,MPU16 AHB Start Address Register 6"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x5C-0x04))&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x5C-0x04))&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MPUH0_SADDR7,MPU16 AHB Start Address Register 7"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x68-0x04))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x68-0x04))&0x01)==0x00)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8"
|
|
else
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "MPUH0_SADDR8,MPU16 AHB Start Address Register 8"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x114-0x04))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9"
|
|
else
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x114-0x04))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9"
|
|
else
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "MPUH0_SADDR9,MPU16 AHB Start Address Register 9"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x120-0x04))&0x01)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10"
|
|
else
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x120-0x04))&0x01)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10"
|
|
else
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "MPUH0_SADDR10,MPU16 AHB Start Address Register 10"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x12C-0x04))&0x01)==0x00)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11"
|
|
else
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x12C-0x04))&0x01)==0x00)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11"
|
|
else
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "MPUH0_SADDR11,MPU16 AHB Start Address Register 11"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x138-0x04))&0x01)==0x00)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12"
|
|
else
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x138-0x04))&0x01)==0x00)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12"
|
|
else
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "MPUH0_SADDR12,MPU16 AHB Start Address Register 12"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x144-0x04))&0x01)==0x00)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13"
|
|
else
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x144-0x04))&0x01)==0x00)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13"
|
|
else
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "MPUH0_SADDR13,MPU16 AHB Start Address Register 13"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x150-0x04))&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x150-0x04))&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "MPUH0_SADDR14,MPU16 AHB Start Address Register 14"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x15C-0x04))&0x01)==0x00)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15"
|
|
else
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x15C-0x04))&0x01)==0x00)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15"
|
|
else
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "MPUH0_SADDR15,MPU16 AHB Start Address Register 15"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x168-0x04))&0x01)==0x00)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16"
|
|
else
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x168-0x04))&0x01)==0x00)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16"
|
|
else
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "MPUH0_SADDR16,MPU16 AHB Start Address Register 16"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x18-0x08))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x18-0x08))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MPUH0_EADDR1,MPU16 AHB End Address Register 1"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x24-0x08))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x24-0x08))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "MPUH0_EADDR2,MPU16 AHB End Address Register 2"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x30-0x08))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x30-0x08))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "MPUH0_EADDR3,MPU16 AHB End Address Register 3"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x3C-0x08))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x3C-0x08))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "MPUH0_EADDR4,MPU16 AHB End Address Register 4"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x48-0x08))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x48-0x08))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MPUH0_EADDR5,MPU16 AHB End Address Register 5"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x54-0x08))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x54-0x08))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MPUH0_EADDR6,MPU16 AHB End Address Register 6"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x60-0x08))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x60-0x08))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "MPUH0_EADDR7,MPU16 AHB End Address Register 7"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x6C-0x08))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x6C-0x08))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "MPUH0_EADDR8,MPU16 AHB End Address Register 8"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x118-0x08))&0x01)==0x00)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9"
|
|
else
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x118-0x08))&0x01)==0x00)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9"
|
|
else
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "MPUH0_EADDR9,MPU16 AHB End Address Register 9"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x124-0x08))&0x01)==0x00)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10"
|
|
else
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x124-0x08))&0x01)==0x00)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10"
|
|
else
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "MPUH0_EADDR10,MPU16 AHB End Address Register 10"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x130-0x08))&0x01)==0x00)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x130-0x08))&0x01)==0x00)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "MPUH0_EADDR11,MPU16 AHB End Address Register 11"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x13C-0x08))&0x01)==0x00)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12"
|
|
else
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x13C-0x08))&0x01)==0x00)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12"
|
|
else
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "MPUH0_EADDR12,MPU16 AHB End Address Register 12"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x148-0x08))&0x01)==0x00)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13"
|
|
else
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x148-0x08))&0x01)==0x00)
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13"
|
|
else
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "MPUH0_EADDR13,MPU16 AHB End Address Register 13"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x154-0x08))&0x01)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x154-0x08))&0x01)==0x00)
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14"
|
|
else
|
|
rgroup.long 0x154++0x03
|
|
line.long 0x00 "MPUH0_EADDR14,MPU16 AHB End Address Register 14"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x160-0x08))&0x01)==0x00)
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15"
|
|
else
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x160-0x08))&0x01)==0x00)
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15"
|
|
else
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "MPUH0_EADDR15,MPU16 AHB End Address Register 15"
|
|
endif
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.l(ad:0xB4710000+0x16C-0x08))&0x01)==0x00)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16"
|
|
else
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4710000+0x00))&0x10000)==0x00)||(((per.b(ad:0xB4710000+0x16C-0x08))&0x01)==0x00)
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16"
|
|
else
|
|
rgroup.long 0x16C++0x03
|
|
line.long 0x00 "MPUH0_EADDR16,MPU16 AHB End Address Register 16"
|
|
endif
|
|
endif
|
|
group.long 0x070++0x03
|
|
line.long 0x00 "MPUH0_UNLOCK,MPU16 AHB Unlock Register"
|
|
rgroup.long 0x074++0x03
|
|
line.long 0x00 "MPUH0_MID,MPU16 AHB Module ID Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CANFD (CAN FD CONTROLER)"
|
|
tree "CPG_CANFD0"
|
|
base ad:0xB4900000
|
|
width 8.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--15. " MON ,Time Stamp Month" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 0.--7. " DAY ,Time Stamp Day" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "ENDN,Endian Register"
|
|
sif (cpu()!="S6J323CKS")&&(cpu()!="S6J323CLS")&&(cpu()!="S6J324CKS")&&(cpu()!="S6J324CLS")&&(cpu()!="S6J325CKS")&&(cpu()!="S6J325CLS")&&(cpu()!="S6J326CKS")&&(cpu()!="S6J326CLS")&&(!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CUST,CUST"
|
|
endif
|
|
if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FBTP,Fast Bit Timing & Prescaler Register"
|
|
bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " TDC ,Transceiver delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " FSJW ,Fast Re Synchronization Jump Width" "0,1,2,3"
|
|
else
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "FBTP,Fast Bit Timing & Prescaler Register"
|
|
bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " TDC ,Transceiver delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " FSJW ,Fast Re Synchronization Jump Width" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB4900000+0x18))&0x80)==0x80)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 8.--13. " TDCV ,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "Con. by CAN,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 8.--13. " TDCV ,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "Con. by CAN,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")
|
|
if (((per.l(ad:0xB4900000+0x18))&0x03)==0x03)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
endif
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
endif
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
bitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
elif (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
rbitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
rbitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
rbitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
rbitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
rbitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
rbitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
endif
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "BTP,Bit Timing & Prescaler Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler"
|
|
bitfld.long 0x00 8.--13. " TSEG1 ,Time Segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SJW ,Re Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "BTP,Bit Timing & Prescaler Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler"
|
|
bitfld.long 0x00 8.--13. " TSEG1 ,Time Segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SJW ,Re Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],CAN FD,0"
|
|
else
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],CAN FD,0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],,0"
|
|
else
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],,0"
|
|
endif
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp Counter"
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "Continuous,Tx FIFO,Rx FIFO 0,Rx FIFO 1"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "Continuous,Tx FIFO,Rx FIFO 0,Rx FIFO 1"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout Counter"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "ECR,Error Counter Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "PSR,Protocol Status Register"
|
|
in
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 31. " STE ,Stuff error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " FOE ,Format error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " ACKE ,Acknowledge error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " BE ,Bit error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " CRCE ,CRC error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " BO ,Bus_Off status" "Unchanged,Changed"
|
|
eventfld.long 0x00 24. " EW ,Warning status" "Unchanged,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 23. " EP ,Error passive" "Unchanged,Changed"
|
|
eventfld.long 0x00 22. " ELO ,Error logging overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " BEC ,Bit error corrected" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " DRX ,Message stored to dedicated Rx buffer" "Updated,Stored"
|
|
eventfld.long 0x00 18. " TOO ,Timeout occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " MRAF ,Message RAM Access failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " TEFL ,Tx event FIFO element lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " TEFF ,Tx event FIFO full" "Not full,Full"
|
|
eventfld.long 0x00 13. " TEFW ,Tx event FIFO watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 12. " TEFN ,Tx event FIFO new entry" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " TFE ,Tx FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not finished,Finished"
|
|
eventfld.long 0x00 9. " TC ,Transmission competed" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " HPM ,High priority message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 7. " RF1L ,Rx FIFO 1 message lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "Not full,Full"
|
|
eventfld.long 0x00 5. " RF1W ,Rx FIFO 1 watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 4. " RF1N ,FIFO 1 new message" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "Not full,Full"
|
|
eventfld.long 0x00 1. " RF0W ,Rx FIFO 0 watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 0. " RF0N ,Rx FIFO 0 new message" "Not occurred,Occurred"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "IE,Interrupt enable"
|
|
bitfld.long 0x00 31. " STEE ,Stuff error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FOEE ,Format error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ACKEE ,Acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BEE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CRCEE ,CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BOE ,Bus_Off status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EWE ,Warning status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPE ,Error passive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ELOE ,Error logging overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BEUE ,Bit error uncorrected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BECE ,Bit error corrected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DRXE ,Message stored to dedicated Rx buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TOOE ,Timeout occurred interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MRAFE ,Message RAM Access failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TSWE ,Timestamp wraparound interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEFLE ,Tx event FIFO element lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TEFFE ,Tx event FIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TEFWE ,Tx event FIFO watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TEFNE ,Tx event FIFO new entry interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFEE ,Tx FIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TCFE ,Transmission cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TCE ,Transmission competed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HPME ,High priority message interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RF1LE ,Rx FIFO 1 message lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RF1FE ,Rx FIFO 1 Full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RF1WE ,Rx FIFO 1 watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RF1NE ,FIFO 1 new message interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RF0LE ,Rx FIFO 0 Message lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RF0FE ,Rx FIFO 0 Full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RF0WE ,Rx FIFO 0 watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RF0NE ,Rx FIFO 0 new message interrupt enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "ILS,Interrupt line select"
|
|
bitfld.long 0x00 31. " STEL ,Stuff error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 30. " FOEL ,Format error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 29. " ACKEL ,Acknowledge error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 28. " BEL ,Bit error interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CRCEL ,CRC error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 25. " BOL ,Bus_Off status interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 24. " EWL ,Warning status interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPL ,Error passive interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 22. " ELOL ,Error logging overflow interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 20. " BECL ,Bit error corrected interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DRXL ,Message stored to dedicated Rx buffer interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 18. " TOOL ,Timeout occurred interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 17. " MRAFL ,Message RAM Access failure interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEFLL ,Tx event FIFO element lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 14. " TEFFL ,Tx event FIFO full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 13. " TEFWL ,Tx event FIFO watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 12. " TEFNL ,Tx event FIFO new entry interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFEL ,Tx FIFO empty interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 9. " TCL ,Transmission competed interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 8. " HPML ,High priority message interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RF1LL ,Rx FIFO 1 message lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 6. " RF1FL ,Rx FIFO 1 Full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 5. " RF1WL ,Rx FIFO 1 watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 4. " RF1NL ,FIFO 1 new message interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RF0LL ,Rx FIFO 0 Message lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 2. " RF0FL ,Rx FIFO 0 Full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 1. " RF0WL ,Rx FIFO 0 watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 0. " RF0NL ,Rx FIFO 0 new message interrupt line" "Canfd_int0,Canfd_int1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "ILE,Interrupt line enable"
|
|
bitfld.long 0x00 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "SIDFC,Standard ID Filter configuration"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LSS ,List size standard"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLSSA ,Filter list standard start address"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "XIDFC,Extended ID filter configuration"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LSE ,List size extended"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLESA ,Filter list extended start address"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask"
|
|
else
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,,"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,,"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "SIDFC,Standard ID Filter configuration"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LSS ,List size standard"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLSSA ,Filter list standard start address"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "XIDFC,Extended ID filter configuration"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LSE ,List size extended"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLESA ,Filter list extended start address"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask"
|
|
endif
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "HPMS,High priority message status"
|
|
bitfld.long 0x00 15. " FLST ,Filter List" "Standard,Extended"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index"
|
|
bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No Rx FIFO,Rx FIFO msg. lost,Stored in FIFO 0,Stored in FIFO 1"
|
|
bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline ""
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "NDAT1,New Data 1"
|
|
eventfld.long 0x00 31. " ND_[31] ,New Data_31" "Not updated,Updated"
|
|
eventfld.long 0x00 30. " [30] ,New Data_30" "Not updated,Updated"
|
|
eventfld.long 0x00 29. " [29] ,New Data_29" "Not updated,Updated"
|
|
eventfld.long 0x00 28. " [28] ,New Data_28" "Not updated,Updated"
|
|
eventfld.long 0x00 27. " [27] ,New Data_27" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 26. " [26] ,New Data_26" "Not updated,Updated"
|
|
eventfld.long 0x00 25. " [25] ,New Data_25" "Not updated,Updated"
|
|
eventfld.long 0x00 24. " [24] ,New Data_24" "Not updated,Updated"
|
|
eventfld.long 0x00 23. " [23] ,New Data_23" "Not updated,Updated"
|
|
eventfld.long 0x00 22. " [22] ,New Data_22" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 21. " [21] ,New Data_21" "Not updated,Updated"
|
|
eventfld.long 0x00 20. " [20] ,New Data_20" "Not updated,Updated"
|
|
eventfld.long 0x00 19. " [19] ,New Data_19" "Not updated,Updated"
|
|
eventfld.long 0x00 18. " [18] ,New Data_18" "Not updated,Updated"
|
|
eventfld.long 0x00 17. " [17] ,New Data_17" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [16] ,New Data_16" "Not updated,Updated"
|
|
eventfld.long 0x00 15. " [15] ,New Data_15" "Not updated,Updated"
|
|
eventfld.long 0x00 14. " [14] ,New Data_14" "Not updated,Updated"
|
|
eventfld.long 0x00 13. " [13] ,New Data_13" "Not updated,Updated"
|
|
eventfld.long 0x00 12. " [12] ,New Data_12" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,New Data_11" "Not updated,Updated"
|
|
eventfld.long 0x00 10. " [10] ,New Data_10" "Not updated,Updated"
|
|
eventfld.long 0x00 9. " [9] ,New Data_9" "Not updated,Updated"
|
|
eventfld.long 0x00 8. " [8] ,New Data_8" "Not updated,Updated"
|
|
eventfld.long 0x00 7. " [7] ,New Data_7" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [6] ,New Data_6" "Not updated,Updated"
|
|
eventfld.long 0x00 5. " [5] ,New Data_5" "Not updated,Updated"
|
|
eventfld.long 0x00 4. " [4] ,New Data_4" "Not updated,Updated"
|
|
eventfld.long 0x00 3. " [3] ,New Data_3" "Not updated,Updated"
|
|
eventfld.long 0x00 2. " [2] ,New Data_2" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,New Data_1" "Not updated,Updated"
|
|
eventfld.long 0x00 0. " [0] ,New Data_0" "Not updated,Updated"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "NDAT2,New Data 2"
|
|
eventfld.long 0x00 31. " ND_[63] ,New Data_63" "Not updated,Updated"
|
|
eventfld.long 0x00 30. " [62] ,New Data_62" "Not updated,Updated"
|
|
eventfld.long 0x00 29. " [61] ,New Data_61" "Not updated,Updated"
|
|
eventfld.long 0x00 28. " [60] ,New Data_60" "Not updated,Updated"
|
|
eventfld.long 0x00 27. " [59] ,New Data_59" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 26. " [58] ,New Data_58" "Not updated,Updated"
|
|
eventfld.long 0x00 25. " [57] ,New Data_57" "Not updated,Updated"
|
|
eventfld.long 0x00 24. " [56] ,New Data_56" "Not updated,Updated"
|
|
eventfld.long 0x00 23. " [55] ,New Data_55" "Not updated,Updated"
|
|
eventfld.long 0x00 22. " [54] ,New Data_54" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 21. " [53] ,New Data_53" "Not updated,Updated"
|
|
eventfld.long 0x00 20. " [52] ,New Data_52" "Not updated,Updated"
|
|
eventfld.long 0x00 19. " [51] ,New Data_51" "Not updated,Updated"
|
|
eventfld.long 0x00 18. " [50] ,New Data_50" "Not updated,Updated"
|
|
eventfld.long 0x00 17. " [49] ,New Data_49" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [48] ,New Data_48" "Not updated,Updated"
|
|
eventfld.long 0x00 15. " [47] ,New Data_47" "Not updated,Updated"
|
|
eventfld.long 0x00 14. " [46] ,New Data_46" "Not updated,Updated"
|
|
eventfld.long 0x00 13. " [45] ,New Data_45" "Not updated,Updated"
|
|
eventfld.long 0x00 12. " [44] ,New Data_44" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [43] ,New Data_43" "Not updated,Updated"
|
|
eventfld.long 0x00 10. " [42] ,New Data_42" "Not updated,Updated"
|
|
eventfld.long 0x00 9. " [41] ,New Data_41" "Not updated,Updated"
|
|
eventfld.long 0x00 8. " [40] ,New Data_40" "Not updated,Updated"
|
|
eventfld.long 0x00 7. " [39] ,New Data_39" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [38] ,New Data_38" "Not updated,Updated"
|
|
eventfld.long 0x00 5. " [37] ,New Data_37" "Not updated,Updated"
|
|
eventfld.long 0x00 4. " [36] ,New Data_36" "Not updated,Updated"
|
|
eventfld.long 0x00 3. " [35] ,New Data_35" "Not updated,Updated"
|
|
eventfld.long 0x00 2. " [34] ,New Data_34" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [33] ,New Data_33" "Not updated,Updated"
|
|
eventfld.long 0x00 0. " [32] ,New Data_32" "Not updated,Updated"
|
|
textline ""
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F0S ,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address"
|
|
else
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F0S ,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address"
|
|
endif
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x00 "RXF0S,Rx FIFO Status"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 message lost" "No msg. lost,Message lost"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 FUll" "Not Full,Full"
|
|
bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx 0 Fill level"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,Rx Buffer Start Address"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
else
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x00 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,Rx Buffer Start Address"
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
endif
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "Idle,A received,A B received,A B C received"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 MEssage Lost" "No msg. lost,Message lost"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 Fill level"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "RXESC,Rx Buffer/FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx buffer data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "Tx FIFO,Tx Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx Buffers Start Address"
|
|
else
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x00 "RXESC,Rx Buffer/FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx buffer data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x00 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "Tx FIFO,Tx Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx Buffers Start Address"
|
|
endif
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x00 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x00 21. " TFQF ,FIFO/Queue Full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " TFQPI ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " TFFL ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
else
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
endif
|
|
textline ""
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending"
|
|
bitfld.long 0x00 31. " TRP_[31] ,Transmission Request Pending 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Transmission Request Pending 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Transmission Request Pending 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Transmission Request Pending 28" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Transmission Request Pending 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission Request Pending 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Transmission Request Pending 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Transmission Request Pending 24" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Transmission Request Pending 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Transmission Request Pending 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission Request Pending 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Transmission Request Pending 20" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Transmission Request Pending 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Transmission Request Pending 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Transmission Request Pending 17" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission Request Pending 16" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Transmission Request Pending 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Transmission Request Pending 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Transmission Request Pending 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Transmission Request Pending 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission Request Pending 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Transmission Request Pending 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Transmission Request Pending 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Transmission Request Pending 8" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Transmission Request Pending 7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission Request Pending 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Transmission Request Pending 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Transmission Request Pending 4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Transmission Request Pending 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Transmission Request Pending 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission Request Pending 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Transmission Request Pending 0" "Not pending,Pending"
|
|
textline ""
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TXBAR,Tx Buffer Add request"
|
|
bitfld.long 0x00 31. " AR_[31] ,Add Request 31" "Not added,Added"
|
|
bitfld.long 0x00 30. " [30] ,Add Request 30" "Not added,Added"
|
|
bitfld.long 0x00 29. " [29] ,Add Request 29" "Not added,Added"
|
|
bitfld.long 0x00 28. " [28] ,Add Request 28" "Not added,Added"
|
|
bitfld.long 0x00 27. " [27] ,Add Request 27" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Add Request 26" "Not added,Added"
|
|
bitfld.long 0x00 25. " [25] ,Add Request 25" "Not added,Added"
|
|
bitfld.long 0x00 24. " [24] ,Add Request 24" "Not added,Added"
|
|
bitfld.long 0x00 23. " [23] ,Add Request 23" "Not added,Added"
|
|
bitfld.long 0x00 22. " [22] ,Add Request 22" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Add Request 21" "Not added,Added"
|
|
bitfld.long 0x00 20. " [20] ,Add Request 20" "Not added,Added"
|
|
bitfld.long 0x00 19. " [19] ,Add Request 19" "Not added,Added"
|
|
bitfld.long 0x00 18. " [18] ,Add Request 18" "Not added,Added"
|
|
bitfld.long 0x00 17. " [17] ,Add Request 17" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Add Request 16" "Not added,Added"
|
|
bitfld.long 0x00 15. " [15] ,Add Request 15" "Not added,Added"
|
|
bitfld.long 0x00 14. " [14] ,Add Request 14" "Not added,Added"
|
|
bitfld.long 0x00 13. " [13] ,Add Request 13" "Not added,Added"
|
|
bitfld.long 0x00 12. " [12] ,Add Request 12" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Add Request 11" "Not added,Added"
|
|
bitfld.long 0x00 10. " [10] ,Add Request 10" "Not added,Added"
|
|
bitfld.long 0x00 9. " [9] ,Add Request 9" "Not added,Added"
|
|
bitfld.long 0x00 8. " [8] ,Add Request 8" "Not added,Added"
|
|
bitfld.long 0x00 7. " [7] ,Add Request 7" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Add Request 6" "Not added,Added"
|
|
bitfld.long 0x00 5. " [5] ,Add Request 5" "Not added,Added"
|
|
bitfld.long 0x00 4. " [4] ,Add Request 4" "Not added,Added"
|
|
bitfld.long 0x00 3. " [3] ,Add Request 3" "Not added,Added"
|
|
bitfld.long 0x00 2. " [2] ,Add Request 2" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Add Request 1" "Not added,Added"
|
|
bitfld.long 0x00 0. " [0] ,Add Request 0" "Not added,Added"
|
|
textline ""
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TXBCR,Tx Buffer Cancellation Request"
|
|
bitfld.long 0x00 31. " CR_[31] ,Cancellation Request 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation Request 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation Request 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation Request 28" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation Request 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation Request 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation Request 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation Request 24" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation Request 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation Request 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation Request 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation Request 20" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation Request 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation Request 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation Request 17" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation Request 16" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation Request 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation Request 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation Request 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation Request 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation Request 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation Request 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation Request 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation Request 8" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation Request 7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation Request 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation Request 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation Request 4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation Request 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Cancellation Request 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation Request 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation Request 0" "Not pending,Pending"
|
|
textline ""
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x00 31. " TO_[31] ,Transmission Occurred 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Transmission Occurred 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Transmission Occurred 29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Transmission Occurred 28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [27] ,Transmission Occurred 27" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission Occurred 26" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Transmission Occurred 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Transmission Occurred 24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [23] ,Transmission Occurred 23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Transmission Occurred 22" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission Occurred 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Transmission Occurred 20" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " [19] ,Transmission Occurred 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Transmission Occurred 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Transmission Occurred 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission Occurred 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [15] ,Transmission Occurred 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Transmission Occurred 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Transmission Occurred 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Transmission Occurred 12" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission Occurred 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Transmission Occurred 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Transmission Occurred 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Transmission Occurred 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " [7] ,Transmission Occurred 7" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission Occurred 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Transmission Occurred 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Transmission Occurred 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Transmission Occurred 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Transmission Occurred 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission Occurred 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Transmission Occurred 0" "Not occurred,Occurred"
|
|
textline ""
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x00 31. " CF_[31] ,Cancellation finished 31" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation finished 30" "Not finished,Finished"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation finished 29" "Not finished,Finished"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation finished 28" "Not finished,Finished"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation finished 27" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation finished 26" "Not finished,Finished"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation finished 25" "Not finished,Finished"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation finished 24" "Not finished,Finished"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation finished 23" "Not finished,Finished"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation finished 22" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation finished 21" "Not finished,Finished"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation finished 20" "Not finished,Finished"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation finished 19" "Not finished,Finished"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation finished 18" "Not finished,Finished"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation finished 17" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation finished 16" "Not finished,Finished"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation finished 15" "Not finished,Finished"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation finished 14" "Not finished,Finished"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation finished 13" "Not finished,Finished"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation finished 12" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation finished 11" "Not finished,Finished"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation finished 10" "Not finished,Finished"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation finished 9" "Not finished,Finished"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation finished 8" "Not finished,Finished"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation finished 7" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation finished 6" "Not finished,Finished"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation finished 5" "Not finished,Finished"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation finished 4" "Not finished,Finished"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation finished 3" "Not finished,Finished"
|
|
bitfld.long 0x00 2. " [2] ,Cancellation finished 2" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation finished 1" "Not finished,Finished"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation finished 0" "Not finished,Finished"
|
|
textline ""
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x00 31. " TIE_[31] ,Transmission interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x00 31. " CFIE_[31] ,Cancellation Finished Interrupt Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation Finished Interrupt Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation Finished Interrupt Enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation Finished Interrupt Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation Finished Interrupt Enable 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation Finished Interrupt Enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation Finished Interrupt Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation Finished Interrupt Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation Finished Interrupt Enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation Finished Interrupt Enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation Finished Interrupt Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation Finished Interrupt Enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation Finished Interrupt Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation Finished Interrupt Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation Finished Interrupt Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation Finished Interrupt Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation Finished Interrupt Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation Finished Interrupt Enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation Finished Interrupt Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation Finished Interrupt Enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation Finished Interrupt Enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation Finished Interrupt Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation Finished Interrupt Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation Finished Interrupt Enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation Finished Interrupt Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation Finished Interrupt Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation Finished Interrupt Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation Finished Interrupt Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation Finished Interrupt Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2 ] ,Cancellation Finished Interrupt Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation Finished Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation Finished Interrupt Enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
if (((per.l(ad:0xB4900000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Start Address"
|
|
else
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Start Address"
|
|
endif
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "No el. lost,Lost"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree "CAN FD MESSAGE RAM ECC FUNCTION"
|
|
if (((per.l(ad:0xB4900000+0x18))&0x02)==0x02)
|
|
group.byte 0x200++0x0
|
|
line.byte 0x00 "FDECR,CAN FD ECC Error Control Register"
|
|
bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes"
|
|
bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x200++0x0
|
|
line.byte 0x00 "FDECR,CAN FD ECC Error Control Register"
|
|
rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes"
|
|
rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x201++0x0
|
|
line.byte 0x00 "FDESR,CAN FD ECC Error Status Register"
|
|
bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not detected,Detected"
|
|
if (((per.l(ad:0xB4900000+0x201))&0x01)==0x01)
|
|
rgroup.word 0x202++0x1
|
|
line.word 0x00 "FDSEAR,CAN FD ECC Single-bit Error Address Register"
|
|
else
|
|
hgroup.word 0x202++0x1
|
|
hide.word 0x00 "FDSEAR,CAN FD ECC Single-bit Error Address Register"
|
|
endif
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x00 "FDESCR,CAN FD ECC Status Clear Register"
|
|
bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No effect,Clear"
|
|
if (((per.l(ad:0xB4900000+0x201))&0x02)==0x02)
|
|
rgroup.word 0x206++0x1
|
|
line.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register"
|
|
else
|
|
hgroup.word 0x206++0x1
|
|
hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "FDFECR,CAN FD ECC False Error Control Register"
|
|
bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No error,Error"
|
|
bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No error,Error"
|
|
bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EI_[15] ,Error specification bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No error,Error"
|
|
bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No error,Error"
|
|
bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No error,Error"
|
|
bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No error,Error"
|
|
bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No error,Error"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("S6J311?HAA")
|
|
tree "CPG_CANFD1"
|
|
base ad:0xB4910000
|
|
width 8.
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--15. " MON ,Time Stamp Month" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0x00 0.--7. " DAY ,Time Stamp Day" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "ENDN,Endian Register"
|
|
sif (cpu()!="S6J323CKS")&&(cpu()!="S6J323CLS")&&(cpu()!="S6J324CKS")&&(cpu()!="S6J324CLS")&&(cpu()!="S6J325CKS")&&(cpu()!="S6J325CLS")&&(cpu()!="S6J326CKS")&&(cpu()!="S6J326CLS")&&(!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CUST,CUST"
|
|
endif
|
|
if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "FBTP,Fast Bit Timing & Prescaler Register"
|
|
bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " TDC ,Transceiver delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " FSJW ,Fast Re Synchronization Jump Width" "0,1,2,3"
|
|
else
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "FBTP,Fast Bit Timing & Prescaler Register"
|
|
bitfld.long 0x00 24.--28. " TDCO ,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 23. " TDC ,Transceiver delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " FBRP ,Fast Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " FTSEG1 ,Fast time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--6. " FTSEG2 ,Fast time segment after sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " FSJW ,Fast Re Synchronization Jump Width" "0,1,2,3"
|
|
endif
|
|
if (((per.l(ad:0xB4910000+0x18))&0x80)==0x80)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 8.--13. " TDCV ,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "Con. by CAN,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 8.--13. " TDCV ,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. " RX ,Receive Pin" "Dominant,Recessive"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " TX ,Control of Transmit Pin" "Con. by CAN,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBCK ,Loop Back Mode" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311*")||cpuis("S6J312?HAA")
|
|
if (((per.l(ad:0xB4910000+0x18))&0x03)==0x03)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
endif
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog Configuration"
|
|
endif
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
bitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
bitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
elif (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
rbitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
rbitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
rbitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "CCCR,CC Control Register"
|
|
rbitfld.long 0x00 14. " TXP ,Transmit Pause" "Disabled,Enabled"
|
|
rbitfld.long 0x00 13. " FDBS ,CAN FD Bit Rate Switching" "No switching,Switching"
|
|
rbitfld.long 0x00 12. " FDO ,CAN FD Operation" "ISO11898,FD format"
|
|
bitfld.long 0x00 10.--11. " CMR ,CAN Mode Request" "Unchanged,FD operation,With switching,ISO11898"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " CME ,CAN Mode Enable" "ISO11898,Enabled,Enabled with switching,Enabled with switching"
|
|
rbitfld.long 0x00 7. " TEST ,Test Mode Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DAR ,Disable Automatic Retransmission" "No,Yes"
|
|
rbitfld.long 0x00 5. " MON ,Bus Monitoring Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSR ,Clock Stop Request" "Not requested,Requested"
|
|
rbitfld.long 0x00 3. " CSA ,Clock Stop Acknowledge" "Not acknowledged,Acknowledged"
|
|
rbitfld.long 0x00 2. " ASM ,Restricted Operation Mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " CCE ,Configuration Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal,Initialization"
|
|
endif
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "BTP,Bit Timing & Prescaler Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler"
|
|
bitfld.long 0x00 8.--13. " TSEG1 ,Time Segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SJW ,Re Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "BTP,Bit Timing & Prescaler Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler"
|
|
bitfld.long 0x00 8.--13. " TSEG1 ,Time Segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--7. " TSEG2 ,Time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SJW ,Re Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],CAN FD,0"
|
|
else
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],CAN FD,0"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],,0"
|
|
else
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "TSCC,Timestamp Counter Configuration"
|
|
bitfld.long 0x00 16.--19. " TCP ,Timestamp Counter Prescaler" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0.--1. " TSS ,Timestamp Select" "0,TSCC.TCP[0-3],,0"
|
|
endif
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSC ,Timestamp Counter"
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "Continuous,Tx FIFO,Rx FIFO 0,Rx FIFO 1"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x00 16.--31. 1. " TOP ,Timeout Period"
|
|
bitfld.long 0x00 1.--2. " TOS ,Timeout Select" "Continuous,Tx FIFO,Rx FIFO 0,Rx FIFO 1"
|
|
bitfld.long 0x00 0. " ETOC ,Enable Timeout Counter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " TOC ,Timeout Counter"
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "ECR,Error Counter Register"
|
|
in
|
|
hgroup.long 0x44++0x3
|
|
hide.long 0x00 "PSR,Protocol Status Register"
|
|
in
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
eventfld.long 0x00 31. " STE ,Stuff error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " FOE ,Format error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " ACKE ,Acknowledge error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " BE ,Bit error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 27. " CRCE ,CRC error" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " WDI ,Watchdog interrupt" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " BO ,Bus_Off status" "Unchanged,Changed"
|
|
eventfld.long 0x00 24. " EW ,Warning status" "Unchanged,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 23. " EP ,Error passive" "Unchanged,Changed"
|
|
eventfld.long 0x00 22. " ELO ,Error logging overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " BEU ,Bit error uncorrected" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " BEC ,Bit error corrected" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " DRX ,Message stored to dedicated Rx buffer" "Updated,Stored"
|
|
eventfld.long 0x00 18. " TOO ,Timeout occurred" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " MRAF ,Message RAM Access failure" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " TSW ,Timestamp wraparound" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " TEFL ,Tx event FIFO element lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " TEFF ,Tx event FIFO full" "Not full,Full"
|
|
eventfld.long 0x00 13. " TEFW ,Tx event FIFO watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 12. " TEFN ,Tx event FIFO new entry" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " TFE ,Tx FIFO empty" "Not empty,Empty"
|
|
eventfld.long 0x00 10. " TCF ,Transmission cancellation finished" "Not finished,Finished"
|
|
eventfld.long 0x00 9. " TC ,Transmission competed" "Not completed,Completed"
|
|
eventfld.long 0x00 8. " HPM ,High priority message" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 7. " RF1L ,Rx FIFO 1 message lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RF1F ,Rx FIFO 1 Full" "Not full,Full"
|
|
eventfld.long 0x00 5. " RF1W ,Rx FIFO 1 watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 4. " RF1N ,FIFO 1 new message" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RF0L ,Rx FIFO 0 Message lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "Not full,Full"
|
|
eventfld.long 0x00 1. " RF0W ,Rx FIFO 0 watermark reached" "Below,Reached"
|
|
eventfld.long 0x00 0. " RF0N ,Rx FIFO 0 new message" "Not occurred,Occurred"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "IE,Interrupt enable"
|
|
bitfld.long 0x00 31. " STEE ,Stuff error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FOEE ,Format error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ACKEE ,Acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BEE ,Bit error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CRCEE ,CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " BOE ,Bus_Off status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EWE ,Warning status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPE ,Error passive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ELOE ,Error logging overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BEUE ,Bit error uncorrected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " BECE ,Bit error corrected interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DRXE ,Message stored to dedicated Rx buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TOOE ,Timeout occurred interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MRAFE ,Message RAM Access failure interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TSWE ,Timestamp wraparound interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEFLE ,Tx event FIFO element lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TEFFE ,Tx event FIFO full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TEFWE ,Tx event FIFO watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TEFNE ,Tx event FIFO new entry interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFEE ,Tx FIFO empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TCFE ,Transmission cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TCE ,Transmission competed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HPME ,High priority message interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RF1LE ,Rx FIFO 1 message lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RF1FE ,Rx FIFO 1 Full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RF1WE ,Rx FIFO 1 watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RF1NE ,FIFO 1 new message interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RF0LE ,Rx FIFO 0 Message lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RF0FE ,Rx FIFO 0 Full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RF0WE ,Rx FIFO 0 watermark reached interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RF0NE ,Rx FIFO 0 new message interrupt enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "ILS,Interrupt line select"
|
|
bitfld.long 0x00 31. " STEL ,Stuff error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 30. " FOEL ,Format error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 29. " ACKEL ,Acknowledge error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 28. " BEL ,Bit error interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CRCEL ,CRC error interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 26. " WDIL ,Watchdog interrupt interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 25. " BOL ,Bus_Off status interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 24. " EWL ,Warning status interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EPL ,Error passive interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 22. " ELOL ,Error logging overflow interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 21. " BEUL ,Bit error uncorrected interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 20. " BECL ,Bit error corrected interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DRXL ,Message stored to dedicated Rx buffer interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 18. " TOOL ,Timeout occurred interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 17. " MRAFL ,Message RAM Access failure interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 16. " TSWL ,Timestamp wraparound interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEFLL ,Tx event FIFO element lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 14. " TEFFL ,Tx event FIFO full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 13. " TEFWL ,Tx event FIFO watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 12. " TEFNL ,Tx event FIFO new entry interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TFEL ,Tx FIFO empty interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 10. " TCFL ,Transmission cancellation finished interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 9. " TCL ,Transmission competed interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 8. " HPML ,High priority message interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RF1LL ,Rx FIFO 1 message lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 6. " RF1FL ,Rx FIFO 1 Full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 5. " RF1WL ,Rx FIFO 1 watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 4. " RF1NL ,FIFO 1 new message interrupt line" "Canfd_int0,Canfd_int1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RF0LL ,Rx FIFO 0 Message lost interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 2. " RF0FL ,Rx FIFO 0 Full interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 1. " RF0WL ,Rx FIFO 0 watermark reached interrupt line" "Canfd_int0,Canfd_int1"
|
|
bitfld.long 0x00 0. " RF0NL ,Rx FIFO 0 new message interrupt line" "Canfd_int0,Canfd_int1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "ILE,Interrupt line enable"
|
|
bitfld.long 0x00 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled"
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,Reject,Reject"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,Reject,Reject"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "SIDFC,Standard ID Filter configuration"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LSS ,List size standard"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLSSA ,Filter list standard start address"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "XIDFC,Extended ID filter configuration"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LSE ,List size extended"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLESA ,Filter list extended start address"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask"
|
|
else
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "FIFO 0,FIFO 1,,"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "FIFO 0,FIFO 1,,"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard(11-bit standard)" "Filter,Reject"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended(29-bit extended)" "Filter,Reject"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "SIDFC,Standard ID Filter configuration"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LSS ,List size standard"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLSSA ,Filter list standard start address"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "XIDFC,Extended ID filter configuration"
|
|
hexmask.long.byte 0x00 16.--22. 1. " LSE ,List size extended"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " FLESA ,Filter list extended start address"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID Mask"
|
|
endif
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "HPMS,High priority message status"
|
|
bitfld.long 0x00 15. " FLST ,Filter List" "Standard,Extended"
|
|
hexmask.long.byte 0x00 8.--14. 1. " FIDX ,Filter index"
|
|
bitfld.long 0x00 6.--7. " MSI ,Message storage indicator" "No Rx FIFO,Rx FIFO msg. lost,Stored in FIFO 0,Stored in FIFO 1"
|
|
bitfld.long 0x00 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline ""
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "NDAT1,New Data 1"
|
|
eventfld.long 0x00 31. " ND_[31] ,New Data_31" "Not updated,Updated"
|
|
eventfld.long 0x00 30. " [30] ,New Data_30" "Not updated,Updated"
|
|
eventfld.long 0x00 29. " [29] ,New Data_29" "Not updated,Updated"
|
|
eventfld.long 0x00 28. " [28] ,New Data_28" "Not updated,Updated"
|
|
eventfld.long 0x00 27. " [27] ,New Data_27" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 26. " [26] ,New Data_26" "Not updated,Updated"
|
|
eventfld.long 0x00 25. " [25] ,New Data_25" "Not updated,Updated"
|
|
eventfld.long 0x00 24. " [24] ,New Data_24" "Not updated,Updated"
|
|
eventfld.long 0x00 23. " [23] ,New Data_23" "Not updated,Updated"
|
|
eventfld.long 0x00 22. " [22] ,New Data_22" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 21. " [21] ,New Data_21" "Not updated,Updated"
|
|
eventfld.long 0x00 20. " [20] ,New Data_20" "Not updated,Updated"
|
|
eventfld.long 0x00 19. " [19] ,New Data_19" "Not updated,Updated"
|
|
eventfld.long 0x00 18. " [18] ,New Data_18" "Not updated,Updated"
|
|
eventfld.long 0x00 17. " [17] ,New Data_17" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [16] ,New Data_16" "Not updated,Updated"
|
|
eventfld.long 0x00 15. " [15] ,New Data_15" "Not updated,Updated"
|
|
eventfld.long 0x00 14. " [14] ,New Data_14" "Not updated,Updated"
|
|
eventfld.long 0x00 13. " [13] ,New Data_13" "Not updated,Updated"
|
|
eventfld.long 0x00 12. " [12] ,New Data_12" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [11] ,New Data_11" "Not updated,Updated"
|
|
eventfld.long 0x00 10. " [10] ,New Data_10" "Not updated,Updated"
|
|
eventfld.long 0x00 9. " [9] ,New Data_9" "Not updated,Updated"
|
|
eventfld.long 0x00 8. " [8] ,New Data_8" "Not updated,Updated"
|
|
eventfld.long 0x00 7. " [7] ,New Data_7" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [6] ,New Data_6" "Not updated,Updated"
|
|
eventfld.long 0x00 5. " [5] ,New Data_5" "Not updated,Updated"
|
|
eventfld.long 0x00 4. " [4] ,New Data_4" "Not updated,Updated"
|
|
eventfld.long 0x00 3. " [3] ,New Data_3" "Not updated,Updated"
|
|
eventfld.long 0x00 2. " [2] ,New Data_2" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [1] ,New Data_1" "Not updated,Updated"
|
|
eventfld.long 0x00 0. " [0] ,New Data_0" "Not updated,Updated"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "NDAT2,New Data 2"
|
|
eventfld.long 0x00 31. " ND_[63] ,New Data_63" "Not updated,Updated"
|
|
eventfld.long 0x00 30. " [62] ,New Data_62" "Not updated,Updated"
|
|
eventfld.long 0x00 29. " [61] ,New Data_61" "Not updated,Updated"
|
|
eventfld.long 0x00 28. " [60] ,New Data_60" "Not updated,Updated"
|
|
eventfld.long 0x00 27. " [59] ,New Data_59" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 26. " [58] ,New Data_58" "Not updated,Updated"
|
|
eventfld.long 0x00 25. " [57] ,New Data_57" "Not updated,Updated"
|
|
eventfld.long 0x00 24. " [56] ,New Data_56" "Not updated,Updated"
|
|
eventfld.long 0x00 23. " [55] ,New Data_55" "Not updated,Updated"
|
|
eventfld.long 0x00 22. " [54] ,New Data_54" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 21. " [53] ,New Data_53" "Not updated,Updated"
|
|
eventfld.long 0x00 20. " [52] ,New Data_52" "Not updated,Updated"
|
|
eventfld.long 0x00 19. " [51] ,New Data_51" "Not updated,Updated"
|
|
eventfld.long 0x00 18. " [50] ,New Data_50" "Not updated,Updated"
|
|
eventfld.long 0x00 17. " [49] ,New Data_49" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 16. " [48] ,New Data_48" "Not updated,Updated"
|
|
eventfld.long 0x00 15. " [47] ,New Data_47" "Not updated,Updated"
|
|
eventfld.long 0x00 14. " [46] ,New Data_46" "Not updated,Updated"
|
|
eventfld.long 0x00 13. " [45] ,New Data_45" "Not updated,Updated"
|
|
eventfld.long 0x00 12. " [44] ,New Data_44" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 11. " [43] ,New Data_43" "Not updated,Updated"
|
|
eventfld.long 0x00 10. " [42] ,New Data_42" "Not updated,Updated"
|
|
eventfld.long 0x00 9. " [41] ,New Data_41" "Not updated,Updated"
|
|
eventfld.long 0x00 8. " [40] ,New Data_40" "Not updated,Updated"
|
|
eventfld.long 0x00 7. " [39] ,New Data_39" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [38] ,New Data_38" "Not updated,Updated"
|
|
eventfld.long 0x00 5. " [37] ,New Data_37" "Not updated,Updated"
|
|
eventfld.long 0x00 4. " [36] ,New Data_36" "Not updated,Updated"
|
|
eventfld.long 0x00 3. " [35] ,New Data_35" "Not updated,Updated"
|
|
eventfld.long 0x00 2. " [34] ,New Data_34" "Not updated,Updated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " [33] ,New Data_33" "Not updated,Updated"
|
|
eventfld.long 0x00 0. " [32] ,New Data_32" "Not updated,Updated"
|
|
textline ""
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F0S ,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address"
|
|
else
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x00 31. " F0OM ,FIFO 0 Operation Mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F0WM ,Rx FIFO 0 Watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F0S ,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F0SA ,Rx FIFO 0 Start Address"
|
|
endif
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x00 "RXF0S,Rx FIFO Status"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 message lost" "No msg. lost,Message lost"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 FUll" "Not Full,Full"
|
|
bitfld.long 0x00 16.--21. " F0PI ,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx 0 Fill level"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,Rx Buffer Start Address"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
else
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x00 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " RBSA ,Rx Buffer Start Address"
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x00 31. " F1OM ,FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x00 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.byte 0x00 16.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
endif
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x00 30.--31. " DMS ,Debug Message Status" "Idle,A received,A B received,A B C received"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 MEssage Lost" "No msg. lost,Message lost"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " F1PI ,Rx FIFO 1 put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 Fill level"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0xBC++0x3
|
|
line.long 0x00 "RXESC,Rx Buffer/FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx buffer data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "Tx FIFO,Tx Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx Buffers Start Address"
|
|
else
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x00 "RXESC,Rx Buffer/FIFO Element Size Configuration"
|
|
bitfld.long 0x00 8.--10. " RBDS ,Rx buffer data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 4.--6. " F1DS ,Rx FIFO 1 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
bitfld.long 0x00 0.--2. " F0DS ,Rx FIFO 0 data field size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x00 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/Queue Mode" "Tx FIFO,Tx Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx Buffers Start Address"
|
|
endif
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x00 "TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x00 21. " TFQF ,FIFO/Queue Full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " TFQPI ,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " TFGI ,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " TFFL ,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
else
|
|
rgroup.long 0xC8++0x3
|
|
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx Buffer Data Field Size" "8byte,12byte,16byte,20byte,24byte,32byte,48byte,64byte"
|
|
endif
|
|
textline ""
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending"
|
|
bitfld.long 0x00 31. " TRP_[31] ,Transmission Request Pending 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Transmission Request Pending 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Transmission Request Pending 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Transmission Request Pending 28" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Transmission Request Pending 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission Request Pending 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Transmission Request Pending 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Transmission Request Pending 24" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Transmission Request Pending 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Transmission Request Pending 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission Request Pending 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Transmission Request Pending 20" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Transmission Request Pending 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Transmission Request Pending 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Transmission Request Pending 17" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission Request Pending 16" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Transmission Request Pending 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Transmission Request Pending 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Transmission Request Pending 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Transmission Request Pending 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission Request Pending 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Transmission Request Pending 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Transmission Request Pending 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Transmission Request Pending 8" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Transmission Request Pending 7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission Request Pending 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Transmission Request Pending 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Transmission Request Pending 4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Transmission Request Pending 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Transmission Request Pending 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission Request Pending 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Transmission Request Pending 0" "Not pending,Pending"
|
|
textline ""
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "TXBAR,Tx Buffer Add request"
|
|
bitfld.long 0x00 31. " AR_[31] ,Add Request 31" "Not added,Added"
|
|
bitfld.long 0x00 30. " [30] ,Add Request 30" "Not added,Added"
|
|
bitfld.long 0x00 29. " [29] ,Add Request 29" "Not added,Added"
|
|
bitfld.long 0x00 28. " [28] ,Add Request 28" "Not added,Added"
|
|
bitfld.long 0x00 27. " [27] ,Add Request 27" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Add Request 26" "Not added,Added"
|
|
bitfld.long 0x00 25. " [25] ,Add Request 25" "Not added,Added"
|
|
bitfld.long 0x00 24. " [24] ,Add Request 24" "Not added,Added"
|
|
bitfld.long 0x00 23. " [23] ,Add Request 23" "Not added,Added"
|
|
bitfld.long 0x00 22. " [22] ,Add Request 22" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Add Request 21" "Not added,Added"
|
|
bitfld.long 0x00 20. " [20] ,Add Request 20" "Not added,Added"
|
|
bitfld.long 0x00 19. " [19] ,Add Request 19" "Not added,Added"
|
|
bitfld.long 0x00 18. " [18] ,Add Request 18" "Not added,Added"
|
|
bitfld.long 0x00 17. " [17] ,Add Request 17" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Add Request 16" "Not added,Added"
|
|
bitfld.long 0x00 15. " [15] ,Add Request 15" "Not added,Added"
|
|
bitfld.long 0x00 14. " [14] ,Add Request 14" "Not added,Added"
|
|
bitfld.long 0x00 13. " [13] ,Add Request 13" "Not added,Added"
|
|
bitfld.long 0x00 12. " [12] ,Add Request 12" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Add Request 11" "Not added,Added"
|
|
bitfld.long 0x00 10. " [10] ,Add Request 10" "Not added,Added"
|
|
bitfld.long 0x00 9. " [9] ,Add Request 9" "Not added,Added"
|
|
bitfld.long 0x00 8. " [8] ,Add Request 8" "Not added,Added"
|
|
bitfld.long 0x00 7. " [7] ,Add Request 7" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Add Request 6" "Not added,Added"
|
|
bitfld.long 0x00 5. " [5] ,Add Request 5" "Not added,Added"
|
|
bitfld.long 0x00 4. " [4] ,Add Request 4" "Not added,Added"
|
|
bitfld.long 0x00 3. " [3] ,Add Request 3" "Not added,Added"
|
|
bitfld.long 0x00 2. " [2] ,Add Request 2" "Not added,Added"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Add Request 1" "Not added,Added"
|
|
bitfld.long 0x00 0. " [0] ,Add Request 0" "Not added,Added"
|
|
textline ""
|
|
group.long 0xD4++0x3
|
|
line.long 0x00 "TXBCR,Tx Buffer Cancellation Request"
|
|
bitfld.long 0x00 31. " CR_[31] ,Cancellation Request 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation Request 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation Request 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation Request 28" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation Request 27" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation Request 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation Request 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation Request 24" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation Request 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation Request 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation Request 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation Request 20" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation Request 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation Request 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation Request 17" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation Request 16" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation Request 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation Request 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation Request 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation Request 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation Request 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation Request 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation Request 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation Request 8" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation Request 7" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation Request 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation Request 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation Request 4" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation Request 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Cancellation Request 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation Request 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation Request 0" "Not pending,Pending"
|
|
textline ""
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x00 31. " TO_[31] ,Transmission Occurred 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Transmission Occurred 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Transmission Occurred 29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Transmission Occurred 28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [27] ,Transmission Occurred 27" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission Occurred 26" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Transmission Occurred 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Transmission Occurred 24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [23] ,Transmission Occurred 23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Transmission Occurred 22" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission Occurred 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Transmission Occurred 20" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " [19] ,Transmission Occurred 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Transmission Occurred 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Transmission Occurred 17" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission Occurred 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [15] ,Transmission Occurred 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Transmission Occurred 14" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Transmission Occurred 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Transmission Occurred 12" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission Occurred 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Transmission Occurred 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Transmission Occurred 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Transmission Occurred 8" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " [7] ,Transmission Occurred 7" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission Occurred 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Transmission Occurred 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Transmission Occurred 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Transmission Occurred 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Transmission Occurred 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission Occurred 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Transmission Occurred 0" "Not occurred,Occurred"
|
|
textline ""
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x00 31. " CF_[31] ,Cancellation finished 31" "Not finished,Finished"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation finished 30" "Not finished,Finished"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation finished 29" "Not finished,Finished"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation finished 28" "Not finished,Finished"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation finished 27" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation finished 26" "Not finished,Finished"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation finished 25" "Not finished,Finished"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation finished 24" "Not finished,Finished"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation finished 23" "Not finished,Finished"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation finished 22" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation finished 21" "Not finished,Finished"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation finished 20" "Not finished,Finished"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation finished 19" "Not finished,Finished"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation finished 18" "Not finished,Finished"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation finished 17" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation finished 16" "Not finished,Finished"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation finished 15" "Not finished,Finished"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation finished 14" "Not finished,Finished"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation finished 13" "Not finished,Finished"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation finished 12" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation finished 11" "Not finished,Finished"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation finished 10" "Not finished,Finished"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation finished 9" "Not finished,Finished"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation finished 8" "Not finished,Finished"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation finished 7" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation finished 6" "Not finished,Finished"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation finished 5" "Not finished,Finished"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation finished 4" "Not finished,Finished"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation finished 3" "Not finished,Finished"
|
|
bitfld.long 0x00 2. " [2] ,Cancellation finished 2" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation finished 1" "Not finished,Finished"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation finished 0" "Not finished,Finished"
|
|
textline ""
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x00 31. " TIE_[31] ,Transmission interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Transmission interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Transmission interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Transmission interrupt enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Transmission interrupt enable 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Transmission interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Transmission interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Transmission interrupt enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Transmission interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Transmission interrupt enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Transmission interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Transmission interrupt enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Transmission interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Transmission interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Transmission interrupt enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Transmission interrupt enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Transmission interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Transmission interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Transmission interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Transmission interrupt enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Transmission interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Transmission interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Transmission interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Transmission interrupt enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Transmission interrupt enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Transmission interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Transmission interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Transmission interrupt enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Transmission interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Transmission interrupt enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Transmission interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Transmission interrupt enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x00 31. " CFIE_[31] ,Cancellation Finished Interrupt Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Cancellation Finished Interrupt Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Cancellation Finished Interrupt Enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Cancellation Finished Interrupt Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Cancellation Finished Interrupt Enable 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [26] ,Cancellation Finished Interrupt Enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Cancellation Finished Interrupt Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Cancellation Finished Interrupt Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Cancellation Finished Interrupt Enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Cancellation Finished Interrupt Enable 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Cancellation Finished Interrupt Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Cancellation Finished Interrupt Enable 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Cancellation Finished Interrupt Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Cancellation Finished Interrupt Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Cancellation Finished Interrupt Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " [16] ,Cancellation Finished Interrupt Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Cancellation Finished Interrupt Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Cancellation Finished Interrupt Enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Cancellation Finished Interrupt Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Cancellation Finished Interrupt Enable 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Cancellation Finished Interrupt Enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Cancellation Finished Interrupt Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Cancellation Finished Interrupt Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Cancellation Finished Interrupt Enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Cancellation Finished Interrupt Enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Cancellation Finished Interrupt Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Cancellation Finished Interrupt Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Cancellation Finished Interrupt Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Cancellation Finished Interrupt Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2 ] ,Cancellation Finished Interrupt Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Cancellation Finished Interrupt Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Cancellation Finished Interrupt Enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
if (((per.l(ad:0xB4910000+0x18))&0x01)==0x01)&&(((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Start Address"
|
|
else
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO Watermark" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO Size" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO Start Address"
|
|
endif
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO Element Lost" "No el. lost,Lost"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. " EFAI ,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree "CAN FD MESSAGE RAM ECC FUNCTION"
|
|
if (((per.l(ad:0xB4910000+0x18))&0x02)==0x02)
|
|
group.byte 0x200++0x0
|
|
line.byte 0x00 "FDECR,CAN FD ECC Error Control Register"
|
|
bitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes"
|
|
bitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x200++0x0
|
|
line.byte 0x00 "FDECR,CAN FD ECC Error Control Register"
|
|
rbitfld.byte 0x00 3. " CEIV ,ECC check disable bit" "No,Yes"
|
|
rbitfld.byte 0x00 2. " CEREN ,ECC error response enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DEIE ,Double-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEIE ,Single-bit error factor interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
rgroup.byte 0x201++0x0
|
|
line.byte 0x00 "FDESR,CAN FD ECC Error Status Register"
|
|
bitfld.byte 0x00 1. " DEI ,Double-bit error occurrence bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " SEI ,Single-bit error occurrence bit" "Not detected,Detected"
|
|
if (((per.l(ad:0xB4910000+0x201))&0x01)==0x01)
|
|
rgroup.word 0x202++0x1
|
|
line.word 0x00 "FDSEAR,CAN FD ECC Single-bit Error Address Register"
|
|
else
|
|
hgroup.word 0x202++0x1
|
|
hide.word 0x00 "FDSEAR,CAN FD ECC Single-bit Error Address Register"
|
|
endif
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x00 "FDESCR,CAN FD ECC Status Clear Register"
|
|
bitfld.byte 0x00 1. " DEIC ,Double-bit error clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " SEIC ,Single-bit error clear bit" "No effect,Clear"
|
|
if (((per.l(ad:0xB4910000+0x201))&0x02)==0x02)
|
|
rgroup.word 0x206++0x1
|
|
line.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register"
|
|
else
|
|
hgroup.word 0x206++0x1
|
|
hide.word 0x00 "FDDEAR,FAN FD ECC Double-bit Error Address Register"
|
|
endif
|
|
sif (cpu()!="S6J3118HAA")&&(cpu()!="S6J3119HAA")&&(cpu()!="S6J311AHAA")&&(cpu()!="S6J311BHAA")&&(cpu()!="S6J311CHAA")&&(cpu()!="S6J311DHAA")&&(cpu()!="S6J311EHAA")&&(cpu()!="S6J311BJAA")&&(cpu()!="S6J311CJAA")&&(cpu()!="S6J311DJAA")&&(cpu()!="S6J311EJAA")&&(!cpuis("S6J312?HAA"))
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "FDFECR,CAN FD ECC False Error Control Register"
|
|
bitfld.long 0x00 31. " FERR ,Error insertion enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EY2 ,Error byte specification bit 0-15" "No error,Error"
|
|
bitfld.long 0x00 17. " EY1 ,Error byte specification bit 16-31" "No error,Error"
|
|
bitfld.long 0x00 16. " EY0 ,Error byte specification bit 32-38" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EI_[15] ,Error specification bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " [14] ,Error specification bit 14" "No error,Error"
|
|
bitfld.long 0x00 13. " [13] ,Error specification bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " [12] ,Error specification bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Error specification bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " [10] ,Error specification bit 10" "No error,Error"
|
|
bitfld.long 0x00 9. " [9] ,Error specification bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " [8] ,Error specification bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Error specification bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " [6] ,Error specification bit 6" "No error,Error"
|
|
bitfld.long 0x00 5. " [5] ,Error specification bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " [4] ,Error specification bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Error specification bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " [2] ,Error specification bit 2" "No error,Error"
|
|
bitfld.long 0x00 1. " [1] ,Error specification bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " [0] ,Error specification bit 0" "No error,Error"
|
|
endif
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "CANP (CAN PRESCALER)"
|
|
base ad:0xB0688C00
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CANP_CTR,CAN Prescaler Control Register"
|
|
bitfld.long 0x00 8. " CPCKS ,CAN prescaler source clock selection bit" "PLL clock,Main clock"
|
|
bitfld.long 0x00 0.--5. " CANPRE ,CAN prescaler division setting bits" "No division,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
sif (!cpuis("S6J311?JAA"))&&(!cpuis("S6J311?HAA"))&&(!cpuis("S6J312?HAA"))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CANP_STR,CAN Prescaler Status Register"
|
|
bitfld.long 0x00 1.--2. " SCKM ,Source clock display" "Stopped,PLL clock,Main clock,In the middle"
|
|
bitfld.long 0x00 0. " BUSY ,Busy" "Idle,Busy"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CANP_STR,CAN Prescaler Status Register"
|
|
bitfld.long 0x00 1.--2. " SCKM ,Source clock display" "On-chip,PLL clock,Main clock,On-chip"
|
|
bitfld.long 0x00 0. " BUSY ,Busy" "Idle,Busy"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "MULTI-FUNCTION SERIAL INTERFACE"
|
|
tree "UART (ASYNCHRONOUS SERIAL INTERFACE)"
|
|
tree "UART 0"
|
|
base ad:0xB4800000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4800000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS0_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS0_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4800000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4800000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS0_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS0_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS0_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS0_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS0_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS0_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS0_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS0_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS0_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS0_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS0_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS0_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS0_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS0_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0xB4800400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4800400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS1_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS1_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4800400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4800400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS1_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS1_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS1_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS1_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS1_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS1_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS1_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS1_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS1_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS1_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS1_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS1_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS1_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS1_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 2"
|
|
base ad:0xB4800800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4800800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS2_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS2_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4800800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4800800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS2_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS2_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS2_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS2_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS2_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS2_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS2_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS2_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS2_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS2_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS2_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS2_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS2_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS2_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 3"
|
|
base ad:0xB4800C00
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS3_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS3_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4800C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4800C00+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS3_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS3_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS3_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS3_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS3_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS3_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS3_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS3_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS3_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS3_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS3_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS3_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS3_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS3_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("S6J311?JAA")
|
|
tree "UART 4"
|
|
base ad:0xB4801000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4801000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4801000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS4_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS4_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 5"
|
|
base ad:0xB4801400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4801400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS5_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS5_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4801400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4801400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS5_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS5_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS5_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS5_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS5_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS5_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS5_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS5_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS5_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS5_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS5_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS5_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS5_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS5_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 6"
|
|
base ad:0xB4801800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4801800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4801800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4801800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS8_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS8_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS8_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS8_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS8_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS8_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS8_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS8_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS8_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS8_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS8_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS8_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 7"
|
|
base ad:0xB4801C00
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4801C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4801C00+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 8"
|
|
base ad:0xB4840000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4840000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4840000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4840000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4840000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4840000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4840000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4840000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 9"
|
|
base ad:0xB4840400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4840400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4840400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4840400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4840400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4840400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4840400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4840400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 10"
|
|
base ad:0xB4840800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4840800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4840800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4840800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4840800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4840800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4840800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4840800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 11"
|
|
base ad:0xB4840C000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4840C000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4840C000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4840C000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4840C000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4840C000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4840C000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 12"
|
|
base ad:0xB4841000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4841000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4841000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4841000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 13"
|
|
base ad:0xB4841400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4841400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4841400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4841400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 14"
|
|
base ad:0xB4841800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4841800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4841800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4841800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 15"
|
|
base ad:0xB4841C00
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4841C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4841C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4841C00+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 16"
|
|
base ad:0xB4842000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4842000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4842000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4842000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 17"
|
|
base ad:0xB4842400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4842400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4842400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4842400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 18"
|
|
base ad:0xB4842800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4842800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4842800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4842800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 19"
|
|
base ad:0xB4842C00
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4842C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4842C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4842C00+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 20"
|
|
base ad:0xB4843000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4843000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4843000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4843000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4843000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 21"
|
|
base ad:0xB4843400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4843400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4843400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4843400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4843400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("S6J312?HAA")
|
|
tree "UART 4"
|
|
base ad:0xB4801000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4801000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4801000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS4_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS4_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 8"
|
|
base ad:0xB4880000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4880000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4880000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 9"
|
|
base ad:0xB4880400
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4880400+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4880400+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 10"
|
|
base ad:0xB4880800
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4880800+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4880800+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 11"
|
|
base ad:0xB4880C00
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4880C00+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 12"
|
|
base ad:0xB4881000
|
|
width 20.
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_UART_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.b(ad:0xB4881000+0x02))&0x40)==0x40)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3 bits,4 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_UART_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_UART_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x00))&0xE0)==0x00)
|
|
if (((per.b(ad:0xB4881000+0x02))&0x10)==0x10)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " P ,Parity selection bit" "Even,Odd"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
elif (((per.b(ad:0xB4881000+0x00))&0xE0)==0x20)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,,,7-bit,,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_UART_ESCR,Extended Communication Control Register"
|
|
rbitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length selection bit" "1-2,3-4"
|
|
bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "NRZ,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " L ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,?..."
|
|
endif
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,?..."
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_UART_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_UART_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_UART_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_UART_TBYTE0,Transfer Byte Register"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_UART_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_UART_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bits"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_UART_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bits"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bits"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_UART_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_UART_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_UART_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_UART_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_UART_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_UART_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "CSIO (CLOCK SYNCHRONOUS SERIAL INTERFACE)"
|
|
tree "CSIO 0"
|
|
base ad:0xB4800000
|
|
width 21.
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4800000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS0_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS0_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS0_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4800000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS0_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS0_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS0_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS0_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS0_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS0_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS0_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS0_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS0_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS0_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS0_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS0_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS0_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 1"
|
|
base ad:0xB4800400
|
|
width 21.
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4800400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS1_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS1_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS1_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4800400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS1_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS1_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS1_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS1_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS1_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS1_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS1_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS1_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS1_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS1_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS1_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS1_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS1_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 2"
|
|
base ad:0xB4800800
|
|
width 21.
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4800800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS2_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS2_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS2_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4800800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS2_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS2_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS2_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS2_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS2_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS2_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS2_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS2_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS2_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS2_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS2_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS2_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS2_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 3"
|
|
base ad:0xB4800C00
|
|
width 21.
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4800C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4800C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4800C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4800C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4800C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS3_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS3_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS3_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4800C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4800C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS3_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS3_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS3_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS3_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS3_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS3_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS3_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS3_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS3_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS3_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS3_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS3_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS3_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("S6J311?JAA")
|
|
tree "CSIO 4"
|
|
base ad:0xB4801000
|
|
width 21.
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4801000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS4_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS4_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 5"
|
|
base ad:0xB4801400
|
|
width 21.
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4801400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS5_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS5_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS5_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4801400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS5_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS5_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS5_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS5_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS5_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS5_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS5_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS5_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS5_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS5_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS5_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS5_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS5_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 6"
|
|
base ad:0xB4801400
|
|
width 21.
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4801800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS6_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS6_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS6_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS6_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS6_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS6_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4801800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS6_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS6_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS6_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS6_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS6_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS6_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS6_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS6_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS6_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS6_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS6_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS6_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS6_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 7"
|
|
base ad:0xB4801400
|
|
width 21.
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4801C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS7_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS7_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS7_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS7_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS7_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS7_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4801C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS7_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS7_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS7_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS7_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS7_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS7_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS7_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS7_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS7_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS7_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS7_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS7_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS7_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 8"
|
|
base ad:0xB4880000
|
|
width 21.
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS8_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS8_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS8_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 9"
|
|
base ad:0xB4880400
|
|
width 21.
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 10"
|
|
base ad:0xB4880800
|
|
width 21.
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS10_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS10_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS10_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 11"
|
|
base ad:0xB4880C00
|
|
width 21.
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS11_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS11_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS11_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 12"
|
|
base ad:0xB4841000
|
|
width 21.
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4841000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4841000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4841000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4841000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4841000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4841000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4841000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4841000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS12_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS12_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS12_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 13"
|
|
base ad:0xB4841400
|
|
width 21.
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4841400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4841400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4841400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4841400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4841400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS13_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS13_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS13_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS13_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS13_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS13_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS13_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS13_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS13_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4841400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS13_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS13_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS13_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4841400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4841400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS13_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS13_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS13_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS13_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS13_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS13_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS13_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS13_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS13_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS13_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS13_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS13_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS13_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS13_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS13_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS13_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS13_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS13_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS13_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS13_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 14"
|
|
base ad:0xB4841800
|
|
width 21.
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4841800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4841800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4841800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4841800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4841800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS14_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS14_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS14_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS14_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS14_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS14_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS14_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS14_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS14_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4841800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS14_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS14_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS14_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4841800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4841800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS14_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS14_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS14_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS14_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS14_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS14_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS14_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS14_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS14_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS14_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS14_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS14_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS14_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS14_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS14_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS14_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS14_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS14_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS14_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS14_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 15"
|
|
base ad:0xB4841C00
|
|
width 21.
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4841C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4841C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4841C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4841C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4841C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4841C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS15_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS15_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS15_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS15_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS15_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS15_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS15_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS15_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS15_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4841C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS15_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS15_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS15_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4841C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4841C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS15_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS15_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS15_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS15_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS15_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS15_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS15_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS15_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS15_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS15_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS15_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS15_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS15_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS15_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS15_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS15_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS15_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS15_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS15_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS15_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 16"
|
|
base ad:0xB4842000
|
|
width 21.
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4842000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4842000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4842000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4842000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4842000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS16_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS16_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS16_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS16_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS16_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS16_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4842000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4842000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4842000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS16_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS16_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS16_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS16_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS16_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS16_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS16_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS16_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS16_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS16_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS16_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS16_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS16_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 17"
|
|
base ad:0xB4842400
|
|
width 21.
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4842400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4842400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4842400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4842400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4842400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS17_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS17_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS17_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS17_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS17_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS17_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4842400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4842400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4842400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS17_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS17_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS17_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS17_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS17_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS17_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS17_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS17_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS17_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS17_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS17_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS17_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS17_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 18"
|
|
base ad:0xB4842800
|
|
width 21.
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4842800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4842800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4842800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4842800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4842800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS18_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS18_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS18_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS18_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS18_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS18_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS18_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS18_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS18_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4842800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS18_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS18_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS18_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4842800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4842800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS18_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS18_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS18_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS18_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS18_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS18_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS18_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS18_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS18_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS18_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS18_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS18_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS18_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS18_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS18_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS18_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS18_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS18_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS18_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS18_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 19"
|
|
base ad:0xB4842C00
|
|
width 21.
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4842C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4842C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4842C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4842C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4842C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4842C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS19_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS19_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS19_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS19_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS19_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS19_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS19_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS19_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS19_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4842C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS19_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS19_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS19_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4842C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4842C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS19_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS19_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS19_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS19_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS19_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS19_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS19_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS19_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS19_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS19_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS19_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS19_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS19_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS19_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS19_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS19_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS19_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS19_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS19_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS19_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 20"
|
|
base ad:0xB4843000
|
|
width 21.
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4843000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4843000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4843000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4843000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4843000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4843000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4843000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS20_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS20_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS20_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4843000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS20_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS20_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS20_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS20_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS20_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS20_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4843000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS20_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS20_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS20_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4843000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4843000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS20_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS20_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS20_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS20_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS20_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS20_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS20_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS20_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS20_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS20_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS20_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS20_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS20_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS20_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS20_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS20_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS20_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS20_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS20_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS20_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 21"
|
|
base ad:0xB4843400
|
|
width 21.
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4843400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4843400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4843400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4843400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4843400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4843400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4843400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS21_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS21_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS21_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4843400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS21_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS21_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS21_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS21_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS21_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS21_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4843400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS21_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS21_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS21_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4843400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4843400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS21_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS21_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS21_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS21_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS21_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS21_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS21_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS21_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS21_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS21_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS21_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS21_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS21_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS21_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS21_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS21_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS21_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS21_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS21_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS21_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("S6J312?HAA")
|
|
tree "CSIO 4"
|
|
base ad:0xB4801000
|
|
width 21.
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4801000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4801000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4801000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4801000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4801000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS4_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS4_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4801000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4801000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS4_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS4_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS4_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 8"
|
|
base ad:0xB4880000
|
|
width 21.
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS8_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS8_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS8_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS8_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS8_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS8_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS8_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS8_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS8_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS8_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 9"
|
|
base ad:0xB4880400
|
|
width 21.
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880400+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880400+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880400+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880400+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880400+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS9_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS9_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880400+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880400+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS9_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS9_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS9_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 10"
|
|
base ad:0xB4880800
|
|
width 21.
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880800+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880800+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880800+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880800+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880800+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS10_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS10_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880800+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880800+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS10_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS10_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS10_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS10_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS10_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS10_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS10_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS10_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 11"
|
|
base ad:0xB4880C00
|
|
width 21.
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4880C00+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4880C00+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4880C00+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4880C00+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)||(((per.w(ad:0xB4880C00+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS11_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS11_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4880C00+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4880C00+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS11_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS11_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS11_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS11_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS11_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS11_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS11_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS11_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSIO 12"
|
|
base ad:0xB4881000
|
|
width 21.
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " SPI ,SPI-supporting bit" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/slave function selection bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x0)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "'H' format,'L' format"
|
|
bitfld.byte 0x00 2. " BDS ,Transfer direction selection bit" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SCKE ,Serial clock input/output enable bit" "Input,Output"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.b(ad:0xB4881000+0x01))&0x2)==0x0)&&(((per.b(ad:0xB4881000+0x01))&0x1)==0x0))&&((((per.b(ad:0xB4881000+0x03))&0x2)==0x2)&&(((per.b(ad:0xB4881000+0x03))&0x4)==0x0))
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
bitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 4. " AWC ,Access width control bit" "16-bit,32-bit"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Full"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)||(((per.w(ad:0xB4881000+0x0E))&0x1E)==0x00)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 5. " CSFE ,Serial chip select format enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
bitfld.byte 0x00 0.--2. 6. " L2_0 ,Data length selection bits" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,Set"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")||cpuis("S6J33*")
|
|
bitfld.byte 0x00 6. " L3 ,L3" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.byte 0x00 3.--4. " WT ,Data transmission/reception wait select bit" "0-bit,1-bit,2-bits,3-bits"
|
|
endif
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "MFS12_UART_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "/1,/2,/4,/8,/16,/32,/64,/128,/256,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x20)==0x20)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSR,Serial Auxiliary Control Status Register"
|
|
setclrfld.word 0x00 15. 0x40 15. 0x28 15. " STST_set/clr ,Serial test bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 13. 0x40 13. 0x28 13. " TBEEN_set/clr ,Transfer byte error enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 12. 0x40 12. 0x28 12. " CSEIE_set/clr ,Chip select error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CSE ,Chip select error flag bit" "No error,Error"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
setclrfld.word 0x00 7. 0x40 7. 0x28 7. " TINTE_set/clr ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.word 0x00 6. 0x40 6. 0x28 6. " TSYNE_set/clr ,Synchronous transmission enable bit" "Disabled,Enabled"
|
|
setclrfld.word 0x00 5. 0x40 5. 0x28 5. " TRGE_set/clr ,External trigger enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits" "0,1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
setclrfld.word 0x00 0. 0x40 0. 0x28 0. " TMRE_set/clr ,Serial timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMR,Serial Timer Register"
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x01)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_CSIO_STMCR,Serial Timer Comparison Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "/1,/2,/4,/8,/16,/32,/64,?..."
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
rbitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
rbitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
rbitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
rbitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 14.--15. " SST ,Serial chip select start bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 12.--13. " SED ,Serial chip select end bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SCAM ,Serial chip select active retention bit" "Inactive,Active"
|
|
bitfld.word 0x00 6.--8. " CDIV ,Serial chip select timing operating clock division bits" "0,1,2,3,4,5,6,"
|
|
bitfld.word 0x00 4. " CSEN3 ,Serial chip select enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CSEN2 ,Serial chip select enable bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CSEN1 ,Serial chip select enable bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x40)
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
bitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSCR,Serial Chip Select Control Status Register"
|
|
bitfld.word 0x00 10.--11. " SCD ,Serial chip select display bits" "SCS0,SCS1,SCS2,SCS3"
|
|
rbitfld.word 0x00 5. " CSLVL ,Serial chip select level set bit" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 1. " CSEN0 ,Serial chip select enable bit 0" "Disabled,Enabled"
|
|
rbitfld.word 0x00 0. " CSOE ,Serial chip select output enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03))
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
rgroup.byte 0x11++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
else
|
|
hgroup.byte 0x10++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSTR0,Serial Chip Select Timing Register 0"
|
|
hgroup.byte 0x11++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSTR1,Serial Chip Select Timing Register 1"
|
|
hgroup.word 0x12++0x01
|
|
hide.word 0x00 "MFS12_CSIO_SCSTR2-3,Serial Chip Select Timing Registers 2-3"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x01))&0x43)==(0x01||0x02||0x03))&&(((per.b(ad:0xB4881000+0x02))&0x20)==0x20)
|
|
rgroup.byte 0x14++0x02
|
|
line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 1" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 1" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 1 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 1" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 1" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
elif (((per.b(ad:0xB4881000+0x01))&0x43)==0x00)&&(((per.b(ad:0xB4881000+0x02))&0x20)==0x20)
|
|
group.byte 0x14++0x02
|
|
line.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
bitfld.byte 0x00 7. " CS1CSLVL ,Bit for setting the serial chip select level of chip select 0" "Low,High"
|
|
bitfld.byte 0x00 6. " CS1SCINV ,Bit for inverting the serial clock of chip select 0" "High,Low"
|
|
bitfld.byte 0x00 5. " CS1SPI ,Bit for making serial chip select pin 0 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CS1BDS ,Bit for selecting the transfer direction of chip select pin 0" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--3. " CS1L ,Bits for selecting the data length of serial chip select pin 0" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x01 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
bitfld.byte 0x01 7. " CS2CSLVL ,Bit for setting the serial chip select level of chip select 2" "Low,High"
|
|
bitfld.byte 0x01 6. " CS2SCINV ,Bit for inverting the serial clock of chip select 2" "High,Low"
|
|
bitfld.byte 0x01 5. " CS2SPI ,Bit for making serial chip select pin 2 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " CS2BDS ,Bit for selecting the transfer direction of chip select pin 2" "LSB,MSB"
|
|
bitfld.byte 0x01 0.--3. " CS2L ,Bits for selecting the data length of serial chip select pin 2" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
line.byte 0x02 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
bitfld.byte 0x02 7. " CS3CSLVL ,Bit for setting the serial chip select level of chip select 3" "Low,High"
|
|
bitfld.byte 0x02 6. " CS3SCINV ,Bit for inverting the serial clock of chip select 3" "High,Low"
|
|
bitfld.byte 0x02 5. " CS3SPI ,Bit for making serial chip select pin 3 support SPI" "Normal,SPI"
|
|
textline " "
|
|
bitfld.byte 0x02 4. " CS3BDS ,Bit for selecting the transfer direction of chip select pin 3" "LSB,MSB"
|
|
bitfld.byte 0x02 0.--3. " CS3L ,Bits for selecting the data length of serial chip select pin 3" "8-bit,5-bit,6-bit,7-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,20-bit,24-bit,32-bit,"
|
|
else
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR0,Serial Chip Select Format Register 0"
|
|
hgroup.byte 0x15++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR1,Serial Chip Select Format Register 1"
|
|
hgroup.byte 0x16++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_SCSFR2,Serial Chip Select Format Register 2"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00)
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
else
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE0,Transfer Byte Register 0"
|
|
hgroup.byte 0x19++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE1,Transfer Byte Register 1"
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE2,Transfer Byte Register 2"
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS12_CSIO_TBYTE3,Transfer Byte Register 3"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS12_CSIO_BGR,Baud Rate Generator Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
else
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR1,FIFO Control Register 1"
|
|
setclrfld.byte 0x00 4. 0x34 4. 0x1C 4. " FLSTE_set/clr ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 3. 0x34 3. 0x1C 3. " FRIIE_set/clr ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request" "No transmission,Transmission"
|
|
textline " "
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FTIE_set/clr ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FSEL_set/clr ,FIFO selection bit (transmission/reception)" "FIFO1/FIFO2,FIFO2/FIFO1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Data lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not execute,Execute"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "No effect,Save"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
setclrfld.byte 0x00 1. 0x34 1. 0x1C 1. " FE2_set/clr ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.byte 0x00 0. 0x34 0. 0x1C 0. " FE1_set/clr ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "MFS12_CSIO_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MFS12_CSIO_FTICR,Transmission FIFO Interrupt Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer set bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer set bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO underrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS12_CSIO_TBSIZE,Transmission Block Size Register"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS12_CSIO_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 11. " CSEC ,Clearing the chip select error flag" ",Clear"
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR1C,FIFO Control Clear Register 1"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS12_CSIO_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS12_CSIO_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointer reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointer saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "LIN (LIN COMMUNICATION CONTROL INTERFACE)"
|
|
tree "LIN 0"
|
|
base ad:0xB4800000
|
|
width 19.
|
|
if (((per.b(ad:0xB4800000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4800000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS0_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS0_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4800000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS0_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4800000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS0_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4800000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS0_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4800000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS0_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS0_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS0_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS0_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS0_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4800000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS0_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS0_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS0_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS0_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS0_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS0_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS0_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4800000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS0_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS0_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS0_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS0_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS0_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS0_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS0_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 1"
|
|
base ad:0xB4800400
|
|
width 19.
|
|
if (((per.b(ad:0xB4800400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4800400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS1_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS1_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4800400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS1_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4800400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS1_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4800400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS1_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4800400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS1_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS1_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS1_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS1_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS1_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4800400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS1_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS1_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS1_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS1_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS1_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS1_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS1_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4800400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS1_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS1_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS1_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS1_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS1_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS1_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS1_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 2"
|
|
base ad:0xB4800800
|
|
width 19.
|
|
if (((per.b(ad:0xB4800800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4800800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS2_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS2_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4800800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS2_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4800800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS2_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4800800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS2_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4800800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS2_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS2_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS2_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS2_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS2_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4800800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS2_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS2_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS2_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS2_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS2_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS2_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS2_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4800800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS2_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS2_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS2_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS2_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS2_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS2_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS2_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 3"
|
|
base ad:0xB4800C00
|
|
width 19.
|
|
if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4800C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS3_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS3_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS3_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4800C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4800C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS3_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS3_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4800C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS3_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS3_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS3_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS3_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS3_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4800C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4800C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4800C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS3_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4800C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS3_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS3_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS3_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS3_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS3_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS3_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4800C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS3_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS3_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS3_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS3_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS3_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS3_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS3_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("S6J311?JAA")
|
|
tree "LIN 4"
|
|
base ad:0xB4801000
|
|
width 19.
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4801000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS4_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4801000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS4_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS4_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 5"
|
|
base ad:0xB4801400
|
|
width 19.
|
|
if (((per.b(ad:0xB4801400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4801400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS5_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS5_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4801400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS5_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4801400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS5_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4801400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS5_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4801400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS5_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS5_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS5_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS5_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS5_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4801400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS5_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS5_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS5_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS5_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS5_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS5_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS5_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4801400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS5_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS5_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS5_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS5_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS5_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS5_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS5_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 6"
|
|
base ad:0xB4801400
|
|
width 19.
|
|
if (((per.b(ad:0xB4801800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4801800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS6_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS6_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS6_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4801800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS6_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4801800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS6_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4801800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS6_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS6_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4801800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS6_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS6_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS6_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS6_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS6_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4801800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS6_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS6_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS6_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS6_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS6_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS6_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS6_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4801800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS6_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS6_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS6_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS6_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS6_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS6_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS6_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 7"
|
|
base ad:0xB4801400
|
|
width 19.
|
|
if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4801C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS7_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS7_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS7_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4801C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS7_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS7_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS7_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS7_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4801C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS7_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS7_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS7_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS7_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS7_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4801C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS7_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS7_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS7_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS7_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS7_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS7_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS7_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4801C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS7_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS7_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS7_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS7_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS7_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS7_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS7_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 8"
|
|
base ad:0xB4880000
|
|
width 19.
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS8_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS8_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS8_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS8_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS8_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS8_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS8_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 9"
|
|
base ad:0xB4880400
|
|
width 19.
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS9_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS9_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS9_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 10"
|
|
base ad:0xB4880800
|
|
width 19.
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS10_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS10_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS10_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS10_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS10_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS10_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS10_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 11"
|
|
base ad:0xB4880C00
|
|
width 19.
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS11_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS11_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS11_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS11_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS11_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS11_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS11_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 12"
|
|
base ad:0xB4841000
|
|
width 19.
|
|
if (((per.b(ad:0xB4841000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4841000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4841000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS12_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4841000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4841000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4841000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS12_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4841000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4841000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS12_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4841000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS12_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS12_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS12_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS12_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4841000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 13"
|
|
base ad:0xB4841400
|
|
width 19.
|
|
if (((per.b(ad:0xB4841400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4841400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS13_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS13_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS13_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4841400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS13_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4841400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4841400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4841400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS13_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4841400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS13_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS13_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4841400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS13_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS13_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS13_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS13_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS13_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4841400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS13_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS13_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS13_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS13_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS13_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS13_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS13_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4841400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS13_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS13_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS13_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS13_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS13_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS13_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS13_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 14"
|
|
base ad:0xB4841800
|
|
width 19.
|
|
if (((per.b(ad:0xB4841800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4841800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS14_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS14_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS14_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4841800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS14_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4841800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4841800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4841800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS14_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4841800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS14_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS14_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4841800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS14_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS14_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS14_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS14_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS14_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4841800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS14_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS14_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS14_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS14_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS14_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS14_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS14_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4841800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS14_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS14_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS14_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS14_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS14_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS14_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS14_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 15"
|
|
base ad:0xB4841C00
|
|
width 19.
|
|
if (((per.b(ad:0xB4841C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4841C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS15_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS15_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS15_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4841C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS15_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4841C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4841C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4841C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS15_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS15_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS15_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4841C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS15_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS15_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS15_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS15_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS15_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4841C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4841C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4841C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4841C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS15_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4841C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS15_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS15_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS15_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS15_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS15_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS15_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4841C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS15_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS15_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS15_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS15_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS15_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS15_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS15_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 16"
|
|
base ad:0xB4842000
|
|
width 19.
|
|
if (((per.b(ad:0xB4842000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4842000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS16_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS16_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS16_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4842000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS16_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4842000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4842000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4842000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS16_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4842000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS16_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS16_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4842000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS16_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS16_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS16_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS16_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS16_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4842000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS16_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS16_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS16_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS16_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS16_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS16_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS16_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4842000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS16_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS16_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS16_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS16_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS16_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS16_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS16_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 17"
|
|
base ad:0xB4842400
|
|
width 19.
|
|
if (((per.b(ad:0xB4842400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4842400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS17_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS17_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS17_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4842400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS17_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4842400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4842400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4842400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS17_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4842400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS17_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS17_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4842400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS17_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS17_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS17_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS17_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS17_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4842400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS17_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS17_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS17_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS17_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS17_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS17_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS17_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4842400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS17_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS17_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS17_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS17_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS17_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS17_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS17_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 18"
|
|
base ad:0xB4842800
|
|
width 19.
|
|
if (((per.b(ad:0xB4842800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4842800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS18_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS18_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS18_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4842800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS18_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4842800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4842800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4842800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS18_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4842800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS18_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS18_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4842800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS18_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS18_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS18_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS18_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS18_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4842800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS18_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS18_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS18_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS18_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS18_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS18_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS18_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4842800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS18_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS18_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS18_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS18_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS18_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS18_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS18_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 19"
|
|
base ad:0xB4842C00
|
|
width 19.
|
|
if (((per.b(ad:0xB4842C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4842C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS19_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS19_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS19_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4842C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS19_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4842C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4842C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4842C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS19_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS19_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS19_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4842C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS19_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS19_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS19_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS19_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS19_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4842C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4842C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4842C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4842C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS19_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4842C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS19_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS19_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS19_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS19_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS19_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS19_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4842C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS19_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS19_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS19_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS19_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS19_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS19_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS19_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 20"
|
|
base ad:0xB4843000
|
|
width 19.
|
|
if (((per.b(ad:0xB4843000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4843000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS20_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS20_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS20_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4843000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS20_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4843000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4843000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4843000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4843000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4843000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4843000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4843000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4843000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4843000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS20_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4843000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS20_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS20_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4843000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS20_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS20_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS20_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS20_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS20_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4843000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4843000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4843000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS20_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS20_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS20_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS20_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS20_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS20_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS20_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4843000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS20_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS20_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS20_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS20_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS20_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS20_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS20_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 21"
|
|
base ad:0xB4843400
|
|
width 19.
|
|
if (((per.b(ad:0xB4843400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4843400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS21_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS21_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS21_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4843400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS21_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4843400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4843400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4843400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4843400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4843400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4843400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4843400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4843400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4843400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4843400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS21_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4843400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS21_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS21_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4843400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS21_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS21_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS21_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS21_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS21_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4843400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4843400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4843400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4843400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4843400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS21_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4843400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS21_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS21_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS21_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS21_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS21_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS21_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4843400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS21_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS21_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS21_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS21_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS21_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS21_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS21_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("S6J312?HAA")
|
|
tree "LIN 4"
|
|
base ad:0xB4801000
|
|
width 19.
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4801000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS4_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4801000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4801000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4801000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS4_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4801000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS4_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4801000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS4_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS4_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS4_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4801000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4801000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4801000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS4_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4801000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS4_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS4_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS4_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS4_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4801000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS4_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS4_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS4_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS4_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS4_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS4_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS4_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 8"
|
|
base ad:0xB4880000
|
|
width 19.
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS8_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS8_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS8_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS8_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS8_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS8_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS8_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS8_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS8_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS8_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS8_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS8_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS8_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS8_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS8_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS8_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS8_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS8_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 9"
|
|
base ad:0xB4880400
|
|
width 19.
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880400+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS9_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880400+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880400+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880400+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS9_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880400+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS9_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880400+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS9_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS9_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS9_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880400+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880400+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880400+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS9_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880400+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS9_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS9_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS9_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS9_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880400+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS9_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS9_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS9_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS9_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS9_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS9_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS9_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 10"
|
|
base ad:0xB4880800
|
|
width 19.
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880800+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS10_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880800+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880800+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880800+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS10_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880800+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS10_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880800+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS10_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS10_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS10_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880800+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880800+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880800+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS10_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880800+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS10_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS10_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS10_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS10_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880800+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS10_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS10_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS10_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS10_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS10_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS10_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS10_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 11"
|
|
base ad:0xB4880C00
|
|
width 19.
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4880C00+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS11_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4880C00+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4880C00+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS11_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS11_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4880C00+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS11_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS11_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS11_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4880C00+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4880C00+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS11_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4880C00+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS11_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS11_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS11_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS11_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4880C00+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS11_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS11_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS11_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS11_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS11_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS11_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS11_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LIN 12"
|
|
base ad:0xB4881000
|
|
width 19.
|
|
if (((per.b(ad:0xB4881000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,Generated"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00)
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 5. " LBR ,LIN break field setting bit" "No effect,ID transmitted"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCR,Serial Control Register"
|
|
bitfld.byte 0x00 7. " UPCL ,Programmable clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave"
|
|
bitfld.byte 0x00 4. " RIE ,Reception interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TIE ,Transmission interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIE ,Transmission bus idle interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " RXE ,Reception operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TXE ,Transmission operation enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
textline " "
|
|
if (((per.b(ad:0xB4881000+0x02))&0x40)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "1-bits,2-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMR,Serial Mode Register"
|
|
bitfld.byte 0x00 5.--7. " MD ,Operation mode setting bits" "Asynchronous normal,Asynchronous multi-processor,Clock synchronous,LIN communication,I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUCR ,Wake up control bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " SBL ,Stop bit length selection bit" "3-bits,4-bits"
|
|
bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSR,Serial Status Register"
|
|
bitfld.byte 0x00 7. " REC ,Reception error flag clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 5. " LBD ,LIN break field detection flag bit" "Not detected,Detected"
|
|
rbitfld.byte 0x00 4. " FRE ,Farming error flag bit" "No error,Error"
|
|
rbitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RDRF ,Reception data full flag bit" "Empty,Contain"
|
|
rbitfld.byte 0x00 1. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
rbitfld.byte 0x00 0. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00)
|
|
if (((per.w(ad:0xB4881000+0x12))&0x01)==0x01)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,17-bits,18-bits,19-bits,20-bits"
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. 2.--3. " LBL ,LIN break field length selection bits" "13-bits,14-bits,15-bits,16-bits,?..."
|
|
bitfld.byte 0x00 0.--1. " DEL ,LIN break delimiter length selection bits" "1-bit,2-bits,3-bits,4-bits"
|
|
endif
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCR,Extended Communication Control Register"
|
|
bitfld.byte 0x00 6. " ESBL ,Extended stop bit length" "1-2bit,3-4bit"
|
|
bitfld.byte 0x00 4. " LBIE ,LIN break field detection interrupt enable bit" "Disabled,Enabled"
|
|
endif
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "MFS12_LIN_RDR/TDR,Reception/Transmission Data Register"
|
|
in
|
|
textline " "
|
|
if (((per.w(ad:0xB4881000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x20)
|
|
if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
textline " "
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4881000+0x08))&0x2000)==0x2000)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " BST ,Baud rate setting flag" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
elif (((per.w(ad:0xB4881000+0x08))&0x2000)==0x00)&&(((per.w(ad:0xB4881000+0x08))&0x20)==0x00)
|
|
if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00)
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
bitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4881000+0x08))&0x01)==0x00)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSR,Serial Auxiliary control status register"
|
|
rbitfld.word 0x00 15. " STST ,Serial test bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " SFD ,Sync field detection flag" "Not detected,Detected"
|
|
bitfld.word 0x00 12. " SFDE ,Sync field detection interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " AUTE ,Auto baud rate adjustment bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9.--10. " TRG ,Trigger selection bits" "Rising,Falling,Both,"
|
|
rbitfld.word 0x00 8. " TINT ,Timer interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTE ,Timer interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 5. " TRGE ,External trigger enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 1.--4. " TDIV ,Timer operation clock division bits(division ratio/8MHz/10MHz/16MHz/20MHz/24MHz/32/MHz)" "clock/1|125ns|100ns|62.5ns|50ns|41.67ns|31.25ns,clock/2|250ns|200ns|125ns|100ns|83.33ns|62.5ns,clock/4|500ns|400ns|250ns|200ns|166.667ns|125ns,clock/8|1us|800ns|500ns|400ns|333.33ns|250ns,clock/16|2us|1.6us|1us|800ns|666.67ns|500ns,clock/32|4us|3.2us|2us|1.6us|1.33us|1us,clock/64|8us|6.4us|4us|3.2us|2.67us|2us,clock/128|16us|12.8us|8us|6.4us|5.33us|4us,clock/256|32us|25.6us|16us|12.8us|10.67us|8us,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " TMRE ,Serial time enable bit" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "MFS12_LIN_STMR,Serial timer register"
|
|
if (((per.w(ad:0xB4881000+0x08))&0x1)==0x1)
|
|
rgroup.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register"
|
|
else
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "MFS12_LIN_STMCR,Serial timer comparison register"
|
|
endif
|
|
if (((per.w(ad:0xB4881000+0x08))&0x800)==0x800)
|
|
rgroup.word 0x0E++0x03
|
|
line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
else
|
|
group.word 0x0E++0x03
|
|
line.word 0x00 "MFS12_LIN_SFUR,Sync Field Upper Limit Register"
|
|
hexmask.word 0x00 0.--14. 1. " TU ,Upper limit bits"
|
|
line.word 0x02 "MFS12_LIN_SFLR,Sync Field Lower Limit Register"
|
|
hexmask.word 0x02 0.--14. 1. " TL ,Lower limit bits"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "MFS12_LIN_BGR,Baud Rate Generator Register"
|
|
bitfld.word 0x00 15. " EXT ,External clock selection bit" "Internal,External"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J312?HAA")
|
|
hexmask.word 0x00 0.--14. 1. " BGR ,Baud rate generator register"
|
|
textline " "
|
|
else
|
|
hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud rate generator register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud rate generator register 0"
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x12))&0x01)==0x00)
|
|
if (((per.b(ad:0xB4881000+0x01))&0x02)==0x00)&&(((per.b(ad:0xB4881000+0x01))&0x01)==0x00)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
rbitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x40)
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "RDR,LAMRID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
else
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCR,LIN Assist Mode Control Register"
|
|
bitfld.byte 0x00 4.--7. " LDL ,LIN data length setting bits" "0-byte,1-byte,2-bytes,3-bytes,4-bytes,5-bytes,6-bytes,7-bytes,8-bytes,?..."
|
|
bitfld.byte 0x00 3. " LTDRCL ,LIN transmission data register clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 2. " LCSTYP ,LIN checksum type selection bit" "Standard,Extended"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LIDEN ,LIN ID register use enable bit" "TDR,LAMTID"
|
|
bitfld.byte 0x00 0. " LAMEN ,LIN assist mode processing enable bit" "Manual,Assist"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x13++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
bitfld.byte 0x00 7. " LER ,LIN representative error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 6. " SER ,Serial interface representative error" "No error,Error"
|
|
bitfld.byte 0x00 5. " RDRF ,Reception data full flag bit" "Not full,Full"
|
|
bitfld.byte 0x00 4. " TDRE ,Transmission data empty flag bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TBI ,Transmission bus idle flag bit" "In progress,No transmission"
|
|
bitfld.byte 0x00 2. " LCSC ,LIN checksum calculation completion flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " LAHC ,LIN auto header completion flag bit" "Not detected,Detected"
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission ID Register"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.byte 0x18++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Reception ID Register"
|
|
bitfld.byte 0x00 6.--7. " P ,LIN ID parity display bits" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--5. " LID ,LIN ID setting/display bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x13++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMSR,LIN Assist Mode Status Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMTID,LIN Assist Mode Transmission/Reception ID Register"
|
|
hgroup.byte 0x18++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMRID,LIN Assist Mode Transmission/Reception ID Register"
|
|
endif
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIER,LIN Assist Mode Interrupt Enable Register"
|
|
bitfld.byte 0x00 6. " LCSERIE ,LIN checksum error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LPTERIE ,LIN ID parity error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " LSFERIE ,LIN sync data error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIE ,LIN bus error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " LCSCIE ,LIN checksum calculation completion interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " LAHCIE ,LIN auto header completion interrupt enable bit" "Disabled,Enabled"
|
|
if (((per.w(ad:0xB4881000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
bitfld.byte 0x00 6. " LCSER ,LIN checksum error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 5. " LPTER ,LIN ID parity error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 4. " LSFER ,LIN sync data error flag bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LBSER ,LIN bus error flag bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1B++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMESR,LIN Assist Mode Error Status Register"
|
|
endif
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01)
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0xB4881000+0x12))&0x01)==0x01)
|
|
rgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")||cpuis("S6J311?HAA")
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
textline " "
|
|
else
|
|
bitfld.byte 0x00 6.--7. " KEY_0-1 ,Key code control bits" "0,1,2,3"
|
|
bitfld.byte 0x00 4. " LCSERT ,LIN checksum error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 3. " LPTERT ,LIN ID parity error pseudo error setting bits" "No error,Error"
|
|
bitfld.byte 0x00 2. " LSFERT ,LIN sync data error pseudo error setting bit" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 1. " LBSERT ,LIN bus error pseudo error setting bit" "No error,Error"
|
|
bitfld.byte 0x00 0. " FRET ,Farming error pseudo error setting bit" "No error,Error"
|
|
else
|
|
hgroup.byte 0x1A++0x00
|
|
hide.byte 0x00 "MFS12_LIN_LAMERT,LIN Assist Mode Error Test Register"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0xB4881000+0x21))&0x04)==0x00)
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
else
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTE ,Retransmission data lost detection enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FRIIE ,Reception FIFO idle detection enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " FDRQ ,Transmission FIFO data request bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIE ,Transmission FIFO interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 0. " FSEL ,FIFO selection bit" "FIFO1/2,FIFO2/1"
|
|
endif
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0,FIFO Control Register 0"
|
|
rbitfld.byte 0x00 6. " FLST ,FIFO retransmission data lost flag bit" "Not lost,Lost"
|
|
bitfld.byte 0x00 5. " FLD ,FIFO pointier reload bit" "Not reload,Reload"
|
|
bitfld.byte 0x00 4. " FSET ,FIFO pointer saving bit" "Not saved,Saved"
|
|
bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset"
|
|
bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled"
|
|
group.word 0x22++0x03
|
|
line.word 0x00 "MFS12_LIN_FBYTE,FIFO Byte Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " FBYTE2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x00 0.--7. 1. " FBYTE1 ,FIFO1 data count indication bit"
|
|
line.word 0x02 "MFS12_LIN_FTICR,Transmission FIFO interrupt Control Register"
|
|
hexmask.word.byte 0x02 8.--15. 1. " FTICR2 ,FIFO2 data count indication bit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " FTICR1 ,FIFO1 data count indication bit"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "MFS12_LIN_ECR,Extended Control Register"
|
|
bitfld.byte 0x00 4. " EISEL ,Error interrupt request output selection bit" "Request pin,Error pin"
|
|
bitfld.byte 0x00 3. " REIE ,Reception error interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmission error interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXBLKEN ,Reception block transfer setting bit" "Demand,Block"
|
|
bitfld.byte 0x00 0. " TXBLKEN ,Transmission block transfer setting bit" "Demand,Block"
|
|
rgroup.byte 0x27++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESR,Extended Status Register"
|
|
bitfld.byte 0x00 3. " RXUDR ,Reception FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " TXOVR ,Transmission FIFO overrun flag bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " RBERR ,Reception block transfer error bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " TBERR ,Transmission block transfer error bit" "Not occurred,Occurred"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "MFS12_LIN_TBSIZE,Transmission Block Size Register"
|
|
textline " "
|
|
wgroup.byte 0x2D++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRC,Serial Control Clear Register"
|
|
bitfld.byte 0x00 6. " MSC ,Clearing the master/slave function selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " RIEC ,Clearing the reception interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " TIEC ,Clearing the transmission interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TBIEC ,Clearing the transmission bus idle interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RXEC ,Clearing the reception operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TXEC ,Clearing the transmission operation enable bit" ",Clear"
|
|
wgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMRC,Serial Mode Clear Register"
|
|
bitfld.byte 0x00 4. " WUCRC ,Clearing the WAKE UP control bit" ",Clear"
|
|
bitfld.byte 0x00 3. " SBLC ,Clearing the stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 0. " SOEC ,Clearing the serial data output enable bit" ",Clear"
|
|
wgroup.byte 0x2F++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSRC,Serial Status Clear Register"
|
|
bitfld.byte 0x00 5. " LBDC ,Clearing the LIN Break FIeld detection flag bit" ",Clear"
|
|
wgroup.byte 0x2E++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCRC,Extended Communication Control Clear Register"
|
|
bitfld.byte 0x00 6. " ESBLC ,Clearing the extended stop bit length selection bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LBIEC ,Clearing the LIN Break Field detection interrupt enable bit" ",Clear"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSRC,Serial Auxiliary Control Status Clear Register"
|
|
bitfld.word 0x00 15. " STSTC ,Clearing the serial test bit" ",Clear"
|
|
bitfld.word 0x00 13. " SFDC ,Clearing the Sync Field detection flag" ",Clear"
|
|
bitfld.word 0x00 12. " SFDEC ,Clearing the Sync Field detection interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 11. " AUTEC ,Clearing the auto baud rate adjustment bit" ",Clear"
|
|
textline " "
|
|
bitfld.word 0x00 8. " TINTC ,Clearing the timer interrupt flag" ",Clear"
|
|
bitfld.word 0x00 7. " TINTEC ,Clearing the timer interrupt enable bit" ",Clear"
|
|
bitfld.word 0x00 5. " TRGEC ,Clearing the external trigger enable bit" ",Clear"
|
|
bitfld.word 0x00 0. " TMREC ,Clearing the serial timer enable bit" ",Clear"
|
|
wgroup.byte 0x37++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMSRC,LIN Assist Mode Status Clear Register"
|
|
bitfld.byte 0x00 2. " LCSCC ,Clearing the LIN checksum calculation completion flag" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCC ,Clearing the LIN auto header completion flag" ",Clear"
|
|
wgroup.byte 0x36++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCRC,LIN Assist Mode Control Clear Register"
|
|
bitfld.byte 0x00 2. " LCSTYPC ,Clearing the LIN checksum type selection bit" ",Clear"
|
|
bitfld.byte 0x00 1. " LIDENC ,Clearing the LIN ID register use enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAMENC ,Clearing the LIN assist mode processing enable bit" ",Clear"
|
|
wgroup.byte 0x39++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIERC,LIN Assist Mode Interrupt enable Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERIEC ,Clearing the LIN checksum error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERIEC ,Clearing the LIN ID parity error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERIEC ,Clearing the LIN sync data error interrupt enable bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIEC ,Clearing the LIN bus error interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " LCSCIEC ,Clearing the LIN checksum calculation completion interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " LAHCIEC ,Clearing the LIN auto header completion interrupt enable bit" ",Clear"
|
|
wgroup.byte 0x3B++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMESRC,LIN Assist Mode Error Status Clear Register"
|
|
bitfld.byte 0x00 6. " LCSERC ,Clearing the LIN checksum error flag" ",Clear"
|
|
bitfld.byte 0x00 5. " LPTERC ,Clearing the LIN ID parity error flag" ",Clear"
|
|
bitfld.byte 0x00 4. " LSFERC ,Clearing the LIN sync data error flag" ",Clear"
|
|
bitfld.byte 0x00 3. " LBSERC ,Clearing the LIN but error flag" ",Clear"
|
|
wgroup.byte 0x3D++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1C,FIFO Control Register 1"
|
|
bitfld.byte 0x00 4. " FLSTEC ,Clearing the retransmission data lost detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 3. " FRIIEC ,Clearing the reception FIFO idle detection enable bit" ",Clear"
|
|
bitfld.byte 0x00 2. " FDRQC ,Clearing the transmission FIFO data request bit" ",Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FTIEC ,Clearing the transmission FIFO interrupt enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FSELC ,Clearing the FIFO selection bit" ",Clear"
|
|
wgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0C,FIFO Control CLear Register 0"
|
|
bitfld.byte 0x00 1. " FE2C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
bitfld.byte 0x00 0. " FE1C ,Clearing the FIFO2 operation enable bit" ",Clear"
|
|
wgroup.byte 0x43++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESRC,Extended Status Clear Register"
|
|
bitfld.byte 0x00 3. " RXUDRC ,Reception FIFO underrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 2. " TXOVRC ,Transmission FIFO overrun flag clear bit" ",Clear"
|
|
bitfld.byte 0x00 1. " RBERRC ,Reception block transfer error clear bit" ",Clear"
|
|
bitfld.byte 0x00 0. " TBERRC ,Transmission block transfer error clear bit" ",Clear"
|
|
if (((per.b(ad:0xB4881000+0x01))&0x40)==0x00)
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 5. " LBRS ,Setting the LIN Break Field setting bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
else
|
|
wgroup.byte 0x45++0x00
|
|
line.byte 0x00 "MFS12_LIN_SCRS,Serial Control Set Register"
|
|
bitfld.byte 0x00 7. " UPCLS ,Setting the programmable clear bit" ",Set"
|
|
bitfld.byte 0x00 6. " MSS ,Setting the master/slave function selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " RIES ,Setting the reception interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " TIES ,Setting the transmission interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " TBIES ,Setting the transmission bus idle interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " RXES ,Setting the reception operation enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TXES ,Setting the transmission operation enable bit" ",Set"
|
|
endif
|
|
wgroup.byte 0x44++0x00
|
|
line.byte 0x00 "MFS12_LIN_SMRS,Serial Mode Set Register"
|
|
bitfld.byte 0x00 4. " WUCRS ,Setting the WAKE UP control bit" ",Set"
|
|
bitfld.byte 0x00 3. " SBLS ,Setting the stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 0. " SOES ,Setting the serial data output enable bit" ",Set"
|
|
wgroup.byte 0x47++0x00
|
|
line.byte 0x00 "MFS12_LIN_SSRS,Serial Status Set Register"
|
|
bitfld.byte 0x00 7. " RECS ,Setting the reception error flag clear bit" ",Set"
|
|
wgroup.byte 0x46++0x00
|
|
line.byte 0x00 "MFS12_LIN_ESCRS,Extended Communication Control Set Register"
|
|
bitfld.byte 0x00 6. " ESBLS ,Setting the extended stop bit length selection bit" ",Set"
|
|
bitfld.byte 0x00 4. " LBIES ,Setting the LIN Break FIeld detection interrupt enable bit" ",Set"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "MFS12_LIN_SACSRS,Serial Auxiliary Control Status Set Register"
|
|
bitfld.word 0x00 15. " STSTS ,Setting the serial test bit" ",Set"
|
|
bitfld.word 0x00 12. " SFDES ,Setting the Sync Field detection interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 11. " AUTES ,Setting the auto baud rate adjustment bit" ",Set"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TINTES ,Setting the timer interrupt enable bit" ",Set"
|
|
bitfld.word 0x00 5. " TRGES ,Setting the external trigger enable bit" ",Set"
|
|
bitfld.word 0x00 0. " TMRES ,Setting the serial timer enable bit" ",Set"
|
|
wgroup.byte 0x4E++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMCRS,LIN Assist Mode Control Set Register"
|
|
bitfld.byte 0x00 3. " LTDRCLS ,Setting the LIN transmission data register clear bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSTYPS ,Setting the LIN checksum type selection bit" ",Set"
|
|
bitfld.byte 0x00 1. " LIDENS ,Setting the LIN ID register use enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAMENS ,Setting the LIN assist mode processing enable bit" ",Set"
|
|
wgroup.byte 0x51++0x00
|
|
line.byte 0x00 "MFS12_LIN_LAMIERS,LIN Assist Mode Interrupt Enable Set Register"
|
|
bitfld.byte 0x00 6. " LCSERIES ,Setting the LIN checksum error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 5. " LPTERIES ,Setting the LIN ID parity error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 4. " LSFERIES ,Setting the LIN Sync Data error interrupt enable bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " LBSERIES ,Setting the LIN bus error interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 2. " LCSCIES ,Setting the LIN checksum calculation completion interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " LAHCIES ,Setting the LIN auto header completion interrupt enable bit" ",Set"
|
|
wgroup.byte 0x55++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR1S,FIFO Control Set Register 1"
|
|
bitfld.byte 0x00 4. " FLSTES ,Setting the retransmission data lost detection enable bit" ",Set"
|
|
bitfld.byte 0x00 3. " FRIIES ,Setting the reception FIFO idle detection enable bit" ",Set"
|
|
bitfld.byte 0x00 1. " FTIES ,Setting the transmission FIFO interrupt enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FSELS ,Setting the FIFO selection bit" ",Set"
|
|
wgroup.byte 0x54++0x00
|
|
line.byte 0x00 "MFS12_LIN_FCR0S,FIFO Control Set Register 0"
|
|
bitfld.byte 0x00 5. " FLDS ,Setting the FIFO pointier reload bit" ",Set"
|
|
bitfld.byte 0x00 4. " FSETS ,Setting the FIFO pointier saving bit" ",Set"
|
|
bitfld.byte 0x00 3. " FCL2S ,Setting the FIFO2 reset bit" ",Set"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FCL1S ,Setting the FIFO1 reset bit" ",Set"
|
|
bitfld.byte 0x00 1. " FE2S ,Setting the FIFO2 operation enable bit" ",Set"
|
|
bitfld.byte 0x00 0. " FE1S ,Setting the FIFO1 operation enable bit" ",Set"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "BT_PWM (Base Timer PWM)"
|
|
tree "BT00"
|
|
base ad:0xB4808000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT0_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT0_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT0_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT0_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT0_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT0_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT0_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT0_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT01"
|
|
base ad:0xB4808400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT1_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT1_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT1_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT1_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT1_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT1_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT1_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT1_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT02"
|
|
base ad:0xB4808800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT2_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT2_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT2_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT2_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT2_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT2_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT2_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT2_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT03"
|
|
base ad:0xB4808C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT3_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT3_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT3_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT3_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT3_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT3_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT3_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT3_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT04"
|
|
base ad:0xB4809000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT4_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT4_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT4_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT4_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT4_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT4_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT4_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT4_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT05"
|
|
base ad:0xB4809400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT5_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT5_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT5_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT5_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT5_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT5_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT5_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT5_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT06"
|
|
base ad:0xB4809800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT6_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT6_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT6_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT6_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT6_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT6_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT6_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT6_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT07"
|
|
base ad:0xB4809C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT7_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT7_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT7_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT7_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT7_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT7_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT7_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT7_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT08"
|
|
base ad:0xB480A000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT8_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT8_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT8_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT8_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT8_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT8_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT8_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT8_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT09"
|
|
base ad:0xB480A400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT9_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT9_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT9_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT9_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT9_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT9_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT9_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT9_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT10"
|
|
base ad:0xB480A800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT10_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT10_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT10_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT10_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT10_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT10_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT10_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT10_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT11"
|
|
base ad:0xB480AC00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT11_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT11_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT11_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT11_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT11_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT11_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT11_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT11_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT12"
|
|
base ad:0xB4843800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT12_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT12_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT12_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4843800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT12_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT12_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT12_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT12_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT12_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT13"
|
|
base ad:0xB4843C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT13_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT13_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT13_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4843C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT13_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT13_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT13_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT13_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT13_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT14"
|
|
base ad:0xB4844000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT14_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT14_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT14_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4844000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT14_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT14_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT14_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT14_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT14_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT15"
|
|
base ad:0xB4844400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT15_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT15_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT15_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4844400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT15_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT15_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT15_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT15_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT15_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT16"
|
|
base ad:0xB4844800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT16_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT16_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT16_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4844800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT16_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT16_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT16_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT16_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT16_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT17"
|
|
base ad:0xB4844C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT17_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT17_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT17_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4844C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT17_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT17_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT17_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT17_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT17_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT18"
|
|
base ad:0xB4845000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT18_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT18_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT18_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4845000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT18_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT18_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT18_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT18_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT18_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT19"
|
|
base ad:0xB4845400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT19_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT19_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT19_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4845400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT19_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT19_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT19_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT19_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT19_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT20"
|
|
base ad:0xB4845800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT20_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT20_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT20_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4845800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT20_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT20_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT20_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT20_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT20_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT21"
|
|
base ad:0xB4845C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT21_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT21_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT21_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4845C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT21_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT21_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT21_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT21_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT21_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT22"
|
|
base ad:0xB4846000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT22_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT22_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT22_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT22_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT22_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT22_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT22_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT22_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT23"
|
|
base ad:0xB4846400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT23_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT23_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT23_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT23_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT23_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT23_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT23_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT23_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT24"
|
|
base ad:0xB4846800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT24_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT24_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT24_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT24_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT24_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT24_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT24_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT24_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT25"
|
|
base ad:0xB4846C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT25_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT25_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT25_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT25_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT25_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT25_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT25_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT25_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT26"
|
|
base ad:0xB4847000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT26_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT26_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT26_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT26_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT26_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT26_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT26_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT26_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT27"
|
|
base ad:0xB4847400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT27_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT27_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT27_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT27_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT27_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT27_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT27_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT27_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT28"
|
|
base ad:0xB4847800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT28_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT28_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT28_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT28_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT28_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT28_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT28_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT28_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT29"
|
|
base ad:0xB4847C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT29_PWM_PCSR,PWM Cycle Setting Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT29_PWM_PDUT,PWM Duty Setting Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "BT29_PWM_TMR,Timer Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " TMR ,Timer value data bits"
|
|
if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PWM_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External (rising),External (falling),External (both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PWM_TMCR,Timer Control Register 1"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection (bits 2:0)" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,?..."
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,?..."
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT29_PWM_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 5. 0x08 5. 0x04 5. " DTIE_set/clr ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 1. " DTIR ,Duty match interrupt request" "No interrupt,Interrupt"
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT29_PWM_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection (bit 3)" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT29_PWM_STCC,"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 1. " DTIRC ,Duty match interrupt request clear" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear" "No effect,Clear"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "BT29_PWM_PSDR,Start Delay Value Setting Register"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "BT29_PWM_ADTR,ADC Trigger Value Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "BT_PPG (Base Timer PPG)"
|
|
tree "BT00"
|
|
base ad:0xB4808000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT0_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT0_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT0_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4808000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4808000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT0_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT0_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT0_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT01"
|
|
base ad:0xB4808400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT1_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT1_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT1_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4808400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4808400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT1_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT1_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT1_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT02"
|
|
base ad:0xB4808800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT2_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT2_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT2_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4808800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4808800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT2_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT2_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT2_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT03"
|
|
base ad:0xB4808C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT3_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT3_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT3_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4808C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4808C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4808C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT3_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT3_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT3_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT04"
|
|
base ad:0xB4809000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT4_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT4_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT4_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4809000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4809000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT4_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT4_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT4_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT05"
|
|
base ad:0xB4809400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT5_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT5_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT5_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4809400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4809400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT5_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT5_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT5_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT06"
|
|
base ad:0xB4809800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT6_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT6_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT6_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4809800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4809800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT6_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT6_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT6_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT07"
|
|
base ad:0xB4809C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT7_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT7_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT7_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4809C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4809C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4809C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT7_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT7_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT7_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT08"
|
|
base ad:0xB480A000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT8_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT8_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT8_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB480A000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB480A000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT8_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT8_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT8_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT09"
|
|
base ad:0xB480A400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT9_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT9_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT9_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB480A400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB480A400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT9_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT9_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT9_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT10"
|
|
base ad:0xB480A800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT10_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT10_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT10_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB480A800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480A800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480A800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB480A800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT10_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT10_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT10_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT11"
|
|
base ad:0xB480AC00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT11_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT11_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT11_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480AC00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480AC00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB480AC00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB480AC00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB480AC00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT11_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT11_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT11_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT12"
|
|
base ad:0xB4843800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT12_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT12_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT12_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4843800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4843800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4843800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4843800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT12_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT12_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT12_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT13"
|
|
base ad:0xB4843C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT13_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT13_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT13_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4843C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4843C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4843C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4843C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4843C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT13_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT13_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT13_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT14"
|
|
base ad:0xB4844000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT14_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT14_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT14_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4844000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4844000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT14_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT14_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT14_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT15"
|
|
base ad:0xB4844400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT15_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT15_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT15_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4844400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4844400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT15_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT15_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT15_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT16"
|
|
base ad:0xB4844800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT16_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT16_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT16_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4844800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4844800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT16_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT16_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT16_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT17"
|
|
base ad:0xB4844C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT17_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT17_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT17_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4844C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4844C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4844C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4844C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT17_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT17_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT17_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT18"
|
|
base ad:0xB4845000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT18_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT18_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT18_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4845000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4845000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT18_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT18_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT18_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT19"
|
|
base ad:0xB4845400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT19_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT19_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT19_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4845400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4845400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT19_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT19_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT19_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT20"
|
|
base ad:0xB4845800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT20_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT20_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT20_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4845800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4845800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT20_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT20_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT20_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT21"
|
|
base ad:0xB4845C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT21_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT21_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT21_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4845C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4845C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4845C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4845C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT21_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT21_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT21_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT22"
|
|
base ad:0xB4846000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT22_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT22_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT22_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4846000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4846000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT22_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT22_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT22_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT23"
|
|
base ad:0xB4846400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT23_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT23_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT23_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4846400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4846400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT23_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT23_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT23_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT24"
|
|
base ad:0xB4846800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT24_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT24_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT24_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4846800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4846800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT24_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT24_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT24_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT25"
|
|
base ad:0xB4846C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT25_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT25_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT25_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4846C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4846C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4846C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT25_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT25_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT25_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT26"
|
|
base ad:0xB4847000
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT26_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT26_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT26_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4847000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847000+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847000+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847000+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4847000+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT26_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT26_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT26_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT27"
|
|
base ad:0xB4847400
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT27_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT27_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT27_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4847400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847400+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847400+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847400+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4847400+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT27_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT27_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT27_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT28"
|
|
base ad:0xB4847800
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT28_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT28_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT28_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4847800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847800+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847800+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847800+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4847800+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT28_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT28_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT28_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BT29"
|
|
base ad:0xB4847C00
|
|
width 16.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT29_PPG_PRLL,L Width Setting Reload Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "BT29_PPG_PRLH,H Width Setting Reload Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "BT29_PPG_TMR,Timer Register"
|
|
if (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847C00+0x11))&0x01)==0x00)&&(((per.w(ad:0xB4847C00+0x0C))&0x08)==0x08)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External(rising),External(falling),External(both)"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
elif (((per.b(ad:0xB4847C00+0x11))&0x01)==0x01)&&(((per.w(ad:0xB4847C00+0x0C))&0x08)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at L"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PPG_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bit" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed at H"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising,Falling,Both"
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT29_PPG_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT29_PPG_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT29_PPG_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "BT_RT (Reload Timer Function)"
|
|
tree "BT00"
|
|
base ad:0xB4808000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT0_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT0_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4808000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT0_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT0_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT0_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT01"
|
|
base ad:0xB4808400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT1_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT1_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4808400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT1_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT1_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT1_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT02"
|
|
base ad:0xB4808800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT2_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT2_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4808800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT2_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT2_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT2_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT03"
|
|
base ad:0xB4808C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT3_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT3_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4808C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4808C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT3_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT3_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT3_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT04"
|
|
base ad:0xB4809000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT4_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT4_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4809000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT4_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT4_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT4_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT05"
|
|
base ad:0xB4809400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT5_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT5_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4809400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT5_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT5_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT5_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT06"
|
|
base ad:0xB4809800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT6_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT6_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4809800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT6_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT6_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT6_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT07"
|
|
base ad:0xB4809C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT7_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT7_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4809C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4809C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT7_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT7_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT7_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT08"
|
|
base ad:0xB480A000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT8_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT8_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB480A000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT8_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT8_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT8_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT09"
|
|
base ad:0xB480A400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT9_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT9_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB480A400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT9_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT9_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT9_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT10"
|
|
base ad:0xB480A800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT10_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT10_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB480A800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480A800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT10_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT10_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT10_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT11"
|
|
base ad:0xB480AC00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT11_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT11_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB480AC00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480AC00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB480AC00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT11_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT11_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT11_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT12"
|
|
base ad:0xB4843800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT12_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT12_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4843800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4843800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4843800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT12_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT12_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT12_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT13"
|
|
base ad:0xB4843C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT13_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT13_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4843C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4843C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4843C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT13_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT13_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT13_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT14"
|
|
base ad:0xB4844000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT14_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT14_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4844000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT14_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT14_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT14_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT15"
|
|
base ad:0xB4844400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT15_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT15_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4844400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT15_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT15_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT15_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT16"
|
|
base ad:0xB4844800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT16_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT16_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4844800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT16_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT16_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT16_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT17"
|
|
base ad:0xB4844C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT17_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT17_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4844C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4844C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT17_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT17_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT17_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT18"
|
|
base ad:0xB4845000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT18_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT18_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4845000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT18_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT18_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT18_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT19"
|
|
base ad:0xB4845400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT19_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT19_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4845400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT19_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT19_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT19_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT20"
|
|
base ad:0xB4845800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT20_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT20_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4845400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT20_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT20_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT20_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT21"
|
|
base ad:0xB4845C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT21_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT21_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4845C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4845C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT21_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT21_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT21_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT22"
|
|
base ad:0xB4846000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT22_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT22_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4846000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT22_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT22_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT22_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT23"
|
|
base ad:0xB4846400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT23_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT23_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4846400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT23_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT23_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT23_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT24"
|
|
base ad:0xB4846800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT24_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT24_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4846800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT24_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT24_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT24_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT25"
|
|
base ad:0xB4846C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT25_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT25_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4846C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4846C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT25_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT25_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT25_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT26"
|
|
base ad:0xB4847000
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT26_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT26_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4847000+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847000+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847000+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT26_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT26_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT26_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT27"
|
|
base ad:0xB4847400
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT27_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT27_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4847400+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847400+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847400+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT27_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT27_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT27_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT28"
|
|
base ad:0xB4847800
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT28_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT28_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4847800+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847800+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847800+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT28_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT28_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT28_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT29"
|
|
base ad:0xB4847C00
|
|
width 15.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "BT29_RT_PCSR,Cycle Setting Register"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x00 "BT29_RT_TMR,Timer Register"
|
|
if (((d.b(ad:0xB4847C00+0x11))&0x81)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847C00+0x11))&0x81)==0x80)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,External rising-edge,External falling-edge,External both-edge"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
elif (((d.b(ad:0xB4847C00+0x11))&0x81)==0x81)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Low,High,Low,High"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_RT_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Invalid,Rising edge,Falling edge,Both edges"
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16,32"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 3. " OSEL ,Out polarity specification bit" "Normal,Inverted"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CTEN ,Count operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " STRG ,Software trigger enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT29_RT_STC,Status Control Register"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " TGIE_set/clr ,Trigger interrupt request enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " UDIE_set/clr ,Underflow interrupt request enable bit" "Disabled,Enabled"
|
|
rbitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "No interrupt,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT29_RT_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 7. " GATE ,Gate input enable bit" "Trigger,Gate"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT29_RT_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 2. " TGIRC ,Trigger interrupt request clear bit" "No effect,Clear"
|
|
bitfld.byte 0x00 0. " UDIRC ,Underflow interrupt request clear bit" "No effect,Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "BT_PWC (Base Timer PWC)"
|
|
tree "BT00"
|
|
base ad:0xB4808000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT0_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4808000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT0_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT0_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT0_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT0_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT01"
|
|
base ad:0xB4808400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT1_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4808400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT1_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT1_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT1_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT1_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT02"
|
|
base ad:0xB4808800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT2_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4808800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT2_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT2_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT2_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT2_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT03"
|
|
base ad:0xB4808C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT3_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4808C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT3_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT3_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT3_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT3_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT04"
|
|
base ad:0xB4809000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT4_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4809000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT4_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT4_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT4_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT4_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT05"
|
|
base ad:0xB4809400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT5_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4809400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT5_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT5_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT5_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT5_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT06"
|
|
base ad:0xB4809800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT6_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4809800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT6_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT6_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT6_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT6_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT07"
|
|
base ad:0xB4809C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT7_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4809C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT7_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT7_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT7_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT7_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT08"
|
|
base ad:0xB480A000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT8_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB480A000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT8_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT8_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT8_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT8_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT09"
|
|
base ad:0xB480A400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT9_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB480A400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT9_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT9_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT9_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT9_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT10"
|
|
base ad:0xB480A800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT10_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB480A800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT10_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT10_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT10_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT10_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT11"
|
|
base ad:0xB480AC00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT11_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB480AC00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT11_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT11_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT11_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT11_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT12"
|
|
base ad:0xB4843800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT12_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4843800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT12_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT12_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT12_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT12_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT13"
|
|
base ad:0xB4843C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT13_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4843C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT13_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT13_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT13_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT13_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT14"
|
|
base ad:0xB4844000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT14_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4844000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT14_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT14_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT14_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT14_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT15"
|
|
base ad:0xB4844400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT15_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4844400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT15_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT15_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT15_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT15_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT16"
|
|
base ad:0xB4844800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT16_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4844800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT16_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT16_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT16_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT16_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT17"
|
|
base ad:0xB4844C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT17_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4844C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT17_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT17_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT17_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT17_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT18"
|
|
base ad:0xB4845000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT18_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4845000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT18_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT18_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT18_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT18_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT19"
|
|
base ad:0xB4889C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT19_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4889C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT19_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT19_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT19_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT19_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT20"
|
|
base ad:0xB4845800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT20_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4845800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT20_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT20_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT20_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT20_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT21"
|
|
base ad:0xB4845C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT21_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4845C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT21_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT21_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT21_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT21_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT22"
|
|
base ad:0xB4846000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT22_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4846000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT22_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT22_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT22_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT22_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT23"
|
|
base ad:0xB4846400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT23_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4846400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT23_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT23_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT23_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT23_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT24"
|
|
base ad:0xB4846800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT24_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4846800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT24_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT24_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT24_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT24_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT25"
|
|
base ad:0xB4846C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT25_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4846C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT25_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT25_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT25_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT25_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT26"
|
|
base ad:0xB4847000
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT26_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4847000+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT26_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT26_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT26_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT26_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT27"
|
|
base ad:0xB4847400
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT27_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4847400+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT27_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT27_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT27_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT27_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT28"
|
|
base ad:0xB4847800
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT28_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4847800+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT28_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT28_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT28_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT28_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree "BT29"
|
|
base ad:0xB4847C00
|
|
width 16.
|
|
hgroup.word 0x4++0x1
|
|
hide.word 0x00 "BT29_PWC_DTBF,Data Buffer Register"
|
|
in
|
|
if (((d.b(ad:0xB4847C00+0x11))&0x01)==0x00)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal,Internal/4,Internal/16,Internal/128,Internal/256,?..."
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "BT29_PWC_TMCR,Timer Control Register"
|
|
bitfld.word 0x00 12.--14. " CKS2_0 ,Count clock selection bits" "Internal/512,Internal/1024,Internal/2048,Internal/2,Internal/8,Internal/32,Internal/64,"
|
|
bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits [(R)ising/(F)alling]" "R to F,R to R,F to F,R or F to F or R,F to R,?..."
|
|
bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset mode,16-bit PWM,16-bit PPG,16/32-bit reload,16/32-bit PWC,,,"
|
|
bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot"
|
|
bitfld.word 0x00 1. " CTEN ,Timer enable bit" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "BT29_PWC_STC,Status Control Register"
|
|
rbitfld.byte 0x00 7. " ERR ,Error flag bit" "No error,Error"
|
|
setclrfld.byte 0x00 6. 0x08 6. 0x04 6. " EDIE_set/clr ,Measurement end interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.byte 0x00 4. 0x08 4. 0x04 4. " OVIE_set/clr ,Overflow interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " EDIR ,Measurement end interrupt request bit" "DTBF,Interrupt"
|
|
rbitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Interrupt"
|
|
group.byte 0x11++0x0
|
|
line.byte 0x00 "BT29_PWC_TMCR2,Timer Control Register 2"
|
|
bitfld.byte 0x00 0. " CKS3 ,Count clock selection bit" "0,1"
|
|
wgroup.byte 0x14++0x0
|
|
line.byte 0x00 "BT29_PWC_STCC,Status Control Clear Register"
|
|
bitfld.byte 0x00 0. " OVIRC ,Overflow interrupt request clear bit" ",Clear"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "BTSEL (base timer I/O selection function)"
|
|
tree "BT01"
|
|
base ad:0xB4808030
|
|
width 12.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL01,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
if (((d.l(ad:0xB4808030+0x00))&0xF)==(0x05||0x06))
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "BT_BTSSSR0,Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 11. " SSSR_[11] ,Simultaneous soft start bit 11" "No effect,Started"
|
|
bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "No effect,Started"
|
|
bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "No effect,Started"
|
|
bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "No effect,Started"
|
|
bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "No effect,Started"
|
|
bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "No effect,Started"
|
|
bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "No effect,Started"
|
|
bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "No effect,Started"
|
|
bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "No effect,Started"
|
|
bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "No effect,Started"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "No effect,Started"
|
|
else
|
|
hgroup.long 0x4++0x3
|
|
hide.long 0x00 "BT_BTSSSR0,Simultaneous Soft Start Register"
|
|
endif
|
|
tree.end
|
|
tree "BT23"
|
|
base ad:0xB4808830
|
|
width 12.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL23,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
tree.end
|
|
tree "BT45"
|
|
base ad:0xB4809030
|
|
width 12.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL45,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
tree.end
|
|
tree "BT67"
|
|
base ad:0xB4809830
|
|
width 12.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL67,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
tree.end
|
|
tree "BT89"
|
|
base ad:0xB480A030
|
|
width 12.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL89,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
tree.end
|
|
tree "BT1011"
|
|
base ad:0xB480A830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL1011,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" "16-bit timer standard mode,32-bit timer full-function mode,PPG trigger 2-channel sharing mode,,Timer start/stop mode,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,Timer start mode,?..."
|
|
tree.end
|
|
tree "BT1213"
|
|
base ad:0xB4843830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL1213,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
if (((d.l(ad:0xB4808030+0x00))&0xF)==(0x05||0x06))
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "BT_BTSSSR12,Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 11. " SSSR_[23] ,Simultaneous soft start bit 23" "No effect,Started"
|
|
bitfld.long 0x00 10. " [22] ,Simultaneous soft start bit 22" "No effect,Started"
|
|
bitfld.long 0x00 9. " [21] ,Simultaneous soft start bit 21" "No effect,Started"
|
|
bitfld.long 0x00 8. " [20] ,Simultaneous soft start bit 20" "No effect,Started"
|
|
bitfld.long 0x00 7. " [19] ,Simultaneous soft start bit 19" "No effect,Started"
|
|
bitfld.long 0x00 6. " [18] ,Simultaneous soft start bit 18" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [17] ,Simultaneous soft start bit 17" "No effect,Started"
|
|
bitfld.long 0x00 4. " [16] ,Simultaneous soft start bit 16" "No effect,Started"
|
|
bitfld.long 0x00 3. " [15] ,Simultaneous soft start bit 15" "No effect,Started"
|
|
bitfld.long 0x00 2. " [14] ,Simultaneous soft start bit 14" "No effect,Started"
|
|
bitfld.long 0x00 1. " [13] ,Simultaneous soft start bit 13" "No effect,Started"
|
|
bitfld.long 0x00 0. " [12] ,Simultaneous soft start bit 12" "No effect,Started"
|
|
else
|
|
hgroup.long 0x4++0x3
|
|
hide.long 0x00 "BT_BTSSSR12,Simultaneous Soft Start Register"
|
|
endif
|
|
tree.end
|
|
tree "BT1415"
|
|
base ad:0xB4844030
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL1415,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT1617"
|
|
base ad:0xB4844830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL1617,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT1819"
|
|
base ad:0xB4845030
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL1819,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT2021"
|
|
base ad:0xB4845830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL2021,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT2223"
|
|
base ad:0xB4846030
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL2223,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT2425"
|
|
base ad:0xB4846830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL2425,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
if (((d.l(ad:0xB4808030+0x00))&0xF)==(0x05||0x06))
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "BT_BTSSSR24,Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 5. " SSSR_[29] ,Simultaneous soft start bit 29" "No effect,Started"
|
|
bitfld.long 0x00 4. " [28] ,Simultaneous soft start bit 28" "No effect,Started"
|
|
bitfld.long 0x00 3. " [27] ,Simultaneous soft start bit 27" "No effect,Started"
|
|
bitfld.long 0x00 2. " [26] ,Simultaneous soft start bit 26" "No effect,Started"
|
|
bitfld.long 0x00 1. " [25] ,Simultaneous soft start bit 25" "No effect,Started"
|
|
bitfld.long 0x00 0. " [24] ,Simultaneous soft start bit 24" "No effect,Started"
|
|
else
|
|
hgroup.long 0x4++0x3
|
|
hide.long 0x00 "BT_BTSSSR24,Simultaneous Soft Start Register"
|
|
endif
|
|
tree.end
|
|
tree "BT2627"
|
|
base ad:0xB4847030
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL2627,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
tree "BT2829"
|
|
base ad:0xB4847830
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "BT_BTSEL2829,I/O Selection Register"
|
|
bitfld.long 0x00 0.--3. " BTSEL01 ,I/O mode selection bits" ",,,,,Simultaneous soft start mode,Timer start/stop and simultaneous soft start mode,?..."
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree.open "32-bit free-run timer"
|
|
tree "FRT00"
|
|
base ad:0xB4820000
|
|
width 8.
|
|
if (((d.l(ad:0xB4820000+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FRT01"
|
|
base ad:0xB4820400
|
|
width 8.
|
|
if (((d.l(ad:0xB4820400+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FRT02"
|
|
base ad:0xB4820800
|
|
width 8.
|
|
if (((d.l(ad:0xB4820800+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FRT03"
|
|
base ad:0xB4820C00
|
|
width 8.
|
|
if (((d.l(ad:0xB4820C00+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FRT04"
|
|
base ad:0xB4821000
|
|
width 8.
|
|
if (((d.l(ad:0xB4821000+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "FRT05"
|
|
base ad:0xB4821400
|
|
width 8.
|
|
if (((d.l(ad:0xB4821400+0x08))&0x80)==0x80)
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "CPCLRB,Compare Clear Buffer Register"
|
|
endif
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CPCLR,Compare Clear Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "TCDT,Timer Data Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "TCCS,Timer State Control Register"
|
|
setclrfld.long 0x00 15. 0x0C 15. 0x08 14. " ECKE_set/clr ,Clock selection bit" "Peripheral,External"
|
|
bitfld.long 0x00 14. " IRQZF ,0 detection interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 13. 0x0C 13. 0x08 13. " IRQZE_set/clr ,0 detection request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " MSI ,Interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,SIxth,Seventh,Eighth"
|
|
bitfld.long 0x00 9. " ICLR ,Compare clear interrupt flag bit" "Not detected,Detected"
|
|
setclrfld.long 0x00 8. 0x0C 9. 0x08 8. " ICRE_set/clr ,Compare clear interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x0C 7. 0x08 7. " BFE_set/clr ,Compare clear buffer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x0C 6. 0x08 6. " STOP_set/clr ,Timer enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x0C 5. 0x08 5. " MODE_set/clr ,Timer count mode bit" "Up count,Up/down count"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x0C 4. 0x00 4. " SCLR_set/clr ,Timer clear bit" "No effect,Cleared"
|
|
bitfld.long 0x00 0.--3. " CLK ,Clock frequency selection bits(clock count/40MHz/20MHz/10MHz/5MHz/2.5MHz)" "clock/1|25ns|50ns|100.0ns|200ns|400.00ns,clock/2|50ns|100ns|200ns|400ns|800.0ns,clock/4|100ns|200ns|400ns|800ns|1.6us,clock/8|100ns|400ns|800ns|1.6us|3.2us,clock/16|400ns|800ns|1.6us|3.2us|6.4us,clock/32|800ns|1.6us|3.2us|6.4us|12.8us,clock/64|1.6us|3.2us|6.4us|12.8us|25.6us,clock/128|3.2us|6.4us|12.8us|25.6us|51.2us,clock/256|6.4us|12.8us|25.6us|51.2us|102.4us,..."
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "TECCS,Timer Extended State Control Register"
|
|
bitfld.long 0x00 11. " MODE2 ,Interrupt mask mode bit 2" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " MSI ,Compare clear interrupt mask selection bits" "First,Second,Third,Fourth,Fifth,Sixth,Seventh,Eighth"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TCCSC,Timer State Control Clear Register"
|
|
bitfld.long 0x00 14. " IRQZFC ,0 detection interrupt flag clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ICLRC ,Compare clear interrupt flag clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "ICU (32-bit Input Capture)"
|
|
tree "ICU0"
|
|
base ad:0xB4828000
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU1"
|
|
base ad:0xB4828400
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU2"
|
|
base ad:0xB4828800
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU3"
|
|
base ad:0xB4828C00
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU4"
|
|
base ad:0xB4829000
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU5"
|
|
base ad:0xB4829400
|
|
width 7.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IPCP0,Input Capture Data Register 0"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IPCP1,Input Capture Data Register 1"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ICS,Input Capture State Control Register"
|
|
rbitfld.long 0x00 9. " IEI1 ,Valid edge indication bit (input capture 1)" "Falling,Raising"
|
|
rbitfld.long 0x00 8. " IEI0 ,Valid edge indication bit (input capture 0)" "Falling,Raising"
|
|
rbitfld.long 0x00 7. " ICP1 ,Interrupt request flag bit (input capture 1)" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x00 6. " ICP0 ,Interrupt request flag bit (input capture 0)" "Not detected,Detected"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " ICE1_SET/CLR ,Interrupt request enable bit (input capture 1)" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ICE0_SET/CLR ,Interrupt request enable bit (input capture 0)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " EG1 ,Edge selection bits (input capture 1)" "None,Rising,Falling,Both"
|
|
bitfld.long 0x00 0.--1. " EG0 ,Edge selection bits (input capture 0)" "None,Rising,Falling,Both"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "ICSC,Input Capture State Control Clear Register"
|
|
bitfld.long 0x00 7. " ICP1C ,ICP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " ICP0C ,ICP0 clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "OCU (32-bit Output Compare)"
|
|
tree "OCU0"
|
|
base ad:0xB4830000
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCU1"
|
|
base ad:0xB4830400
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCU2"
|
|
base ad:0xB4830800
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCU3"
|
|
base ad:0xB4830C00
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCU4"
|
|
base ad:0xB4831000
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "OCU5"
|
|
base ad:0xB4831400
|
|
width 8.
|
|
wgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCPB0,Output Compare Buffer Register 0"
|
|
line.long 0x04 "OCCPB1,Output Compare Buffer Register 1"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "OCCP0,Output Compare Register 0"
|
|
line.long 0x04 "OCCP1,Output Compare Register 1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OCS,Compare Control Register"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " BTS1_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " BTS0_SET/CLR ,Buffer transfer selection bit" "0,1"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " CMOD_SET/CLR ,Output level invert mode bit" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " OTD1_SET/CLR ,OUT1 output level bit" "0,1"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " OTD0_SET/CLR ,OUT0 output level bit" "0,1"
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 7. " IOP1 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
newline
|
|
sif cpuis("S6J342*")||cpuis("S6J35*")
|
|
rbitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
else
|
|
bitfld.long 0x00 6. " IOP0 ,Compare match interrupt flag bit" "Not detected,Detected"
|
|
endif
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " IOE1_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " IOE0_SET/CLR ,Compare match interrupt enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BUF1_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " BUF0_SET/CLR ,Compare buffer disable bit" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " CST1_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " CST0_SET/CLR ,Compare operation enable bit" "Disabled,Enabled"
|
|
sif cpuis("S6J342*")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "OCSC,Compare Control Clear Register"
|
|
bitfld.long 0x00 7. " IOP1C ,IOP1 clear bit" "No effect,Clear"
|
|
bitfld.long 0x00 6. " IOP0C ,IOP0 clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("S6J312?HAA")
|
|
tree.open "RLT (32-bit Reload Timer)"
|
|
tree "RLT0"
|
|
base ad:0xB4810000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT0_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810000+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4810000+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT0_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT0_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT0_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT1"
|
|
base ad:0xB4810400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT1_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810400+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4810400+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT1_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT1_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT1_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT2"
|
|
base ad:0xB4810800
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT2_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810800+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4810800+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT2_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT2_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT2_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT3"
|
|
base ad:0xB4810C00
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT3_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4810C00+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4810C00+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT3_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT3_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT3_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT16"
|
|
base ad:0xB4890000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT16_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890000+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4890000+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT16_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT16_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT16_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT17"
|
|
base ad:0xB4890400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT17_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890400+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4890400+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT17_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT17_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT17_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT18"
|
|
base ad:0xB4890800
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT18_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4890800+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890800+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4890800+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT18_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT18_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT18_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT19"
|
|
base ad:0xB4890C00
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT19_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4890C00+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4890C00+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4890C00+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT19_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT19_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT19_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT32"
|
|
base ad:0xB4788000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT32_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4788000+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788000+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4788000+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT32_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT32_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT32_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT33"
|
|
base ad:0xB4788400
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RLT33_DMACFG,DMA Configuration Register"
|
|
bitfld.long 0x00 0. " ENDMAUF ,DMA enable for underflow" "Disabled,Enabled"
|
|
sif (cpuis("S6J33*"))
|
|
if (((per.l(ad:0xB4788400+0x08))&0x1001810)==0x1001810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x1001810)==0x1001800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x1000010)==0x1000010)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x1000010)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
newline
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x1810)==0x1810)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x1810)==0x1800)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--14. " MOD ,Operation mode" ",Event/Rising,Event/Falling,Event/Both"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xB4788400+0x08))&0x10)==0x10)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "Start Low,Start High"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "Disabled,Trigger/Rising,Trigger/Falling,Trigger/Both,Gate/Low,Gate/High,Gate/Low,Gate/High"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "/1,/2,/4,/8,/16,/32,Event on TIN,Second event on TIN"
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "High,Low"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
newline
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xB4788400+0x08))&0x1000000)==0x1000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TRG ,Trigger" "No effect,Trigger"
|
|
bitfld.long 0x00 17. " UFCLR ,Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RLT33_TMCSR,Timer Control Status Register"
|
|
bitfld.long 0x00 24. " CNTE ,Count enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " UFCLR , Underflow interrupt clear" "No effect,Clear"
|
|
newline
|
|
rbitfld.long 0x00 16. " UF ,Underflow" "No,Yes"
|
|
bitfld.long 0x00 13.--15. " MOD ,Operation mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 10.--12. " CSL ,Clock select" "1/1,1/2,1/4,1/8,1/16,1/32,Event on TIN,Second event on TIN"
|
|
newline
|
|
bitfld.long 0x00 8. " NFE ,Noise filter enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("S6J312?HAA")
|
|
bitfld.long 0x00 7. " DBGE ,Debug mode enable" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 5. " OUTL ,Output level" "0,1"
|
|
bitfld.long 0x00 4. " RELD ,Reload" "One-shot,Reload"
|
|
bitfld.long 0x00 3. " INTE ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RLT33_TMRLR,32-Bit Reload Register"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RLT33_TMR,32-Bit Timer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "RLTSSS (Reload Timer Simultaneous Soft Start)"
|
|
tree "RLT0"
|
|
base ad:0xB483FC00
|
|
width 6.
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
bitfld.long 0x00 3. " TSEL_[3] ,Trigger selection bit 3 (Channel 3)" "External,Software"
|
|
bitfld.long 0x00 2. " [2] ,Trigger selection bit 2 (Channel 2)" "External,Software"
|
|
bitfld.long 0x00 1. " [1] ,Trigger selection bit 1 (Channel 1)" "External,Software"
|
|
bitfld.long 0x00 0. " [0] ,Trigger selection bit 0 (Channel 0)" "External,Software"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software"
|
|
bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software"
|
|
bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software"
|
|
bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software"
|
|
bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software"
|
|
bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software"
|
|
bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software"
|
|
bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software"
|
|
bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software"
|
|
bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software"
|
|
bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software"
|
|
bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software"
|
|
bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software"
|
|
endif
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 3. " SSSR_[3] ,Simultaneous soft start bit 3 (Channel 3)" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2 (Channel 2)" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1 (Channel 1)" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0 (Channel 0)" "Not active,Active"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT1"
|
|
base ad:0xB48BFC00
|
|
width 6.
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
bitfld.long 0x00 1. " TSEL_[1] ,Trigger selection bit 1 (Channel 17)" "External,Software"
|
|
bitfld.long 0x00 0. " [0] ,Trigger selection bit 0 (Channel 16)" "External,Software"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software"
|
|
bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software"
|
|
bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software"
|
|
bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software"
|
|
bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software"
|
|
bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software"
|
|
bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software"
|
|
bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software"
|
|
bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software"
|
|
bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software"
|
|
bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software"
|
|
bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software"
|
|
bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software"
|
|
endif
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 1. " SSSR_[1] ,Simultaneous soft start bit 1 (Channel 17)" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0 (Channel 16)" "Not active,Active"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RLT2"
|
|
base ad:0xB478FC00
|
|
width 6.
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSEL,Reload Timer Trigger Selection Register"
|
|
bitfld.long 0x00 15. " TSEL_[15] ,Trigger selection bit 15" "External,Software"
|
|
bitfld.long 0x00 14. " [14] ,Trigger selection bit 14" "External,Software"
|
|
bitfld.long 0x00 13. " [13] ,Trigger selection bit 13" "External,Software"
|
|
bitfld.long 0x00 12. " [12] ,Trigger selection bit 12" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Trigger selection bit 11" "External,Software"
|
|
bitfld.long 0x00 10. " [10] ,Trigger selection bit 10" "External,Software"
|
|
bitfld.long 0x00 9. " [9] ,Trigger selection bit 9" "External,Software"
|
|
bitfld.long 0x00 8. " [8] ,Trigger selection bit 8" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Trigger selection bit 7" "External,Software"
|
|
bitfld.long 0x00 6. " [6] ,Trigger selection bit 6" "External,Software"
|
|
bitfld.long 0x00 5. " [5] ,Trigger selection bit 5" "External,Software"
|
|
bitfld.long 0x00 4. " [4] ,Trigger selection bit 4" "External,Software"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Trigger selection bit 3" "External,Software"
|
|
bitfld.long 0x00 2. " [2] ,Trigger selection bit 2" "External,Software"
|
|
bitfld.long 0x00 1. " [1] ,Trigger selection bit 1" "External,Software"
|
|
bitfld.long 0x00 0. " [0] ,Trigger selection bit 0" "External,Software"
|
|
endif
|
|
sif cpuis("S6J336*")||cpuis("S6J337*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSSR,Reload Timer Simultaneous Soft Start Register"
|
|
bitfld.long 0x00 15. " SSSR_[15] ,Simultaneous soft start bit 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Simultaneous soft start bit 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Simultaneous soft start bit 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Simultaneous soft start bit 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Simultaneous soft start bit 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Simultaneous soft start bit 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Simultaneous soft start bit 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Simultaneous soft start bit 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Simultaneous soft start bit 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Simultaneous soft start bit 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Simultaneous soft start bit 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Simultaneous soft start bit 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Simultaneous soft start bit 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Simultaneous soft start bit 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Simultaneous soft start bit 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Simultaneous soft start bit 0" "Not active,Active"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "QC (QUAD POSITION & REVOLUTION COUTER)"
|
|
tree "QC08"
|
|
base ad:0xB4818000
|
|
width 12.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "QC08_QPCR,Quad Position & Revolution Counter Position Count Register"
|
|
group.word 0x2++0x1
|
|
line.word 0x00 "QC08_QRCR,QPRC Revolution Count Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "QC08_QPCCR,QPRC Position Counter Compare Register"
|
|
group.word 0x6++0x1
|
|
line.word 0x00 "QC08_QPRCR,QPRC Position and Revolution Counter Compare Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "QC08_QMPR,QPRC Maximum Position Register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x00 "QC08_QICRL,Low-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not compared,Compared"
|
|
bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled"
|
|
group.byte 0xB++0x0
|
|
line.byte 0x00 "QC08_QICRH,High-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 5. " QPCNRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented"
|
|
bitfld.byte 0x00 1. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled"
|
|
if ((d.l(ad:0xB4818000+0x0C)&0x20)==0x20)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "QC08_QCR,QPRC Control Register"
|
|
bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled"
|
|
bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAP ,Swap bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate"
|
|
bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "QC08_QCR,QPRC Control Register"
|
|
bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAP ,Swap bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate"
|
|
bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3"
|
|
endif
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "QC08_QECR,QPRC Extension Control Register"
|
|
bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "QC09"
|
|
base ad:0xB4818400
|
|
width 12.
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "QC09_QPCR,Quad Position & Revolution Counter Position Count Register"
|
|
group.word 0x2++0x1
|
|
line.word 0x00 "QC09_QRCR,QPRC Revolution Count Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "QC09_QPCCR,QPRC Position Counter Compare Register"
|
|
group.word 0x6++0x1
|
|
line.word 0x00 "QC09_QPRCR,QPRC Position and Revolution Counter Compare Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x00 "QC09_QMPR,QPRC Maximum Position Register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x00 "QC09_QICRL,Low-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " OUZIE ,Overflow/Underflow/Zero index interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched"
|
|
bitfld.byte 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not compared,Compared"
|
|
bitfld.byte 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled"
|
|
group.byte 0xB++0x0
|
|
line.byte 0x00 "QC09_QICRH,High-Order Bytes of QPRC Interrupt Control Register"
|
|
bitfld.byte 0x00 5. " QPCNRCMF ,PC and RC match interrupt request flag bit" "Not matched,Matched"
|
|
bitfld.byte 0x00 4. " QPCNRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DIRPC ,Last position counter direction bit" "Incremented,Decremented"
|
|
bitfld.byte 0x00 1. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled"
|
|
if ((d.l(ad:0xB4818400+0x0C)&0x20)==0x20)
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "QC09_QCR,QPRC Control Register"
|
|
bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Low,High,Disabled"
|
|
bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAP ,Swap bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate"
|
|
bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3"
|
|
else
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "QC09_QCR,QPRC Control Register"
|
|
bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling"
|
|
bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Both"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "0,1,2,3"
|
|
bitfld.word 0x00 7. " SWAP ,Swap bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Clear,Gate"
|
|
bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "0,1,2,3"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "0,1,2,3"
|
|
endif
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "QC09_QECR,QPRC Extension Control Register"
|
|
bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "EICU (External Interrupt Capture Unit)"
|
|
base ad:0xB0688000
|
|
width 13.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "EICU0_CNFGR,Configuration Register"
|
|
bitfld.long 0x00 26. " IRQEN ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " OBSEN ,Observation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DATARESET ,Data Reset" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " DATAVALID ,Data valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 22. " BUSY ,Sampling status" "Not ongoing,Ongoing"
|
|
rbitfld.long 0x00 16.--20. " OBSCH ,Observed channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2.--7. " PRESCALE ,Prescale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--1. " CLKSEL ,Clock select" "Slow RC,Fast RC,Main,"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "EICU0_IRENR,External Interrupt Pin Enable Register"
|
|
bitfld.long 0x00 31. " IREN_[31] ,External interrupt pin observe enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,External interrupt pin observe enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,External interrupt pin observe enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,External interrupt pin observe enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,External interrupt pin observe enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,External interrupt pin observe enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,External interrupt pin observe enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,External interrupt pin observe enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,External interrupt pin observe enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,External interrupt pin observe enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,External interrupt pin observe enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,External interrupt pin observe enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,External interrupt pin observe enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,External interrupt pin observe enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,External interrupt pin observe enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,External interrupt pin observe enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,External interrupt pin observe enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,External interrupt pin observe enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,External interrupt pin observe enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,External interrupt pin observe enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,External interrupt pin observe enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,External interrupt pin observe enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,External interrupt pin observe enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,External interrupt pin observe enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,External interrupt pin observe enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,External interrupt pin observe enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,External interrupt pin observe enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,External interrupt pin observe enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,External interrupt pin observe enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,External interrupt pin observe enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,External interrupt pin observe enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,External interrupt pin observe enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
if (((d.l(ad:0xB0688000))&0x800000)==0x800000)
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "EICU0_SPLR0,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[31] ,Sample bit 31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Sample bit 30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Sample bit 29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Sample bit 28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [27] ,Sample bit 27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [26] ,Sample bit 26" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [25] ,Sample bit 25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Sample bit 24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [23] ,Sample bit 23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Sample bit 22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [21] ,Sample bit 21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Sample bit 20" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Sample bit 19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Sample bit 18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Sample bit 17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [16] ,Sample bit 16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [15] ,Sample bit 15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Sample bit 14" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [13] ,Sample bit 13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Sample bit 12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [11] ,Sample bit 11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Sample bit 10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Sample bit 9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Sample bit 8" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Sample bit 7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [6] ,Sample bit 6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Sample bit 5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Sample bit 4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Sample bit 3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Sample bit 2" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Sample bit 1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Sample bit 0" "Not occurred,Occurred"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x00 "EICU0_SPLR1,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[63] ,Sample bit 63" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [62] ,Sample bit 62" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [61] ,Sample bit 61" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [60] ,Sample bit 60" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [59] ,Sample bit 59" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [58] ,Sample bit 58" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [57] ,Sample bit 57" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [56] ,Sample bit 56" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [55] ,Sample bit 55" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [54] ,Sample bit 54" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [53] ,Sample bit 53" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [52] ,Sample bit 52" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Sample bit 51" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [50] ,Sample bit 50" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [49] ,Sample bit 49" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [48] ,Sample bit 48" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [47] ,Sample bit 47" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [46] ,Sample bit 46" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [45] ,Sample bit 45" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [44] ,Sample bit 44" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [43] ,Sample bit 43" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [42] ,Sample bit 42" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [41] ,Sample bit 41" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [40] ,Sample bit 40" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Sample bit 39" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [38] ,Sample bit 38" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [37] ,Sample bit 37" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [36] ,Sample bit 36" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [35] ,Sample bit 35" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [34] ,Sample bit 34" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [33] ,Sample bit 33" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [32] ,Sample bit 32" "Not occurred,Occurred"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "EICU0_SPLR2,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[95] ,Sample bit 95" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [94] ,Sample bit 94" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [93] ,Sample bit 93" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [92] ,Sample bit 92" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [91] ,Sample bit 91" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [90] ,Sample bit 90" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [89] ,Sample bit 89" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [88] ,Sample bit 88" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [87] ,Sample bit 87" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [86] ,Sample bit 86" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [85] ,Sample bit 85" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [84] ,Sample bit 84" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [83] ,Sample bit 83" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [82] ,Sample bit 82" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [81] ,Sample bit 81" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [80] ,Sample bit 80" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [79] ,Sample bit 79" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [78] ,Sample bit 78" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [77] ,Sample bit 77" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [76] ,Sample bit 76" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [75] ,Sample bit 75" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [74] ,Sample bit 74" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [73] ,Sample bit 73" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [72] ,Sample bit 72" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [71] ,Sample bit 71" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [70] ,Sample bit 70" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [69] ,Sample bit 69" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [68] ,Sample bit 68" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [67] ,Sample bit 67" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [66] ,Sample bit 66" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [65] ,Sample bit 65" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [64] ,Sample bit 64" "Not occurred,Occurred"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "EICU0_SPLR3,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[127] ,Sample bit 127" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [126] ,Sample bit 126" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [125] ,Sample bit 125" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [124] ,Sample bit 124" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [123] ,Sample bit 123" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [122] ,Sample bit 122" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [121] ,Sample bit 121" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [120] ,Sample bit 120" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [119] ,Sample bit 119" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [118] ,Sample bit 118" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [117] ,Sample bit 117" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [116] ,Sample bit 116" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [115] ,Sample bit 115" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [114] ,Sample bit 114" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [113] ,Sample bit 113" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [112] ,Sample bit 112" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [111] ,Sample bit 111" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [110] ,Sample bit 110" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [109] ,Sample bit 109" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [108] ,Sample bit 108" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [107] ,Sample bit 107" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [106] ,Sample bit 106" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [105] ,Sample bit 105" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [104] ,Sample bit 104" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [103] ,Sample bit 103" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [102] ,Sample bit 102" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [101] ,Sample bit 101" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [100] ,Sample bit 100" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [99] ,Sample bit 99" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [98] ,Sample bit 98" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [97] ,Sample bit 97" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [96] ,Sample bit 96" "Not occurred,Occurred"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "EICU0_SPLR4,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[159] ,Sample bit 159" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [158] ,Sample bit 158" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [157] ,Sample bit 157" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [156] ,Sample bit 156" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [155] ,Sample bit 155" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [154] ,Sample bit 154" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [153] ,Sample bit 153" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [152] ,Sample bit 152" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [151] ,Sample bit 151" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [150] ,Sample bit 150" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [149] ,Sample bit 149" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [148] ,Sample bit 148" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [147] ,Sample bit 147" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [146] ,Sample bit 146" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [145] ,Sample bit 145" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [144] ,Sample bit 144" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [143] ,Sample bit 143" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [142] ,Sample bit 142" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [141] ,Sample bit 141" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [140] ,Sample bit 140" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [139] ,Sample bit 139" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [138] ,Sample bit 138" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [137] ,Sample bit 137" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [136] ,Sample bit 136" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [135] ,Sample bit 135" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [134] ,Sample bit 134" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [133] ,Sample bit 133" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [132] ,Sample bit 132" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [131] ,Sample bit 131" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [130] ,Sample bit 130" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [129] ,Sample bit 129" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [128] ,Sample bit 128" "Not occurred,Occurred"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "EICU0_SPLR5,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[191] ,Sample bit 191" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [190] ,Sample bit 190" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [189] ,Sample bit 189" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [188] ,Sample bit 188" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [187] ,Sample bit 187" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [186] ,Sample bit 186" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [185] ,Sample bit 185" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [184] ,Sample bit 184" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [183] ,Sample bit 183" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [182] ,Sample bit 182" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [181] ,Sample bit 181" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [180] ,Sample bit 180" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [179] ,Sample bit 179" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [178] ,Sample bit 178" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [177] ,Sample bit 177" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [176] ,Sample bit 176" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [175] ,Sample bit 175" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [174] ,Sample bit 174" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [173] ,Sample bit 173" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [172] ,Sample bit 172" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [171] ,Sample bit 171" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [170] ,Sample bit 170" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [169] ,Sample bit 169" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [168] ,Sample bit 168" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [167] ,Sample bit 167" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [166] ,Sample bit 166" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [165] ,Sample bit 165" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [164] ,Sample bit 164" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [163] ,Sample bit 163" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [162] ,Sample bit 162" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [161] ,Sample bit 161" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [160] ,Sample bit 160" "Not occurred,Occurred"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "EICU0_SPLR6,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[223] ,Sample bit 223" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [222] ,Sample bit 222" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [221] ,Sample bit 221" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [220] ,Sample bit 220" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [219] ,Sample bit 219" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [218] ,Sample bit 218" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [217] ,Sample bit 217" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [216] ,Sample bit 216" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [215] ,Sample bit 215" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [214] ,Sample bit 214" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [213] ,Sample bit 213" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [212] ,Sample bit 212" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [211] ,Sample bit 211" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [210] ,Sample bit 210" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [209] ,Sample bit 209" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [208] ,Sample bit 208" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [207] ,Sample bit 207" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [206] ,Sample bit 206" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [205] ,Sample bit 205" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [204] ,Sample bit 204" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [203] ,Sample bit 203" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [202] ,Sample bit 202" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [201] ,Sample bit 201" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [200] ,Sample bit 200" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [199] ,Sample bit 199" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [198] ,Sample bit 198" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [197] ,Sample bit 197" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [196] ,Sample bit 196" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [195] ,Sample bit 195" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [194] ,Sample bit 194" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [193] ,Sample bit 193" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [192] ,Sample bit 192" "Not occurred,Occurred"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "EICU0_SPLR7,Sample Register"
|
|
bitfld.long 0x00 31. " SPL_[255] ,Sample bit 255" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [254] ,Sample bit 254" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [253] ,Sample bit 253" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [252] ,Sample bit 252" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [251] ,Sample bit 251" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [250] ,Sample bit 250" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 25. " [249] ,Sample bit 249" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [248] ,Sample bit 248" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [247] ,Sample bit 247" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [246] ,Sample bit 246" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [245] ,Sample bit 245" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [244] ,Sample bit 244" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [243] ,Sample bit 243" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [242] ,Sample bit 242" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [241] ,Sample bit 241" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [240] ,Sample bit 240" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [239] ,Sample bit 239" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [238] ,Sample bit 238" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 13. " [237] ,Sample bit 237" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [236] ,Sample bit 236" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " [235] ,Sample bit 235" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [234] ,Sample bit 234" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [233] ,Sample bit 233" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [232] ,Sample bit 232" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [231] ,Sample bit 231" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [230] ,Sample bit 230" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [229] ,Sample bit 229" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [228] ,Sample bit 228" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [227] ,Sample bit 227" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [226] ,Sample bit 226" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [225] ,Sample bit 225" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [224] ,Sample bit 224" "Not occurred,Occurred"
|
|
else
|
|
hgroup.long 0x8++0x3
|
|
hide.long 0x00 "EICU0_SPLR0,Sample Register"
|
|
hgroup.long 0xC++0x3
|
|
hide.long 0x00 "EICU0_SPLR1,Sample Register"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "EICU0_SPLR2,Sample Register"
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "EICU0_SPLR3,Sample Register"
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x00 "EICU0_SPLR4,Sample Register"
|
|
hgroup.long 0x1C++0x3
|
|
hide.long 0x00 "EICU0_SPLR5,Sample Register"
|
|
hgroup.long 0x20++0x3
|
|
hide.long 0x00 "EICU0_SPLR6,Sample Register"
|
|
hgroup.long 0x24++0x3
|
|
hide.long 0x00 "EICU0_SPLR7,Sample Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.open "CRC (Cyclic Redundancy Check)"
|
|
tree "CRC0"
|
|
base ad:0xB4718000
|
|
width 15.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRC0_CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled"
|
|
if (((d.b(ad:0xB4718000))&0x2)==0x00)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC0_CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC0_CRCINIT,Initial Value Register"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CRC0_CRCIN,Input Data Register"
|
|
if (((d.b(ad:0xB4718000))&0x12)==0x00)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC0_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits"
|
|
elif (((d.b(ad:0xB4718000))&0x12)==0x10)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC0_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC0_CRCR,CRC Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC1"
|
|
base ad:0xB4718400
|
|
width 15.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRC1_CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled"
|
|
if (((d.b(ad:0xB4718400))&0x2)==0x00)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC1_CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC1_CRCINIT,Initial Value Register"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CRC1_CRCIN,Input Data Register"
|
|
if (((d.b(ad:0xB4718400))&0x12)==0x00)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC1_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits"
|
|
elif (((d.b(ad:0xB4718400))&0x12)==0x10)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC1_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC1_CRCR,CRC Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC2"
|
|
base ad:0xB4718800
|
|
width 15.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRC2_CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled"
|
|
if (((d.b(ad:0xB4718800))&0x2)==0x00)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC2_CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC2_CRCINIT,Initial Value Register"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CRC2_CRCIN,Input Data Register"
|
|
if (((d.b(ad:0xB4718800))&0x12)==0x00)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC2_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits"
|
|
elif (((d.b(ad:0xB4718800))&0x12)==0x10)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC2_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC2_CRCR,CRC Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC3"
|
|
base ad:0xB4718C00
|
|
width 15.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CRC3_CRCCR,CRC Control Register"
|
|
bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Available"
|
|
bitfld.byte 0x00 5. " CRCLSF ,CRC result bit order setting bit" "MSB,LSB"
|
|
bitfld.byte 0x00 4. " CRCLTE ,CRC result byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 3. " LSBFST ,Bit order setting bit" "MSB,LSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " LTLEND ,Byte order setting bit" "Big endian,Little endian"
|
|
bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "16,32"
|
|
bitfld.byte 0x00 0. " INIT ,Initialization bit" "Disabled,Enabled"
|
|
if (((d.b(ad:0xB4718C00))&0x2)==0x00)
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC3_CRCINIT,Initial Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC initial value bits"
|
|
else
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CRC3_CRCINIT,Initial Value Register"
|
|
endif
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "CRC3_CRCIN,Input Data Register"
|
|
if (((d.b(ad:0xB4718C00))&0x12)==0x00)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC3_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " D ,CRC result bits"
|
|
elif (((d.b(ad:0xB4718C00))&0x12)==0x10)
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC3_CRCR,CRC Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " D ,CRC result bits"
|
|
else
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "CRC3_CRCR,CRC Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "I/O port"
|
|
tree "GPIO"
|
|
base ad:0xB4738000
|
|
width 13.
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "GPIO_DDR0,Data Direction Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD_set/clr_[31] ,Data direction selection bit 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD_set/clr_[30] ,Data direction selection bit 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD_set/clr_[29] ,Data direction selection bit 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD_set/clr_[28] ,Data direction selection bit 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD_set/clr_[27] ,Data direction selection bit 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD_set/clr_[26] ,Data direction selection bit 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD_set/clr_[25] ,Data direction selection bit 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD_set/clr_[24] ,Data direction selection bit 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD_set/clr_[23] ,Data direction selection bit 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD_set/clr_[22] ,Data direction selection bit 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD_set/clr_[21] ,Data direction selection bit 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD_set/clr_[20] ,Data direction selection bit 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD_set/clr_[19] ,Data direction selection bit 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD_set/clr_[18] ,Data direction selection bit 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD_set/clr_[17] ,Data direction selection bit 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD_set/clr_[16] ,Data direction selection bit 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD_set/clr_[15] ,Data direction selection bit 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD_set/clr_[14] ,Data direction selection bit 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD_set/clr_[13] ,Data direction selection bit 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD_set/clr_[12] ,Data direction selection bit 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD_set/clr_[11] ,Data direction selection bit 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD_set/clr_[10] ,Data direction selection bit 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD_set/clr_[9] ,Data direction selection bit 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD_set/clr_[8] ,Data direction selection bit 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD_set/clr_[7] ,Data direction selection bit 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD_set/clr_[6] ,Data direction selection bit 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD_set/clr_[5] ,Data direction selection bit 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD_set/clr_[4] ,Data direction selection bit 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD_set/clr_[3] ,Data direction selection bit 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD_set/clr_[2] ,Data direction selection bit 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD_set/clr_[1] ,Data direction selection bit 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD_set/clr_[0] ,Data direction selection bit 0" "Input,Output"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "GPIO_DDR1,Data Direction Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD_set/clr_[31] ,Data direction selection bit 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD_set/clr_[30] ,Data direction selection bit 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD_set/clr_[29] ,Data direction selection bit 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD_set/clr_[28] ,Data direction selection bit 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD_set/clr_[27] ,Data direction selection bit 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD_set/clr_[26] ,Data direction selection bit 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD_set/clr_[25] ,Data direction selection bit 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD_set/clr_[24] ,Data direction selection bit 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD_set/clr_[23] ,Data direction selection bit 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD_set/clr_[22] ,Data direction selection bit 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD_set/clr_[21] ,Data direction selection bit 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD_set/clr_[20] ,Data direction selection bit 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD_set/clr_[19] ,Data direction selection bit 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD_set/clr_[18] ,Data direction selection bit 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD_set/clr_[17] ,Data direction selection bit 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD_set/clr_[16] ,Data direction selection bit 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD_set/clr_[15] ,Data direction selection bit 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD_set/clr_[14] ,Data direction selection bit 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD_set/clr_[13] ,Data direction selection bit 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD_set/clr_[12] ,Data direction selection bit 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD_set/clr_[11] ,Data direction selection bit 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD_set/clr_[10] ,Data direction selection bit 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD_set/clr_[9] ,Data direction selection bit 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD_set/clr_[8] ,Data direction selection bit 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD_set/clr_[7] ,Data direction selection bit 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD_set/clr_[6] ,Data direction selection bit 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD_set/clr_[5] ,Data direction selection bit 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD_set/clr_[4] ,Data direction selection bit 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD_set/clr_[3] ,Data direction selection bit 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD_set/clr_[2] ,Data direction selection bit 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD_set/clr_[1] ,Data direction selection bit 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD_set/clr_[0] ,Data direction selection bit 0" "Input,Output"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "GPIO_DDR2,Data Direction Set/Clear Register 2"
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD_set/clr_[31] ,Data direction selection bit 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD_set/clr_[30] ,Data direction selection bit 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD_set/clr_[29] ,Data direction selection bit 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD_set/clr_[28] ,Data direction selection bit 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD_set/clr_[27] ,Data direction selection bit 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD_set/clr_[26] ,Data direction selection bit 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD_set/clr_[25] ,Data direction selection bit 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD_set/clr_[24] ,Data direction selection bit 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD_set/clr_[23] ,Data direction selection bit 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD_set/clr_[22] ,Data direction selection bit 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD_set/clr_[21] ,Data direction selection bit 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD_set/clr_[20] ,Data direction selection bit 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD_set/clr_[19] ,Data direction selection bit 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD_set/clr_[18] ,Data direction selection bit 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD_set/clr_[17] ,Data direction selection bit 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD_set/clr_[16] ,Data direction selection bit 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD_set/clr_[15] ,Data direction selection bit 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD_set/clr_[14] ,Data direction selection bit 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD_set/clr_[13] ,Data direction selection bit 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD_set/clr_[12] ,Data direction selection bit 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD_set/clr_[11] ,Data direction selection bit 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD_set/clr_[10] ,Data direction selection bit 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD_set/clr_[9] ,Data direction selection bit 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD_set/clr_[8] ,Data direction selection bit 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD_set/clr_[7] ,Data direction selection bit 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD_set/clr_[6] ,Data direction selection bit 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD_set/clr_[5] ,Data direction selection bit 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD_set/clr_[4] ,Data direction selection bit 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD_set/clr_[3] ,Data direction selection bit 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD_set/clr_[2] ,Data direction selection bit 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD_set/clr_[1] ,Data direction selection bit 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD_set/clr_[0] ,Data direction selection bit 0" "Input,Output"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "GPIO_DDR3,Data Direction Set/Clear Register 3"
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD_set/clr_[31] ,Data direction selection bit 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD_set/clr_[30] ,Data direction selection bit 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD_set/clr_[29] ,Data direction selection bit 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD_set/clr_[28] ,Data direction selection bit 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD_set/clr_[27] ,Data direction selection bit 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD_set/clr_[26] ,Data direction selection bit 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD_set/clr_[25] ,Data direction selection bit 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD_set/clr_[24] ,Data direction selection bit 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD_set/clr_[23] ,Data direction selection bit 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD_set/clr_[22] ,Data direction selection bit 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD_set/clr_[21] ,Data direction selection bit 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD_set/clr_[20] ,Data direction selection bit 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD_set/clr_[19] ,Data direction selection bit 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD_set/clr_[18] ,Data direction selection bit 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD_set/clr_[17] ,Data direction selection bit 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD_set/clr_[16] ,Data direction selection bit 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD_set/clr_[15] ,Data direction selection bit 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD_set/clr_[14] ,Data direction selection bit 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD_set/clr_[13] ,Data direction selection bit 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD_set/clr_[12] ,Data direction selection bit 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD_set/clr_[11] ,Data direction selection bit 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD_set/clr_[10] ,Data direction selection bit 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD_set/clr_[9] ,Data direction selection bit 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD_set/clr_[8] ,Data direction selection bit 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD_set/clr_[7] ,Data direction selection bit 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD_set/clr_[6] ,Data direction selection bit 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD_set/clr_[5] ,Data direction selection bit 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD_set/clr_[4] ,Data direction selection bit 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD_set/clr_[3] ,Data direction selection bit 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD_set/clr_[2] ,Data direction selection bit 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD_set/clr_[1] ,Data direction selection bit 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD_set/clr_[0] ,Data direction selection bit 0" "Input,Output"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "GPIO_DDR4,Data Direction Set/Clear Register 4"
|
|
setclrfld.long 0x00 31. -0x1FC 31. -0x1F8 31. " DD_set/clr_[31] ,Data direction selection bit 31" "Input,Output"
|
|
setclrfld.long 0x00 30. -0x1FC 30. -0x1F8 30. " DD_set/clr_[30] ,Data direction selection bit 30" "Input,Output"
|
|
setclrfld.long 0x00 29. -0x1FC 29. -0x1F8 29. " DD_set/clr_[29] ,Data direction selection bit 29" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x1FC 28. -0x1F8 28. " DD_set/clr_[28] ,Data direction selection bit 28" "Input,Output"
|
|
setclrfld.long 0x00 27. -0x1FC 27. -0x1F8 27. " DD_set/clr_[27] ,Data direction selection bit 27" "Input,Output"
|
|
setclrfld.long 0x00 26. -0x1FC 26. -0x1F8 26. " DD_set/clr_[26] ,Data direction selection bit 26" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x1FC 25. -0x1F8 25. " DD_set/clr_[25] ,Data direction selection bit 25" "Input,Output"
|
|
setclrfld.long 0x00 24. -0x1FC 24. -0x1F8 24. " DD_set/clr_[24] ,Data direction selection bit 24" "Input,Output"
|
|
setclrfld.long 0x00 23. -0x1FC 23. -0x1F8 23. " DD_set/clr_[23] ,Data direction selection bit 23" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x1FC 22. -0x1F8 22. " DD_set/clr_[22] ,Data direction selection bit 22" "Input,Output"
|
|
setclrfld.long 0x00 21. -0x1FC 21. -0x1F8 21. " DD_set/clr_[21] ,Data direction selection bit 21" "Input,Output"
|
|
setclrfld.long 0x00 20. -0x1FC 20. -0x1F8 20. " DD_set/clr_[20] ,Data direction selection bit 20" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x1FC 19. -0x1F8 19. " DD_set/clr_[19] ,Data direction selection bit 19" "Input,Output"
|
|
setclrfld.long 0x00 18. -0x1FC 18. -0x1F8 18. " DD_set/clr_[18] ,Data direction selection bit 18" "Input,Output"
|
|
setclrfld.long 0x00 17. -0x1FC 17. -0x1F8 17. " DD_set/clr_[17] ,Data direction selection bit 17" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x1FC 16. -0x1F8 16. " DD_set/clr_[16] ,Data direction selection bit 16" "Input,Output"
|
|
setclrfld.long 0x00 15. -0x1FC 15. -0x1F8 15. " DD_set/clr_[15] ,Data direction selection bit 15" "Input,Output"
|
|
setclrfld.long 0x00 14. -0x1FC 14. -0x1F8 14. " DD_set/clr_[14] ,Data direction selection bit 14" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x1FC 13. -0x1F8 13. " DD_set/clr_[13] ,Data direction selection bit 13" "Input,Output"
|
|
setclrfld.long 0x00 12. -0x1FC 12. -0x1F8 12. " DD_set/clr_[12] ,Data direction selection bit 12" "Input,Output"
|
|
setclrfld.long 0x00 11. -0x1FC 11. -0x1F8 11. " DD_set/clr_[11] ,Data direction selection bit 11" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x1FC 10. -0x1F8 10. " DD_set/clr_[10] ,Data direction selection bit 10" "Input,Output"
|
|
setclrfld.long 0x00 9. -0x1FC 9. -0x1F8 9. " DD_set/clr_[9] ,Data direction selection bit 9" "Input,Output"
|
|
setclrfld.long 0x00 8. -0x1FC 8. -0x1F8 8. " DD_set/clr_[8] ,Data direction selection bit 8" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x1FC 7. -0x1F8 7. " DD_set/clr_[7] ,Data direction selection bit 7" "Input,Output"
|
|
setclrfld.long 0x00 6. -0x1FC 6. -0x1F8 6. " DD_set/clr_[6] ,Data direction selection bit 6" "Input,Output"
|
|
setclrfld.long 0x00 5. -0x1FC 5. -0x1F8 5. " DD_set/clr_[5] ,Data direction selection bit 5" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x1FC 4. -0x1F8 4. " DD_set/clr_[4] ,Data direction selection bit 4" "Input,Output"
|
|
setclrfld.long 0x00 3. -0x1FC 3. -0x1F8 3. " DD_set/clr_[3] ,Data direction selection bit 3" "Input,Output"
|
|
setclrfld.long 0x00 2. -0x1FC 2. -0x1F8 2. " DD_set/clr_[2] ,Data direction selection bit 2" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x1FC 1. -0x1F8 1. " DD_set/clr_[1] ,Data direction selection bit 1" "Input,Output"
|
|
setclrfld.long 0x00 0. -0x1FC 0. -0x1F8 0. " DD_set/clr_[0] ,Data direction selection bit 0" "Input,Output"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "GPIO_PODR0,Port Output Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " POD_set/clr_[31] ,Port output data bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " POD_set/clr_[30] ,Port output data bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " POD_set/clr_[29] ,Port output data bit 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " POD_set/clr_[28] ,Port output data bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " POD_set/clr_[27] ,Port output data bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " POD_set/clr_[26] ,Port output data bit 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " POD_set/clr_[25] ,Port output data bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " POD_set/clr_[24] ,Port output bit data 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " POD_set/clr_[23] ,Port output bit data 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " POD_set/clr_[22] ,Port output bit data 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " POD_set/clr_[21] ,Port output bit data 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " POD_set/clr_[20] ,Port output bit data 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " POD_set/clr_[19] ,Port output data bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " POD_set/clr_[18] ,Port output data bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " POD_set/clr_[17] ,Port output data bit 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " POD_set/clr_[16] ,Port output data bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " POD_set/clr_[15] ,Port output data bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " POD_set/clr_[14] ,Port output data bit 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " POD_set/clr_[13] ,Port output data bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " POD_set/clr_[12] ,Port output data bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " POD_set/clr_[11] ,Port output data bit 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " POD_set/clr_[10] ,Port output data bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 09. -0x1FC 09. " POD_set/clr_[9] ,Port output data bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 08. -0x1FC 08. " POD_set/clr_[8] ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 07. -0x1FC 07. " POD_set/clr_[7] ,Port output data bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 06. -0x1FC 06. " POD_set/clr_[6] ,Port output data bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 05. -0x1FC 05. " POD_set/clr_[5] ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x200 04. -0x1FC 04. " POD_set/clr_[4] ,Port output data bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x200 03. -0x1FC 03. " POD_set/clr_[3] ,Port output data bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 02. -0x1FC 02. " POD_set/clr_[2] ,Port output data bit 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x200 01. -0x1FC 01. " POD_set/clr_[1] ,Port output data bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 00. -0x1FC 00. " POD_set/clr_[0] ,Port output data bit 0" "Low,High"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "GPIO_PODR1,Port Output Set/Clear Register 1"
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " POD_set/clr_[31] ,Port output data bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " POD_set/clr_[30] ,Port output data bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " POD_set/clr_[29] ,Port output data bit 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " POD_set/clr_[28] ,Port output data bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " POD_set/clr_[27] ,Port output data bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " POD_set/clr_[26] ,Port output data bit 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " POD_set/clr_[25] ,Port output data bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " POD_set/clr_[24] ,Port output bit data 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " POD_set/clr_[23] ,Port output bit data 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " POD_set/clr_[22] ,Port output bit data 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " POD_set/clr_[21] ,Port output bit data 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " POD_set/clr_[20] ,Port output bit data 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " POD_set/clr_[19] ,Port output data bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " POD_set/clr_[18] ,Port output data bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " POD_set/clr_[17] ,Port output data bit 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " POD_set/clr_[16] ,Port output data bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " POD_set/clr_[15] ,Port output data bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " POD_set/clr_[14] ,Port output data bit 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " POD_set/clr_[13] ,Port output data bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " POD_set/clr_[12] ,Port output data bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " POD_set/clr_[11] ,Port output data bit 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " POD_set/clr_[10] ,Port output data bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 09. -0x1FC 09. " POD_set/clr_[9] ,Port output data bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 08. -0x1FC 08. " POD_set/clr_[8] ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 07. -0x1FC 07. " POD_set/clr_[7] ,Port output data bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 06. -0x1FC 06. " POD_set/clr_[6] ,Port output data bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 05. -0x1FC 05. " POD_set/clr_[5] ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x200 04. -0x1FC 04. " POD_set/clr_[4] ,Port output data bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x200 03. -0x1FC 03. " POD_set/clr_[3] ,Port output data bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 02. -0x1FC 02. " POD_set/clr_[2] ,Port output data bit 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x200 01. -0x1FC 01. " POD_set/clr_[1] ,Port output data bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 00. -0x1FC 00. " POD_set/clr_[0] ,Port output data bit 0" "Low,High"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "GPIO_PODR2,Port Output Set/Clear Register 2"
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " POD_set/clr_[31] ,Port output data bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " POD_set/clr_[30] ,Port output data bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " POD_set/clr_[29] ,Port output data bit 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " POD_set/clr_[28] ,Port output data bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " POD_set/clr_[27] ,Port output data bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " POD_set/clr_[26] ,Port output data bit 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " POD_set/clr_[25] ,Port output data bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " POD_set/clr_[24] ,Port output bit data 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " POD_set/clr_[23] ,Port output bit data 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " POD_set/clr_[22] ,Port output bit data 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " POD_set/clr_[21] ,Port output bit data 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " POD_set/clr_[20] ,Port output bit data 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " POD_set/clr_[19] ,Port output data bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " POD_set/clr_[18] ,Port output data bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " POD_set/clr_[17] ,Port output data bit 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " POD_set/clr_[16] ,Port output data bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " POD_set/clr_[15] ,Port output data bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " POD_set/clr_[14] ,Port output data bit 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " POD_set/clr_[13] ,Port output data bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " POD_set/clr_[12] ,Port output data bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " POD_set/clr_[11] ,Port output data bit 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " POD_set/clr_[10] ,Port output data bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 09. -0x1FC 09. " POD_set/clr_[9] ,Port output data bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 08. -0x1FC 08. " POD_set/clr_[8] ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 07. -0x1FC 07. " POD_set/clr_[7] ,Port output data bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 06. -0x1FC 06. " POD_set/clr_[6] ,Port output data bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 05. -0x1FC 05. " POD_set/clr_[5] ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x200 04. -0x1FC 04. " POD_set/clr_[4] ,Port output data bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x200 03. -0x1FC 03. " POD_set/clr_[3] ,Port output data bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 02. -0x1FC 02. " POD_set/clr_[2] ,Port output data bit 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x200 01. -0x1FC 01. " POD_set/clr_[1] ,Port output data bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 00. -0x1FC 00. " POD_set/clr_[0] ,Port output data bit 0" "Low,High"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "GPIO_PODR3,Port Output Set/Clear Register 3"
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " POD_set/clr_[31] ,Port output data bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " POD_set/clr_[30] ,Port output data bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " POD_set/clr_[29] ,Port output data bit 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " POD_set/clr_[28] ,Port output data bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " POD_set/clr_[27] ,Port output data bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " POD_set/clr_[26] ,Port output data bit 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " POD_set/clr_[25] ,Port output data bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " POD_set/clr_[24] ,Port output bit data 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " POD_set/clr_[23] ,Port output bit data 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " POD_set/clr_[22] ,Port output bit data 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " POD_set/clr_[21] ,Port output bit data 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " POD_set/clr_[20] ,Port output bit data 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " POD_set/clr_[19] ,Port output data bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " POD_set/clr_[18] ,Port output data bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " POD_set/clr_[17] ,Port output data bit 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " POD_set/clr_[16] ,Port output data bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " POD_set/clr_[15] ,Port output data bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " POD_set/clr_[14] ,Port output data bit 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " POD_set/clr_[13] ,Port output data bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " POD_set/clr_[12] ,Port output data bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " POD_set/clr_[11] ,Port output data bit 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " POD_set/clr_[10] ,Port output data bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 09. -0x1FC 09. " POD_set/clr_[9] ,Port output data bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 08. -0x1FC 08. " POD_set/clr_[8] ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 07. -0x1FC 07. " POD_set/clr_[7] ,Port output data bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 06. -0x1FC 06. " POD_set/clr_[6] ,Port output data bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 05. -0x1FC 05. " POD_set/clr_[5] ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x200 04. -0x1FC 04. " POD_set/clr_[4] ,Port output data bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x200 03. -0x1FC 03. " POD_set/clr_[3] ,Port output data bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 02. -0x1FC 02. " POD_set/clr_[2] ,Port output data bit 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x200 01. -0x1FC 01. " POD_set/clr_[1] ,Port output data bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 00. -0x1FC 00. " POD_set/clr_[0] ,Port output data bit 0" "Low,High"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "GPIO_PODR4,Port Output Set/Clear Register 4"
|
|
setclrfld.long 0x00 31. -0x200 31. -0x1FC 31. " POD_set/clr_[31] ,Port output data bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. -0x200 30. -0x1FC 30. " POD_set/clr_[30] ,Port output data bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. -0x200 29. -0x1FC 29. " POD_set/clr_[29] ,Port output data bit 29" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 28. -0x200 28. -0x1FC 28. " POD_set/clr_[28] ,Port output data bit 28" "Low,High"
|
|
setclrfld.long 0x00 27. -0x200 27. -0x1FC 27. " POD_set/clr_[27] ,Port output data bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. -0x200 26. -0x1FC 26. " POD_set/clr_[26] ,Port output data bit 26" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 25. -0x200 25. -0x1FC 25. " POD_set/clr_[25] ,Port output data bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. -0x200 24. -0x1FC 24. " POD_set/clr_[24] ,Port output bit data 24" "Low,High"
|
|
setclrfld.long 0x00 23. -0x200 23. -0x1FC 23. " POD_set/clr_[23] ,Port output bit data 23" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 22. -0x200 22. -0x1FC 22. " POD_set/clr_[22] ,Port output bit data 22" "Low,High"
|
|
setclrfld.long 0x00 21. -0x200 21. -0x1FC 21. " POD_set/clr_[21] ,Port output bit data 21" "Low,High"
|
|
setclrfld.long 0x00 20. -0x200 20. -0x1FC 20. " POD_set/clr_[20] ,Port output bit data 20" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 19. -0x200 19. -0x1FC 19. " POD_set/clr_[19] ,Port output data bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. -0x200 18. -0x1FC 18. " POD_set/clr_[18] ,Port output data bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. -0x200 17. -0x1FC 17. " POD_set/clr_[17] ,Port output data bit 17" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 16. -0x200 16. -0x1FC 16. " POD_set/clr_[16] ,Port output data bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. -0x200 15. -0x1FC 15. " POD_set/clr_[15] ,Port output data bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. -0x200 14. -0x1FC 14. " POD_set/clr_[14] ,Port output data bit 14" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 13. -0x200 13. -0x1FC 13. " POD_set/clr_[13] ,Port output data bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. -0x200 12. -0x1FC 12. " POD_set/clr_[12] ,Port output data bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. -0x200 11. -0x1FC 11. " POD_set/clr_[11] ,Port output data bit 11" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 10. -0x200 10. -0x1FC 10. " POD_set/clr_[10] ,Port output data bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. -0x200 09. -0x1FC 09. " POD_set/clr_[9] ,Port output data bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. -0x200 08. -0x1FC 08. " POD_set/clr_[8] ,Port output data bit 8" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 7. -0x200 07. -0x1FC 07. " POD_set/clr_[7] ,Port output data bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. -0x200 06. -0x1FC 06. " POD_set/clr_[6] ,Port output data bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. -0x200 05. -0x1FC 05. " POD_set/clr_[5] ,Port output data bit 5" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 4. -0x200 04. -0x1FC 04. " POD_set/clr_[4] ,Port output data bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. -0x200 03. -0x1FC 03. " POD_set/clr_[3] ,Port output data bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. -0x200 02. -0x1FC 02. " POD_set/clr_[2] ,Port output data bit 2" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 1. -0x200 01. -0x1FC 01. " POD_set/clr_[1] ,Port output data bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. -0x200 00. -0x1FC 00. " POD_set/clr_[0] ,Port output data bit 0" "Low,High"
|
|
group.long 0x300++0x3
|
|
line.long 0x00 "GPIO_PIDR0,Port Input Data Register 0"
|
|
bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PID[30] ,Port input data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PID[29] ,Port input data bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PID[28] ,Port input data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PID[27] ,Port input data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PID[26] ,Port input data bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PID[25] ,Port input data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PID[24] ,Port input data bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " PID[23] ,Port input data bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PID[21] ,Port input data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PID[20] ,Port input data bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID[19] ,Port input data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PID[18] ,Port input data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PID[17] ,Port input data bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PID[16] ,Port input data bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " PID[15] ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PID[14] ,Port input data bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PID[13] ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PID[12] ,Port input data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PID[11] ,Port input data bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PID[10] ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PID[9] ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PID[8] ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID[7] ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PID[6] ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PID[5] ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PID[4] ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PID[3] ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PID[2] ,Port input data bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PID[1] ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PID[0] ,Port input data bit 0" "Low,High"
|
|
group.long 0x304++0x3
|
|
line.long 0x00 "GPIO_PIDR1,Port Input Data Register 1"
|
|
bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PID[30] ,Port input data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PID[29] ,Port input data bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PID[28] ,Port input data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PID[27] ,Port input data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PID[26] ,Port input data bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PID[25] ,Port input data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PID[24] ,Port input data bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " PID[23] ,Port input data bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PID[21] ,Port input data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PID[20] ,Port input data bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID[19] ,Port input data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PID[18] ,Port input data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PID[17] ,Port input data bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PID[16] ,Port input data bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " PID[15] ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PID[14] ,Port input data bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PID[13] ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PID[12] ,Port input data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PID[11] ,Port input data bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PID[10] ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PID[9] ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PID[8] ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID[7] ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PID[6] ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PID[5] ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PID[4] ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PID[3] ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PID[2] ,Port input data bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PID[1] ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PID[0] ,Port input data bit 0" "Low,High"
|
|
group.long 0x308++0x3
|
|
line.long 0x00 "GPIO_PIDR2,Port Input Data Register 2"
|
|
bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PID[30] ,Port input data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PID[29] ,Port input data bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PID[28] ,Port input data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PID[27] ,Port input data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PID[26] ,Port input data bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PID[25] ,Port input data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PID[24] ,Port input data bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " PID[23] ,Port input data bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PID[21] ,Port input data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PID[20] ,Port input data bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID[19] ,Port input data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PID[18] ,Port input data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PID[17] ,Port input data bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PID[16] ,Port input data bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " PID[15] ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PID[14] ,Port input data bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PID[13] ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PID[12] ,Port input data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PID[11] ,Port input data bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PID[10] ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PID[9] ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PID[8] ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID[7] ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PID[6] ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PID[5] ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PID[4] ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PID[3] ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PID[2] ,Port input data bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PID[1] ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PID[0] ,Port input data bit 0" "Low,High"
|
|
group.long 0x30C++0x3
|
|
line.long 0x00 "GPIO_PIDR3,Port Input Data Register 3"
|
|
bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PID[30] ,Port input data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PID[29] ,Port input data bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PID[28] ,Port input data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PID[27] ,Port input data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PID[26] ,Port input data bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PID[25] ,Port input data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PID[24] ,Port input data bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " PID[23] ,Port input data bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PID[21] ,Port input data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PID[20] ,Port input data bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID[19] ,Port input data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PID[18] ,Port input data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PID[17] ,Port input data bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PID[16] ,Port input data bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " PID[15] ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PID[14] ,Port input data bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PID[13] ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PID[12] ,Port input data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PID[11] ,Port input data bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PID[10] ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PID[9] ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PID[8] ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID[7] ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PID[6] ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PID[5] ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PID[4] ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PID[3] ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PID[2] ,Port input data bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PID[1] ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PID[0] ,Port input data bit 0" "Low,High"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "GPIO_PIDR4,Port Input Data Register 4"
|
|
bitfld.long 0x00 31. " PID[31] ,Port input data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PID[30] ,Port input data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PID[29] ,Port input data bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PID[28] ,Port input data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PID[27] ,Port input data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PID[26] ,Port input data bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PID[25] ,Port input data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PID[24] ,Port input data bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " PID[23] ,Port input data bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PID[22] ,Port input data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PID[21] ,Port input data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PID[20] ,Port input data bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PID[19] ,Port input data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PID[18] ,Port input data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PID[17] ,Port input data bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PID[16] ,Port input data bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " PID[15] ,Port input data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PID[14] ,Port input data bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PID[13] ,Port input data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PID[12] ,Port input data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PID[11] ,Port input data bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PID[10] ,Port input data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PID[9] ,Port input data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PID[8] ,Port input data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PID[7] ,Port input data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PID[6] ,Port input data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PID[5] ,Port input data bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PID[4] ,Port input data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PID[3] ,Port input data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PID[2] ,Port input data bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PID[1] ,Port input data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PID[0] ,Port input data bit 0" "Low,High"
|
|
group.long 0x400++0x3
|
|
line.long 0x00 "GPIO_PORTEN,Port Input Enable Register"
|
|
bitfld.long 0x00 0. " GPORTEN ,Global input enable bit" "Disabled,Enabled"
|
|
wgroup.long 0x404++0x3
|
|
line.long 0x00 "GPIO_KEYCDR,GPIO Key Code Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PPC"
|
|
base ad:0xB4740000
|
|
width 14.
|
|
sif cpuis("S6J311?JAA")
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "PPC_PCFGR000,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD0,,,SOT2_1,?..."
|
|
group.word 0x02++0x1
|
|
line.word 0x00 "PPC_PCFGR001,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD1,,,SCS20_1,?..."
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "PPC_PCFGR002,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD2,TIOA0_1,,SCS21_1,?..."
|
|
group.word 0x06++0x1
|
|
line.word 0x00 "PPC_PCFGR003,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD3,,,SCS22_1,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "PPC_PCFGR004,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD4,TIOA1_1,,SCS23_1,?..."
|
|
group.word 0x0A++0x1
|
|
line.word 0x00 "PPC_PCFGR005,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD5,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "PPC_PCFGR006,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD6,,SOT3_0,?..."
|
|
group.word 0x0E++0x1
|
|
line.word 0x00 "PPC_PCFGR007,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD7,,SCK3_0,SCK18_1,?..."
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "PPC_PCFGR008,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD8,TIOA0_0,SCS30_0,SCS180_1,?..."
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PPC_PCFGR009,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD9,TIOA1_0,?..."
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "PPC_PCFGR010,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,TIOA2_0,SOT8_0,?..."
|
|
group.word 0x16++0x1
|
|
line.word 0x00 "PPC_PCFGR011,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,TIOA2_1,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "PPC_PCFGR012,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA3_0,SCK8_0,,OUT5_0,?..."
|
|
group.word 0x1A++0x1
|
|
line.word 0x00 "PPC_PCFGR013,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,TIOA4_0,SCS80_0,,OUT6_0,?..."
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "PPC_PCFGR014,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA3_1,,SOT18_1,?..."
|
|
group.word 0x1E++0x1
|
|
line.word 0x00 "PPC_PCFGR015,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA5_0,SCS81_0,,OUT7_0,?..."
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "PPC_PCFGR016,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,TIOA6_0,SCS82_0,,OUT8_0,?..."
|
|
group.word 0x22++0x1
|
|
line.word 0x00 "PPC_PCFGR017,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA7_0,SCS83_0,,OUT9_0,?..."
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "PPC_PCFGR018,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,TIOA8_0,,,OUT10_0,?..."
|
|
group.word 0x26++0x1
|
|
line.word 0x00 "PPC_PCFGR019,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,,,OUT11_0,?..."
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "PPC_PCFGR020,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SOT0_0,?..."
|
|
group.word 0x2A++0x1
|
|
line.word 0x00 "PPC_PCFGR021,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,SCK0_0,SCK4_1,?..."
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "PPC_PCFGR022,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,?..."
|
|
group.word 0x2E++0x1
|
|
line.word 0x00 "PPC_PCFGR023,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,SCS0_0,?..."
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "PPC_PCFGR024,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,,,SOT4_1,?..."
|
|
group.word 0x32++0x1
|
|
line.word 0x00 "PPC_PCFGR025,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,,SCS40_1,?..."
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "PPC_PCFGR026,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,,SCS41_1,?..."
|
|
group.word 0x36++0x1
|
|
line.word 0x00 "PPC_PCFGR027,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,TIOA4_1,,SCS42_1,?..."
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "PPC_PCFGR028,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,,,OUT0_1,?..."
|
|
group.word 0x3A++0x1
|
|
line.word 0x00 "PPC_PCFGR029,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,,SOT1_0,,OUT1_1,?..."
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "PPC_PCFGR030,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,,,SCS43_1,OUT2_1,?..."
|
|
group.word 0x3E++0x1
|
|
line.word 0x00 "PPC_PCFGR031,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,SCS1_0,,OUT3_1,?..."
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "PPC_PCFGR100,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,SCK1_0,,OUT4_1,?..."
|
|
group.word 0x42++0x1
|
|
line.word 0x00 "PPC_PCFGR101,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,,OUT5_1,?..."
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "PPC_PCFGR102,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,?..."
|
|
group.word 0x46++0x1
|
|
line.word 0x00 "PPC_PCFGR103,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,OUT6_1,?..."
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "PPC_PCFGR104,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,SOT17_0,?..."
|
|
group.word 0x4A++0x1
|
|
line.word 0x00 "PPC_PCFGR105,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,TIOA9_0,SCK17_0,,OUT7_1,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "PPC_PCFGR106,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SCS170_0,,OUT8_1,TX1_2,?..."
|
|
group.word 0x4E++0x1
|
|
line.word 0x00 "PPC_PCFGR107,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,TIOA10_0,,,OUT9_1,?..."
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "PPC_PCFGR108,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA11_0,SOT19_0,,OUT10_1,?..."
|
|
group.word 0x52++0x1
|
|
line.word 0x00 "PPC_PCFGR109,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA12_0,SCK19_0,,OUT11_1?..."
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "PPC_PCFGR110,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,SCS190_0,?..."
|
|
group.word 0x56++0x1
|
|
line.word 0x00 "PPC_PCFGR111,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,?..."
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "PPC_PCFGR112,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA13_0,SOT18_0,?..."
|
|
group.word 0x5A++0x1
|
|
line.word 0x00 "PPC_PCFGR113,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,TIOA5_1,SCK18_0,SOT19_1,?..."
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "PPC_PCFGR114,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA6_1,SCS180_0,?..."
|
|
group.word 0x5E++0x1
|
|
line.word 0x00 "PPC_PCFGR115,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,?..."
|
|
group.word 0x60++0x1
|
|
line.word 0x00 "PPC_PCFGR116,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,?..."
|
|
group.word 0x62++0x1
|
|
line.word 0x00 "PPC_PCFGR117,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,?..."
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "PPC_PCFGR118,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,?..."
|
|
group.word 0x66++0x1
|
|
line.word 0x00 "PPC_PCFGR119,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,SCS60_0,?..."
|
|
group.word 0x68++0x1
|
|
line.word 0x00 "PPC_PCFGR120,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SCS61_0,?..."
|
|
group.word 0x6A++0x1
|
|
line.word 0x00 "PPC_PCFGR121,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,TIOA14_0,SCS160_0,?..."
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "PPC_PCFGR122,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,TIOA11_1,SCS62_0,?..."
|
|
group.word 0x6E++0x1
|
|
line.word 0x00 "PPC_PCFGR123,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,TIOA12_1,SCS63_0,?..."
|
|
group.word 0x70++0x1
|
|
line.word 0x00 "PPC_PCFGR124,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,TIOA15_0,?..."
|
|
group.word 0x72++0x1
|
|
line.word 0x00 "PPC_PCFGR125,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,TIOA16_0,SOT16_0,?..."
|
|
group.word 0x74++0x1
|
|
line.word 0x00 "PPC_PCFGR126,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,SCK16_0,?..."
|
|
group.word 0x76++0x1
|
|
line.word 0x00 "PPC_PCFGR127,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,SCS203_0,?..."
|
|
group.word 0x78++0x1
|
|
line.word 0x00 "PPC_PCFGR128,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,SCS200_0,?..."
|
|
group.word 0x7A++0x1
|
|
line.word 0x00 "PPC_PCFGR129,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,,SCS201_0,?..."
|
|
group.word 0x7C++0x1
|
|
line.word 0x00 "PPC_PCFGR130,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,?..."
|
|
group.word 0x7E++0x1
|
|
line.word 0x00 "PPC_PCFGR131,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,SOT6_0,?..."
|
|
group.word 0x80++0x1
|
|
line.word 0x00 "PPC_PCFGR200,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,TIOA17_0,SCS202_0,?..."
|
|
group.word 0x82++0x1
|
|
line.word 0x00 "PPC_PCFGR201,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,TIOA18_0,?..."
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "PPC_PCFGR202,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,SCK6_0,?..."
|
|
group.word 0x86++0x1
|
|
line.word 0x00 "PPC_PCFGR203,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,?..."
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "PPC_PCFGR204,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,SOT20_0,?..."
|
|
group.word 0x8A++0x1
|
|
line.word 0x00 "PPC_PCFGR205,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,SCK20_0,?..."
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "PPC_PCFGR206,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SCS43_0,?..."
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "PPC_PCFGR207,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SCK4_0,?..."
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "PPC_PCFGR208,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA19_0,SCS42_0,?..."
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "PPC_PCFGR209,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA20_0,SOT4_0,?..."
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "PPC_PCFGR210,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,TIOA21_0,?..."
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "PPC_PCFGR211,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,TIOA22_0,SCS40_0,?..."
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "PPC_PCFGR212,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA13_1,SCS41_0,SCS50_1,?..."
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "PPC_PCFGR213,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,TIOA14_1,?..."
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "PPC_PCFGR214,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA15_1,,SOT5_1,?..."
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "PPC_PCFGR215,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA16_1,,SCK5_1,?..."
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "PPC_PCFGR216,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,?..."
|
|
group.word 0xA2++0x1
|
|
line.word 0x00 "PPC_PCFGR217,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,,SOT15_0,?..."
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "PPC_PCFGR218,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,SCK15_0,?..."
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "PPC_PCFGR219,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,,SCS150_0,?..."
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "PPC_PCFGR220,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SCS53_0,?..."
|
|
group.word 0xAA++0x1
|
|
line.word 0x00 "PPC_PCFGR221,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,SCS52_0,?..."
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "PPC_PCFGR222,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD22,?..."
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "PPC_PCFGR223,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD23,,SSC51_0,?..."
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "PPC_PCFGR224,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD24,,SCS50_0,,,TX0_2,?..."
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "PPC_PCFGR225,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,,SOT5_0,?..."
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "PPC_PCFGR226,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,TIOA17_1,SCK5_0,?..."
|
|
group.word 0xB6++0x1
|
|
line.word 0x00 "PPC_PCFGR227,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,TIOA23_0,SCK10_0,?..."
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "PPC_PCFGR228,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,TIOA24_0,SOT10_0,,,TX0_1,?..."
|
|
group.word 0xBA++0x1
|
|
line.word 0x00 "PPC_PCFGR229,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,TIOA25_0,,,OUT0_0,?..."
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "PPC_PCFGR230,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,TIOA26_0,SCS103_0,,OUT1_0?..."
|
|
group.word 0xBE++0x1
|
|
line.word 0x00 "PPC_PCFGR231,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,TIOA27_0,SCS102_0,,OUT2_0,?..."
|
|
group.word 0xC0++0x1
|
|
line.word 0x00 "PPC_PCFGR300,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,TIOA28_0,SCS101_0,,OUT3_0,?..."
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "PPC_PCFGR301,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,TIOA18_1,SCS100_0,,OUT4_0,?..."
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "PPC_PCFGR302,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,TIOA19_1,?..."
|
|
group.word 0xC6++0x1
|
|
line.word 0x00 "PPC_PCFGR303,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,SOT14_0,?..."
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "PPC_PCFGR304,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,TIOA20_1,SCK14_0,?..."
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "PPC_PCFGR305,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,TIOA29_0,SCS140_0,?..."
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "PPC_PCFGR306,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SCS73_0,,,TX0_0,?..."
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "PPC_PCFGR307,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SCS72_0,?..."
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "PPC_PCFGR308,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,TIOA28_1,SCK13_0,?..."
|
|
group.word 0xD2++0x1
|
|
line.word 0x00 "PPC_PCFGR309,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA29_1,SCS130_0,?..."
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "PPC_PCFGR310,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,?..."
|
|
group.word 0xD6++0x1
|
|
line.word 0x00 "PPC_PCFGR311,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,SOT13_0,?..."
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "PPC_PCFGR312,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,,SCS71_0,?..."
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "PPC_PCFGR313,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SOT7_0,?..."
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "PPC_PCFGR314,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,TIOA7_1,SCK7_0,?..."
|
|
group.word 0xDE++0x1
|
|
line.word 0x00 "PPC_PCFGR315,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA8_1,SCS70_0,?..."
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "PPC_PCFGR316,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,TIOA21_1,?..."
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "PPC_PCFGR317,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA9_1,,,,TX1_1,?..."
|
|
group.word 0xE4++0x1
|
|
line.word 0x00 "PPC_PCFGR318,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,TIOA10_1,?..."
|
|
group.word 0xE6++0x1
|
|
line.word 0x00 "PPC_PCFGR319,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,?..."
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "PPC_PCFGR320,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,,,PWUTRG,?..."
|
|
group.word 0xEA++0x1
|
|
line.word 0x00 "PPC_PCFGR321,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "JTAG_nSRST,POD21,?..."
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "PPC_PCFGR322,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "JTAG_TRST,POD22,?..."
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "PPC_PCFGR323,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "JTAG_TDO,POD23,?..."
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "PPC_PCFGR324,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "JTAG_TDI,POD24,?..."
|
|
group.word 0xF2++0x1
|
|
line.word 0x00 "PPC_PCFGR325,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD25,?..."
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "PPC_PCFGR326,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD26,,SOT21_0,?..."
|
|
group.word 0xF6++0x1
|
|
line.word 0x00 "PPC_PCFGR327,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD27,,SCK21_0,SCK6_1,?..."
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "PPC_PCFGR328,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD28,,SCS210_0,SOT6_1,?..."
|
|
group.word 0xFA++0x1
|
|
line.word 0x00 "PPC_PCFGR329,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD29,?..."
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "PPC_PCFGR330,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD30,?..."
|
|
group.word 0xFE++0x1
|
|
line.word 0x00 "PPC_PCFGR331,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD31,,,SCS60_1,?..."
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "PPC_PCFGR400,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD00,,,SCS61_1,?..."
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "PPC_PCFGR401,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD01,,,SCS62_1,,TX1_0,?..."
|
|
group.word 0x104++0x1
|
|
line.word 0x00 "PPC_PCFGR402,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD02,,SCS90_0,SCS63_1,?..."
|
|
group.word 0x106++0x1
|
|
line.word 0x00 "PPC_PCFGR403,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD03,,,,TRACEDATA0,?..."
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "PPC_PCFGR404,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD04,,,,TRACEDATA1,?..."
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "PPC_PCFGR405,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD05,,,,TRACEDATA2,?..."
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "PPC_PCFGR406,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD06,,SOT9_0,,TRACEDATA3,?..."
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "PPC_PCFGR407,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD07,,SCK9_0,SCK7_1,TRACEDATA4,?..."
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "PPC_PCFGR408,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD08,,,,TRACEDATA5,?..."
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "PPC_PCFGR409,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD09,TIOA24_1,SOT2_0,,TRACEDATA6,?..."
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "PPC_PCFGR410,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD10,,,SCS70_1,?..."
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "PPC_PCFGR411,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD11,,SCK2_0,SCS71_1,TRACEDATA7,?..."
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "PPC_PCFGR412,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD12,TIOA25_1,,SCS72_1,?..."
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "PPC_PCFGR413,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD13,,SCS20_0,SCS73_1,?..."
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "PPC_PCFGR414,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD14,,,SCS21_0,?..."
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "PPC_PCFGR415,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD15,TIOA26_1,SOT11_0,?..."
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "PPC_PCFGR416,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD16,TIOA22_1,SCK11_0,?..."
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "PPC_PCFGR417,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD17,TIOA23_1,SCS110_0,SOT7_1,?..."
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "PPC_PCFGR418,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD18,,,SCS22_0,?..."
|
|
group.word 0x126++0x1
|
|
line.word 0x00 "PPC_PCFGR419,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD19,TIOA27_1,SOT12_0,SCS23_0,?..."
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "PPC_PCFGR420,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD20,,SCK12_0,SCK2_1,TRACECLK,?..."
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "PPC_PCFGR421,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "POD21,,SCS120_0,,TRACECTL,?..."
|
|
elif cpuis("S6J311?HAA")
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "PPC_PCFGR00,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2++0x1
|
|
line.word 0x00 "PPC_PCFGR01,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "PPC_PCFGR02,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6++0x1
|
|
line.word 0x00 "PPC_PCFGR03,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA++0x1
|
|
line.word 0x00 "PPC_PCFGR05,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "PPC_PCFGR06,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "PPC_PCFGR07,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "PPC_PCFGR08,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PPC_PCFGR09,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "PPC_PCFGR010,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "PPC_PCFGR012,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x1A++0x1
|
|
line.word 0x00 "PPC_PCFGR013,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x1E++0x1
|
|
line.word 0x00 "PPC_PCFGR015,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "PPC_PCFGR016,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x22++0x1
|
|
line.word 0x00 "PPC_PCFGR017,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "PPC_PCFGR018,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x26++0x1
|
|
line.word 0x00 "PPC_PCFGR019,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "PPC_PCFGR020,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2A++0x1
|
|
line.word 0x00 "PPC_PCFGR021,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "PPC_PCFGR022,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2E++0x1
|
|
line.word 0x00 "PPC_PCFGR023,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "PPC_PCFGR024,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x36++0x1
|
|
line.word 0x00 "PPC_PCFGR027,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "PPC_PCFGR028,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3A++0x1
|
|
line.word 0x00 "PPC_PCFGR029,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "PPC_PCFGR030,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3E++0x1
|
|
line.word 0x00 "PPC_PCFGR031,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "PPC_PCFGR0100,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x42++0x1
|
|
line.word 0x00 "PPC_PCFGR0101,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x46++0x1
|
|
line.word 0x00 "PPC_PCFGR0103,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4A++0x1
|
|
line.word 0x00 "PPC_PCFGR0105,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "PPC_PCFGR0106,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4E++0x1
|
|
line.word 0x00 "PPC_PCFGR0107,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "PPC_PCFGR0108,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x52++0x1
|
|
line.word 0x00 "PPC_PCFGR0109,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "PPC_PCFGR0112,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5A++0x1
|
|
line.word 0x00 "PPC_PCFGR0113,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "PPC_PCFGR0114,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5E++0x1
|
|
line.word 0x00 "PPC_PCFGR0115,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x62++0x1
|
|
line.word 0x00 "PPC_PCFGR0117,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "PPC_PCFGR0118,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x66++0x1
|
|
line.word 0x00 "PPC_PCFGR0119,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x68++0x1
|
|
line.word 0x00 "PPC_PCFGR0120,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "PPC_PCFGR0122,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6E++0x1
|
|
line.word 0x00 "PPC_PCFGR0123,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x74++0x1
|
|
line.word 0x00 "PPC_PCFGR0126,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x76++0x1
|
|
line.word 0x00 "PPC_PCFGR0127,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x78++0x1
|
|
line.word 0x00 "PPC_PCFGR0128,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7A++0x1
|
|
line.word 0x00 "PPC_PCFGR0129,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7C++0x1
|
|
line.word 0x00 "PPC_PCFGR0130,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7E++0x1
|
|
line.word 0x00 "PPC_PCFGR0131,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "PPC_PCFGR0202,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x86++0x1
|
|
line.word 0x00 "PPC_PCFGR0203,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "PPC_PCFGR0204,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8A++0x1
|
|
line.word 0x00 "PPC_PCFGR0205,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "PPC_PCFGR0206,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "PPC_PCFGR0207,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "PPC_PCFGR0208,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "PPC_PCFGR0209,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "PPC_PCFGR0210,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "PPC_PCFGR0211,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "PPC_PCFGR0212,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "PPC_PCFGR0213,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "PPC_PCFGR0214,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "PPC_PCFGR0215,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "PPC_PCFGR0218,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "PPC_PCFGR0219,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "PPC_PCFGR0220,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "PPC_PCFGR0222,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "PPC_PCFGR0223,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "PPC_PCFGR0224,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "PPC_PCFGR0225,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "PPC_PCFGR0226,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB6++0x1
|
|
line.word 0x00 "PPC_PCFGR0227,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "PPC_PCFGR0228,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBA++0x1
|
|
line.word 0x00 "PPC_PCFGR0229,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "PPC_PCFGR0230,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBE++0x1
|
|
line.word 0x00 "PPC_PCFGR0231,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC0++0x1
|
|
line.word 0x00 "PPC_PCFGR0300,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "PPC_PCFGR0301,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "PPC_PCFGR0302,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "PPC_PCFGR0304,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "PPC_PCFGR0305,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "PPC_PCFGR0306,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "PPC_PCFGR0307,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "PPC_PCFGR0308,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD2++0x1
|
|
line.word 0x00 "PPC_PCFGR0309,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "PPC_PCFGR0312,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "PPC_PCFGR0313,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "PPC_PCFGR0314,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDE++0x1
|
|
line.word 0x00 "PPC_PCFGR0315,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "PPC_PCFGR0317,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEA++0x1
|
|
line.word 0x00 "PPC_PCFGR0321,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "PPC_PCFGR0322,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "PPC_PCFGR0323,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "PPC_PCFGR0324,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xF6++0x1
|
|
line.word 0x00 "PPC_PCFGR0327,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "PPC_PCFGR0330,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xFE++0x1
|
|
line.word 0x00 "PPC_PCFGR0331,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "PPC_PCFGR0400,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "PPC_PCFGR0401,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x104++0x1
|
|
line.word 0x00 "PPC_PCFGR0402,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x106++0x1
|
|
line.word 0x00 "PPC_PCFGR0403,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "PPC_PCFGR0404,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "PPC_PCFGR0405,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "PPC_PCFGR0406,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "PPC_PCFGR0407,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "PPC_PCFGR0408,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "PPC_PCFGR0409,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "PPC_PCFGR0411,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "PPC_PCFGR0413,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "PPC_PCFGR0414,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "PPC_PCFGR0416,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "PPC_PCFGR0417,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "PPC_PCFGR0418,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "PPC_PCFGR0420,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "PPC_PCFGR0421,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
elif cpuis("S6J312?HAA")
|
|
group.word 0x0++0x1
|
|
line.word 0x00 "PPC_PCFGR00,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2++0x1
|
|
line.word 0x00 "PPC_PCFGR01,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4++0x1
|
|
line.word 0x00 "PPC_PCFGR02,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6++0x1
|
|
line.word 0x00 "PPC_PCFGR03,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA++0x1
|
|
line.word 0x00 "PPC_PCFGR05,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "PPC_PCFGR06,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "PPC_PCFGR07,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "PPC_PCFGR08,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x12++0x1
|
|
line.word 0x00 "PPC_PCFGR09,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "PPC_PCFGR010,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "PPC_PCFGR012,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x1A++0x1
|
|
line.word 0x00 "PPC_PCFGR013,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x1E++0x1
|
|
line.word 0x00 "PPC_PCFGR015,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "PPC_PCFGR016,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x22++0x1
|
|
line.word 0x00 "PPC_PCFGR017,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "PPC_PCFGR018,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x26++0x1
|
|
line.word 0x00 "PPC_PCFGR019,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "PPC_PCFGR020,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2A++0x1
|
|
line.word 0x00 "PPC_PCFGR021,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "PPC_PCFGR022,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x2E++0x1
|
|
line.word 0x00 "PPC_PCFGR023,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "PPC_PCFGR024,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x36++0x1
|
|
line.word 0x00 "PPC_PCFGR027,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "PPC_PCFGR028,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3A++0x1
|
|
line.word 0x00 "PPC_PCFGR029,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "PPC_PCFGR030,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x3E++0x1
|
|
line.word 0x00 "PPC_PCFGR031,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "PPC_PCFGR0100,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x42++0x1
|
|
line.word 0x00 "PPC_PCFGR0101,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x46++0x1
|
|
line.word 0x00 "PPC_PCFGR0103,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4A++0x1
|
|
line.word 0x00 "PPC_PCFGR0105,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "PPC_PCFGR0106,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x4E++0x1
|
|
line.word 0x00 "PPC_PCFGR0107,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "PPC_PCFGR0108,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x52++0x1
|
|
line.word 0x00 "PPC_PCFGR0109,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "PPC_PCFGR0112,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5A++0x1
|
|
line.word 0x00 "PPC_PCFGR0113,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "PPC_PCFGR0114,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x5E++0x1
|
|
line.word 0x00 "PPC_PCFGR0115,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x62++0x1
|
|
line.word 0x00 "PPC_PCFGR0117,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "PPC_PCFGR0118,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x66++0x1
|
|
line.word 0x00 "PPC_PCFGR0119,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x68++0x1
|
|
line.word 0x00 "PPC_PCFGR0120,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "PPC_PCFGR0122,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x6E++0x1
|
|
line.word 0x00 "PPC_PCFGR0123,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x74++0x1
|
|
line.word 0x00 "PPC_PCFGR0126,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x76++0x1
|
|
line.word 0x00 "PPC_PCFGR0127,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x78++0x1
|
|
line.word 0x00 "PPC_PCFGR0128,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7A++0x1
|
|
line.word 0x00 "PPC_PCFGR0129,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7C++0x1
|
|
line.word 0x00 "PPC_PCFGR0130,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x7E++0x1
|
|
line.word 0x00 "PPC_PCFGR0131,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "PPC_PCFGR0202,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x86++0x1
|
|
line.word 0x00 "PPC_PCFGR0203,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "PPC_PCFGR0204,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8A++0x1
|
|
line.word 0x00 "PPC_PCFGR0205,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "PPC_PCFGR0206,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "PPC_PCFGR0207,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "PPC_PCFGR0208,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "PPC_PCFGR0209,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "PPC_PCFGR0210,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "PPC_PCFGR0211,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "PPC_PCFGR0212,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "PPC_PCFGR0213,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "PPC_PCFGR0214,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "PPC_PCFGR0215,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "PPC_PCFGR0218,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "PPC_PCFGR0219,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "PPC_PCFGR0220,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "PPC_PCFGR0222,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "PPC_PCFGR0223,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "PPC_PCFGR0224,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "PPC_PCFGR0225,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "PPC_PCFGR0226,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBA++0x1
|
|
line.word 0x00 "PPC_PCFGR0229,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "PPC_PCFGR0230,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xBE++0x1
|
|
line.word 0x00 "PPC_PCFGR0231,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC0++0x1
|
|
line.word 0x00 "PPC_PCFGR0300,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "PPC_PCFGR0301,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "PPC_PCFGR0302,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "PPC_PCFGR0304,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "PPC_PCFGR0305,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "PPC_PCFGR0307,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "PPC_PCFGR0308,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD2++0x1
|
|
line.word 0x00 "PPC_PCFGR0309,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "PPC_PCFGR0312,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "PPC_PCFGR0313,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "PPC_PCFGR0314,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xDE++0x1
|
|
line.word 0x00 "PPC_PCFGR0315,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "PPC_PCFGR0317,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEA++0x1
|
|
line.word 0x00 "PPC_PCFGR0321,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "PPC_PCFGR0322,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "PPC_PCFGR0323,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "PPC_PCFGR0324,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xF6++0x1
|
|
line.word 0x00 "PPC_PCFGR0327,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0xFE++0x1
|
|
line.word 0x00 "PPC_PCFGR0331,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "PPC_PCFGR0400,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "PPC_PCFGR0401,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x104++0x1
|
|
line.word 0x00 "PPC_PCFGR0402,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x106++0x1
|
|
line.word 0x00 "PPC_PCFGR0403,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "PPC_PCFGR0404,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "PPC_PCFGR0405,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "PPC_PCFGR0406,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "PPC_PCFGR0407,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "PPC_PCFGR0408,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "PPC_PCFGR0409,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "PPC_PCFGR0411,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "PPC_PCFGR0413,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "PPC_PCFGR0414,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "PPC_PCFGR0416,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "PPC_PCFGR0417,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "PPC_PCFGR0418,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "PPC_PCFGR0420,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "PPC_PCFGR0421,Port Setting Register"
|
|
rbitfld.word 0x00 15. " POE ,Port output enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " POD ,Port output data bit" "Low,High"
|
|
rbitfld.word 0x00 13. " PID ,Port input data bit" "Low,High"
|
|
bitfld.word 0x00 12. " PIE ,Port input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " PIL ,Input level bit" "CMOS hysteresis input,Automotive input,?..."
|
|
bitfld.word 0x00 9. " PUE ,Pull up enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PDE ,Pull down enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6.--7. " ODR ,Port output drive selection bit" "A,B,C,D"
|
|
textline " "
|
|
bitfld.word 0x00 5. " NFE ,Port noise filter enable select bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--2. " POF ,Port output function selection bit" "ALT_0,ALT_1,ALT_2,ALT_3,ALT_4,ALT_5,ALT_6,ALT_7"
|
|
endif
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x00 "PPC_KEYCDR,PPC Key Code Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RIC"
|
|
base ad:0xB4748000
|
|
width 14.
|
|
sif cpuis("S6J311?JAA")
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "RIC_RESIN6,SIN2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P408,P421,?..."
|
|
group.word 0x0E++0x1
|
|
line.word 0x00 "RIC_RESIN7,SCK2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P411,P420,?..."
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "RIC_RESIN8,SCS2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P413,P001,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "RIC_RESIN12,SIN4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P210,P023,?..."
|
|
group.word 0x1A++0x1
|
|
line.word 0x00 "RIC_RESIN13,SCK4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P207,P021,?..."
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "RIC_RESIN14,SCS4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P211,P025,?..."
|
|
group.word 0x1E++0x1
|
|
line.word 0x00 "RIC_RESIN15,SIN5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P222,P213,?..."
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "RIC_RESIN16,SCK5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P226,P215,?..."
|
|
group.word 0x22++0x1
|
|
line.word 0x00 "RIC_RESIN17,SCS5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P224,P212,?..."
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "RIC_RESIN18,SIN6 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P130,P329,?..."
|
|
group.word 0x26++0x1
|
|
line.word 0x00 "RIC_RESIN19,SCK6 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P202,P327,?..."
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "RIC_RESIN20,SCS6 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P119,P331,?..."
|
|
group.word 0x2A++0x1
|
|
line.word 0x00 "RIC_RESIN21,SIN7 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P319,P416,?..."
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "RIC_RESIN22,SCK7 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P314,P407,?..."
|
|
group.word 0x2E++0x1
|
|
line.word 0x00 "RIC_RESIN23,SCS7 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P315,P410,?..."
|
|
group.word 0x6C++0x1
|
|
line.word 0x00 "RIC_RESIN54,SIN18 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P111,P011,?..."
|
|
group.word 0x6E++0x1
|
|
line.word 0x00 "RIC_RESIN55,SCK18 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P113,P007,?..."
|
|
group.word 0x70++0x1
|
|
line.word 0x00 "RIC_RESIN56,SCS18 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P114,P008,?..."
|
|
group.word 0x72++0x1
|
|
line.word 0x00 "RIC_RESIN57,SIN19 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P107,P109,?..."
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "RIC_RESIN66,RX0 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P307,P229,P225,?..."
|
|
group.word 0x86++0x1
|
|
line.word 0x00 "RIC_RESIN67,RX1 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P402,P318,P107,?..."
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "RIC_RESIN68,INT0 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P225,P009,?..."
|
|
group.word 0x8A++0x1
|
|
line.word 0x00 "RIC_RESIN69,INT1 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P307,P027,?..."
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "RIC_RESIN70,INT2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P402,P107,?..."
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "RIC_RESIN71,INT3 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P022,P108,?..."
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "RIC_RESIN72,INT4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P028,P117,?..."
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "RIC_RESIN73,INT5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P130,P118,?..."
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "RIC_RESIN74,INT6 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P210,P202,?..."
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "RIC_RESIN75,INT7 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P222,P207,?..."
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "RIC_RESIN76,INT8 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P229,P213,?..."
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "RIC_RESIN77,INT9 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P318,P215,?..."
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "RIC_RESIN78,INT10 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P325,P313,?..."
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "RIC_RESIN79,INT11 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P405,P317,?..."
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "RIC_RESIN80,INT12 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P408,P319,?..."
|
|
group.word 0xA2++0x1
|
|
line.word 0x00 "RIC_RESIN81,INT13 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P415,P411,?..."
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "RIC_RESIN82,INT14 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P418,P413,?..."
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "RIC_RESIN83,INT15 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P310,P417,?..."
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "RIC_RESIN84,TEXT0 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P019,P027,?..."
|
|
group.word 0xAA++0x1
|
|
line.word 0x00 "RIC_RESIN85,TEXT1 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P020,P127,?..."
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "RIC_RESIN86,TEXT2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P218,P128,?..."
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "RIC_RESIN87,TEXT3 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P219,P205,?..."
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "RIC_RESIN88,TEXT4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P304,P206,?..."
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "RIC_RESIN89,TEXT5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P305,P207,?..."
|
|
group.byte 0xB4++0x1
|
|
line.byte 0x00 "RIC_RESIN90,OCU0 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN90,OCU1 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xB6++0x1
|
|
line.word 0x00 "RIC_RESIN91,OCU0_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "RIC_RESIN92,OCU0_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xBA++0x1
|
|
line.byte 0x00 "RIC_RESIN93,OCU2 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN93,OCU3 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "RIC_RESIN94,OCU1_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0x0BE++0x1
|
|
line.word 0x00 "RIC_RESIN95,OCU1_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xC0++0x1
|
|
line.byte 0x00 "RIC_RESIN96,OCU4 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN96,OCU5 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "RIC_RESIN97,OCU2_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "RIC_RESIN98,OCU2_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xC6++0x1
|
|
line.byte 0x00 "RIC_RESIN99,OCU6 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN99,OCU7 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "RIC_RESIN100,OCU3_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "RIC_RESIN101,OCU3_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xCC++0x1
|
|
line.byte 0x00 "RIC_RESIN102,OCU8 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN102,OCU9 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "RIC_RESIN103,OCU4_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "RIC_RESIN104,OCU4_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xD2++0x1
|
|
line.byte 0x00 "RIC_RESIN105,OCU10 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN105,OCU11 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "RIC_RESIN106,OCU5_MOD0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.word 0xD6++0x1
|
|
line.word 0x00 "RIC_RESIN107,OCU5_MOD1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "0,1,?..."
|
|
group.byte 0xD8++0x1
|
|
line.byte 0x00 "RIC_RESIN108,ICU0 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN108,ICU1 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "RIC_RESIN109,IN0 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P401,P308,P210,?..."
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "RIC_RESIN110,IN1 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P402,P309,P221,?..."
|
|
group.byte 0xDE++0x1
|
|
line.byte 0x00 "RIC_RESIN111,ICU2 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN111,ICU3 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "RIC_RESIN112,IN2 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P403,P312,P212,?..."
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "RIC_RESIN113,IN3 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P404,P313,P213,?..."
|
|
group.byte 0x0E4++0x1
|
|
line.byte 0x00 "RIC_RESIN114,ICU4 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN114,ICU5 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xE6++0x1
|
|
line.word 0x00 "RIC_RESIN115,IN4 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P405,P314,P214,?..."
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "RIC_RESIN116,IN5 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P416,P315,P215,?..."
|
|
group.byte 0xEA++0x1
|
|
line.byte 0x00 "RIC_RESIN117,ICU6 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN117,ICU7 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "RIC_RESIN118,IN6 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P005,P129,P220,?..."
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "RIC_RESIN119,IN7 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P006,P130,P222,?..."
|
|
group.byte 0xF0++0x1
|
|
line.byte 0x00 "RIC_RESIN120,ICU8 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN120,ICU9 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xF2++0x1
|
|
line.word 0x00 "RIC_RESIN121,IN8 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P007,P131,P223,?..."
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "RIC_RESIN122,IN9 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P008,P202,P224,?..."
|
|
group.byte 0xF6++0x1
|
|
line.byte 0x00 "RIC_RESIN123,ICU10 Resource Input Setting Register"
|
|
bitfld.byte 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
line.byte 0x01 "RIC_RESIN123,ICU11 Resource Input Setting Register"
|
|
bitfld.byte 0x01 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "RIC_RESIN124,IN10 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P009,P203,P225,?..."
|
|
group.word 0xFA++0x1
|
|
line.word 0x00 "RIC_RESIN125,IN11 Resource Input Setting Register"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,Resource selection bit" "P010,P204,P226,?..."
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "RIC_RESIN126,ADC0 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0xFE++0x1
|
|
line.word 0x00 "RIC_RESIN127,ADC1 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "RIC_RESIN128,ADC2 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "RIC_RESIN129,ADC3 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x104++0x1
|
|
line.word 0x00 "RIC_RESIN130,ADC4 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0X106++0x1
|
|
line.word 0x00 "RIC_RESIN131,ADC5 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "RIC_RESIN132,ADC6 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "RIC_RESIN133,ADC7 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "RIC_RESIN134,ADC8 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "RIC_RESIN135,ADC9 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "RIC_RESIN136,ADC10 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "RIC_RESIN137,ADC11 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "RIC_RESIN138,ADC12 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "RIC_RESIN139,ADC13 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "RIC_RESIN140,ADC14 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "RIC_RESIN141,ADC15 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "RIC_RESIN142,ADC16 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "RIC_RESIN143,ADC17 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "RIC_RESIN144,ADC18 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "RIC_RESIN145,ADC19 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "RIC_RESIN146,ADC20 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x126++0x1
|
|
line.word 0x00 "RIC_RESIN147,ADC21 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "RIC_RESIN148,ADC22 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "RIC_RESIN149,ADC23 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x12C++0x1
|
|
line.word 0x00 "RIC_RESIN150,ADC24 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x12E++0x1
|
|
line.word 0x00 "RIC_RESIN151,ADC25 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x130++0x1
|
|
line.word 0x00 "RIC_RESIN152,ADC26 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x132++0x1
|
|
line.word 0x00 "RIC_RESIN153,ADC27 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x134++0x1
|
|
line.word 0x00 "RIC_RESIN154,ADC28 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x136++0x1
|
|
line.word 0x00 "RIC_RESIN155,ADC29 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x138++0x1
|
|
line.word 0x00 "RIC_RESIN156,ADC30 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x13A++0x1
|
|
line.word 0x00 "RIC_RESIN157,ADC31 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x13C++0x1
|
|
line.word 0x00 "RIC_RESIN158,ADC32 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x13E++0x1
|
|
line.word 0x00 "RIC_RESIN159,ADC33 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x140++0x1
|
|
line.word 0x00 "RIC_RESIN160,ADC34 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x142++0x1
|
|
line.word 0x00 "RIC_RESIN161,ADC35 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x144++0x1
|
|
line.word 0x00 "RIC_RESIN162,ADC36 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x146++0x1
|
|
line.word 0x00 "RIC_RESIN163,ADC37 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x148++0x1
|
|
line.word 0x00 "RIC_RESIN164,ADC38 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x14A++0x1
|
|
line.word 0x00 "RIC_RESIN165,ADC39 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x14C++0x1
|
|
line.word 0x00 "RIC_RESIN166,ADC40 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x14E++0x1
|
|
line.word 0x00 "RIC_RESIN167,ADC41 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x150++0x1
|
|
line.word 0x00 "RIC_RESIN168,ADC42 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x152++0x1
|
|
line.word 0x00 "RIC_RESIN169,ADC43 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x154++0x1
|
|
line.word 0x00 "RIC_RESIN170,ADC44 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x156++0x1
|
|
line.word 0x00 "RIC_RESIN171,ADC45 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x158++0x1
|
|
line.word 0x00 "RIC_RESIN172,ADC46 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x15A++0x1
|
|
line.word 0x00 "RIC_RESIN173,ADC47 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x15C++0x1
|
|
line.word 0x00 "RIC_RESIN174,ADC48 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x15E++0x1
|
|
line.word 0x00 "RIC_RESIN175,ADC49 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x160++0x1
|
|
line.word 0x00 "RIC_RESIN176,ADC50 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x162++0x1
|
|
line.word 0x00 "RIC_RESIN177,ADC51 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x164++0x1
|
|
line.word 0x00 "RIC_RESIN178,ADC52 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x166++0x1
|
|
line.word 0x00 "RIC_RESIN179,ADC53 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x168++0x1
|
|
line.word 0x00 "RIC_RESIN180,ADC54 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x16A++0x1
|
|
line.word 0x00 "RIC_RESIN181,ADC55 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x16C++0x1
|
|
line.word 0x00 "RIC_RESIN182,ADC56 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x16E++0x1
|
|
line.word 0x00 "RIC_RESIN183,ADC57 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x170++0x1
|
|
line.word 0x00 "RIC_RESIN184,ADC58 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x172++0x1
|
|
line.word 0x00 "RIC_RESIN185,ADC59 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x174++0x1
|
|
line.word 0x00 "RIC_RESIN186,ADC60 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x176++0x1
|
|
line.word 0x00 "RIC_RESIN187,ADC61 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x178++0x1
|
|
line.word 0x00 "RIC_RESIN188,ADC62 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
group.word 0x17A++0x1
|
|
line.word 0x00 "RIC_RESIN189,ADC63 Resource Input Setting Register"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,Resource selection bit" "FRT0,FRT1,FRT2,FRT3,FRT4,FRT5,?..."
|
|
elif cpuis("S6J311?HAA")
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "RIC_RESIN6,Resource Input Setting Register 6"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "RIC_RESIN7,Resource Input Setting Register 7"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "RIC_RESIN8,Resource Input Setting Register 8"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "RIC_RESIN66,Resource Input Setting Register 66"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "RIC_RESIN68,Resource Input Setting Register 68"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x8A++0x1
|
|
line.word 0x00 "RIC_RESIN69,Resource Input Setting Register 69"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "RIC_RESIN70,Resource Input Setting Register 70"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "RIC_RESIN71,Resource Input Setting Register 71"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "RIC_RESIN72,Resource Input Setting Register 72"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "RIC_RESIN73,Resource Input Setting Register 73"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "RIC_RESIN74,Resource Input Setting Register 74"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "RIC_RESIN75,Resource Input Setting Register 75"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "RIC_RESIN76,Resource Input Setting Register 76"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "RIC_RESIN77,Resource Input Setting Register 77"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "RIC_RESIN78,Resource Input Setting Register 78"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "RIC_RESIN79,Resource Input Setting Register 79"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA2++0x1
|
|
line.word 0x00 "RIC_RESIN81,Resource Input Setting Register 81"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "RIC_RESIN82,Resource Input Setting Register 82"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "RIC_RESIN83,Resource Input Setting Register 83"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "RIC_RESIN84,Resource Input Setting Register 84"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAA++0x1
|
|
line.word 0x00 "RIC_RESIN85,Resource Input Setting Register 85"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "RIC_RESIN86,Resource Input Setting Register 86"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "RIC_RESIN87,Resource Input Setting Register 87"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "RIC_RESIN88,Resource Input Setting Register 88"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "RIC_RESIN89,Resource Input Setting Register 89"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "RIC_RESIN90,Resource Input Setting Register 90"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB6++0x1
|
|
line.word 0x00 "RIC_RESIN91,Resource Input Setting Register 91"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "RIC_RESIN92,Resource Input Setting Register 92"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBA++0x1
|
|
line.word 0x00 "RIC_RESIN93,Resource Input Setting Register 93"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "RIC_RESIN94,Resource Input Setting Register 94"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBE++0x1
|
|
line.word 0x00 "RIC_RESIN95,Resource Input Setting Register 95"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC0++0x1
|
|
line.word 0x00 "RIC_RESIN96,Resource Input Setting Register 96"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "RIC_RESIN97,Resource Input Setting Register 97"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "RIC_RESIN98,Resource Input Setting Register 98"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC6++0x1
|
|
line.word 0x00 "RIC_RESIN99,Resource Input Setting Register 99"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "RIC_RESIN100,Resource Input Setting Register 100"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "RIC_RESIN101,Resource Input Setting Register 101"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "RIC_RESIN102,Resource Input Setting Register 102"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "RIC_RESIN103,Resource Input Setting Register 103"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "RIC_RESIN104,Resource Input Setting Register 104"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD2++0x1
|
|
line.word 0x00 "RIC_RESIN105,Resource Input Setting Register 105"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "RIC_RESIN106,Resource Input Setting Register 106"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD6++0x1
|
|
line.word 0x00 "RIC_RESIN107,Resource Input Setting Register 107"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "RIC_RESIN108,Resource Input Setting Register 108"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "RIC_RESIN109,Resource Input Setting Register 109"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "RIC_RESIN110,Resource Input Setting Register 110"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDE++0x1
|
|
line.word 0x00 "RIC_RESIN111,Resource Input Setting Register 111"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "RIC_RESIN112,Resource Input Setting Register 112"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "RIC_RESIN113,Resource Input Setting Register 113"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE4++0x1
|
|
line.word 0x00 "RIC_RESIN114,Resource Input Setting Register 114"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE6++0x1
|
|
line.word 0x00 "RIC_RESIN115,Resource Input Setting Register 115"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "RIC_RESIN116,Resource Input Setting Register 116"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEA++0x1
|
|
line.word 0x00 "RIC_RESIN117,Resource Input Setting Register 117"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "RIC_RESIN118,Resource Input Setting Register 118"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "RIC_RESIN119,Resource Input Setting Register 119"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "RIC_RESIN120,Resource Input Setting Register 120"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF2++0x1
|
|
line.word 0x00 "RIC_RESIN121,Resource Input Setting Register 121"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "RIC_RESIN122,Resource Input Setting Register 122"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF6++0x1
|
|
line.word 0x00 "RIC_RESIN123,Resource Input Setting Register 123"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "RIC_RESIN124,Resource Input Setting Register 124"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xFA++0x1
|
|
line.word 0x00 "RIC_RESIN125,Resource Input Setting Register 125"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "RIC_RESIN126,Resource Input Setting Register 126"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xFE++0x1
|
|
line.word 0x00 "RIC_RESIN127,Resource Input Setting Register 127"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "RIC_RESIN128,Resource Input Setting Register 128"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "RIC_RESIN129,Resource Input Setting Register 129"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x106++0x1
|
|
line.word 0x00 "RIC_RESIN131,Resource Input Setting Register 131"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "RIC_RESIN132,Resource Input Setting Register 132"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "RIC_RESIN135,Resource Input Setting Register 135"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "RIC_RESIN136,Resource Input Setting Register 136"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "RIC_RESIN138,Resource Input Setting Register 138"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "RIC_RESIN139,Resource Input Setting Register 139"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "RIC_RESIN140,Resource Input Setting Register 140"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "RIC_RESIN141,Resource Input Setting Register 141"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "RIC_RESIN143,Resource Input Setting Register 143"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "RIC_RESIN144,Resource Input Setting Register 144"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "RIC_RESIN145,Resource Input Setting Register 145"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "RIC_RESIN146,Resource Input Setting Register 146"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x126++0x1
|
|
line.word 0x00 "RIC_RESIN147,Resource Input Setting Register 147"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "RIC_RESIN148,Resource Input Setting Register 148"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "RIC_RESIN149,Resource Input Setting Register 149"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x12C++0x1
|
|
line.word 0x00 "RIC_RESIN150,Resource Input Setting Register 150"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x132++0x1
|
|
line.word 0x00 "RIC_RESIN153,Resource Input Setting Register 153"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x134++0x1
|
|
line.word 0x00 "RIC_RESIN154,Resource Input Setting Register 154"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x136++0x1
|
|
line.word 0x00 "RIC_RESIN155,Resource Input Setting Register 155"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x138++0x1
|
|
line.word 0x00 "RIC_RESIN156,Resource Input Setting Register 156"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13A++0x1
|
|
line.word 0x00 "RIC_RESIN157,Resource Input Setting Register 157"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13C++0x1
|
|
line.word 0x00 "RIC_RESIN158,Resource Input Setting Register 158"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13E++0x1
|
|
line.word 0x00 "RIC_RESIN159,Resource Input Setting Register 159"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x140++0x1
|
|
line.word 0x00 "RIC_RESIN160,Resource Input Setting Register 160"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x142++0x1
|
|
line.word 0x00 "RIC_RESIN161,Resource Input Setting Register 161"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x144++0x1
|
|
line.word 0x00 "RIC_RESIN162,Resource Input Setting Register 162"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x146++0x1
|
|
line.word 0x00 "RIC_RESIN163,Resource Input Setting Register 163"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x148++0x1
|
|
line.word 0x00 "RIC_RESIN164,Resource Input Setting Register 164"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14A++0x1
|
|
line.word 0x00 "RIC_RESIN165,Resource Input Setting Register 165"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14C++0x1
|
|
line.word 0x00 "RIC_RESIN166,Resource Input Setting Register 166"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14E++0x1
|
|
line.word 0x00 "RIC_RESIN167,Resource Input Setting Register 167"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x150++0x1
|
|
line.word 0x00 "RIC_RESIN168,Resource Input Setting Register 168"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x152++0x1
|
|
line.word 0x00 "RIC_RESIN169,Resource Input Setting Register 169"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x154++0x1
|
|
line.word 0x00 "RIC_RESIN170,Resource Input Setting Register 170"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x156++0x1
|
|
line.word 0x00 "RIC_RESIN171,Resource Input Setting Register 171"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x158++0x1
|
|
line.word 0x00 "RIC_RESIN172,Resource Input Setting Register 172"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15A++0x1
|
|
line.word 0x00 "RIC_RESIN173,Resource Input Setting Register 173"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15C++0x1
|
|
line.word 0x00 "RIC_RESIN174,Resource Input Setting Register 174"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15E++0x1
|
|
line.word 0x00 "RIC_RESIN175,Resource Input Setting Register 175"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x160++0x1
|
|
line.word 0x00 "RIC_RESIN176,Resource Input Setting Register 176"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x162++0x1
|
|
line.word 0x00 "RIC_RESIN177,Resource Input Setting Register 177"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x164++0x1
|
|
line.word 0x00 "RIC_RESIN178,Resource Input Setting Register 178"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x166++0x1
|
|
line.word 0x00 "RIC_RESIN179,Resource Input Setting Register 179"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x168++0x1
|
|
line.word 0x00 "RIC_RESIN180,Resource Input Setting Register 180"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16A++0x1
|
|
line.word 0x00 "RIC_RESIN181,Resource Input Setting Register 181"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16C++0x1
|
|
line.word 0x00 "RIC_RESIN182,Resource Input Setting Register 182"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16E++0x1
|
|
line.word 0x00 "RIC_RESIN183,Resource Input Setting Register 183"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x170++0x1
|
|
line.word 0x00 "RIC_RESIN184,Resource Input Setting Register 184"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x172++0x1
|
|
line.word 0x00 "RIC_RESIN185,Resource Input Setting Register 185"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x174++0x1
|
|
line.word 0x00 "RIC_RESIN186,Resource Input Setting Register 186"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x176++0x1
|
|
line.word 0x00 "RIC_RESIN187,Resource Input Setting Register 187"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x178++0x1
|
|
line.word 0x00 "RIC_RESIN188,Resource Input Setting Register 188"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif cpuis("S6J312?HAA")
|
|
group.word 0xC++0x1
|
|
line.word 0x00 "RIC_RESIN6,Resource Input Setting Register 6"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE++0x1
|
|
line.word 0x00 "RIC_RESIN7,Resource Input Setting Register 7"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "RIC_RESIN8,Resource Input Setting Register 8"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "RIC_RESIN12,Resource Input Setting Register 12"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1A++0x1
|
|
line.word 0x00 "RIC_RESIN13,Resource Input Setting Register 13"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E++0x1
|
|
line.word 0x00 "RIC_RESIN15,Resource Input Setting Register 15"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "RIC_RESIN16,Resource Input Setting Register 16"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x22++0x1
|
|
line.word 0x00 "RIC_RESIN17,Resource Input Setting Register 17"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x2A++0x1
|
|
line.word 0x00 "RIC_RESIN21,Resource Input Setting Register 21"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "RIC_RESIN22,Resource Input Setting Register 22"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "RIC_RESIN66,Resource Input Setting Register 66"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x86++0x1
|
|
line.word 0x00 "RIC_RESIN67,Resource Input Setting Register 67"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "RIC_RESIN68,Resource Input Setting Register 68"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "RIC_RESIN70,Resource Input Setting Register 70"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x8E++0x1
|
|
line.word 0x00 "RIC_RESIN71,Resource Input Setting Register 71"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "RIC_RESIN72,Resource Input Setting Register 72"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x92++0x1
|
|
line.word 0x00 "RIC_RESIN73,Resource Input Setting Register 73"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "RIC_RESIN74,Resource Input Setting Register 74"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x96++0x1
|
|
line.word 0x00 "RIC_RESIN75,Resource Input Setting Register 75"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "RIC_RESIN76,Resource Input Setting Register 76"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9A++0x1
|
|
line.word 0x00 "RIC_RESIN77,Resource Input Setting Register 77"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "RIC_RESIN78,Resource Input Setting Register 78"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x9E++0x1
|
|
line.word 0x00 "RIC_RESIN79,Resource Input Setting Register 79"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "RIC_RESIN80,Resource Input Setting Register 80"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA2++0x1
|
|
line.word 0x00 "RIC_RESIN81,Resource Input Setting Register 81"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "RIC_RESIN82,Resource Input Setting Register 82"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA6++0x1
|
|
line.word 0x00 "RIC_RESIN83,Resource Input Setting Register 83"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "RIC_RESIN84,Resource Input Setting Register 84"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAA++0x1
|
|
line.word 0x00 "RIC_RESIN85,Resource Input Setting Register 85"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "RIC_RESIN86,Resource Input Setting Register 86"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xAE++0x1
|
|
line.word 0x00 "RIC_RESIN87,Resource Input Setting Register 87"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "RIC_RESIN88,Resource Input Setting Register 88"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB2++0x1
|
|
line.word 0x00 "RIC_RESIN89,Resource Input Setting Register 89"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "RIC_RESIN90,Resource Input Setting Register 90"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB6++0x1
|
|
line.word 0x00 "RIC_RESIN91,Resource Input Setting Register 91"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "RIC_RESIN92,Resource Input Setting Register 92"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBA++0x1
|
|
line.word 0x00 "RIC_RESIN93,Resource Input Setting Register 93"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "RIC_RESIN94,Resource Input Setting Register 94"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xBE++0x1
|
|
line.word 0x00 "RIC_RESIN95,Resource Input Setting Register 95"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC0++0x1
|
|
line.word 0x00 "RIC_RESIN96,Resource Input Setting Register 96"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC2++0x1
|
|
line.word 0x00 "RIC_RESIN97,Resource Input Setting Register 97"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "RIC_RESIN98,Resource Input Setting Register 98"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC6++0x1
|
|
line.word 0x00 "RIC_RESIN99,Resource Input Setting Register 99"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "RIC_RESIN100,Resource Input Setting Register 100"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCA++0x1
|
|
line.word 0x00 "RIC_RESIN101,Resource Input Setting Register 101"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "RIC_RESIN102,Resource Input Setting Register 102"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xCE++0x1
|
|
line.word 0x00 "RIC_RESIN103,Resource Input Setting Register 103"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "RIC_RESIN104,Resource Input Setting Register 104"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD2++0x1
|
|
line.word 0x00 "RIC_RESIN105,Resource Input Setting Register 105"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "RIC_RESIN106,Resource Input Setting Register 106"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD6++0x1
|
|
line.word 0x00 "RIC_RESIN107,Resource Input Setting Register 107"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "RIC_RESIN108,Resource Input Setting Register 108"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDA++0x1
|
|
line.word 0x00 "RIC_RESIN109,Resource Input Setting Register 109"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "RIC_RESIN110,Resource Input Setting Register 110"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xDE++0x1
|
|
line.word 0x00 "RIC_RESIN111,Resource Input Setting Register 111"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "RIC_RESIN112,Resource Input Setting Register 112"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE2++0x1
|
|
line.word 0x00 "RIC_RESIN113,Resource Input Setting Register 113"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE4++0x1
|
|
line.word 0x00 "RIC_RESIN114,Resource Input Setting Register 114"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE6++0x1
|
|
line.word 0x00 "RIC_RESIN115,Resource Input Setting Register 115"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "RIC_RESIN116,Resource Input Setting Register 116"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEA++0x1
|
|
line.word 0x00 "RIC_RESIN117,Resource Input Setting Register 117"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "RIC_RESIN118,Resource Input Setting Register 118"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xEE++0x1
|
|
line.word 0x00 "RIC_RESIN119,Resource Input Setting Register 119"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "RIC_RESIN120,Resource Input Setting Register 120"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF2++0x1
|
|
line.word 0x00 "RIC_RESIN121,Resource Input Setting Register 121"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "RIC_RESIN122,Resource Input Setting Register 122"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF6++0x1
|
|
line.word 0x00 "RIC_RESIN123,Resource Input Setting Register 123"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "RIC_RESIN124,Resource Input Setting Register 124"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0xFA++0x1
|
|
line.word 0x00 "RIC_RESIN125,Resource Input Setting Register 125"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x102++0x1
|
|
line.word 0x00 "RIC_RESIN129,Resource Input Setting Register 129"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x104++0x1
|
|
line.word 0x00 "RIC_RESIN130,Resource Input Setting Register 130"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x106++0x1
|
|
line.word 0x00 "RIC_RESIN131,Resource Input Setting Register 131"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "RIC_RESIN132,Resource Input Setting Register 132"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "RIC_RESIN135,Resource Input Setting Register 135"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "RIC_RESIN136,Resource Input Setting Register 136"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "RIC_RESIN138,Resource Input Setting Register 138"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "RIC_RESIN139,Resource Input Setting Register 139"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "RIC_RESIN140,Resource Input Setting Register 140"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "RIC_RESIN141,Resource Input Setting Register 141"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "RIC_RESIN143,Resource Input Setting Register 143"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x120++0x1
|
|
line.word 0x00 "RIC_RESIN144,Resource Input Setting Register 144"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x122++0x1
|
|
line.word 0x00 "RIC_RESIN145,Resource Input Setting Register 145"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x124++0x1
|
|
line.word 0x00 "RIC_RESIN146,Resource Input Setting Register 146"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x126++0x1
|
|
line.word 0x00 "RIC_RESIN147,Resource Input Setting Register 147"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x128++0x1
|
|
line.word 0x00 "RIC_RESIN148,Resource Input Setting Register 148"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x12A++0x1
|
|
line.word 0x00 "RIC_RESIN149,Resource Input Setting Register 149"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x12C++0x1
|
|
line.word 0x00 "RIC_RESIN150,Resource Input Setting Register 150"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x132++0x1
|
|
line.word 0x00 "RIC_RESIN153,Resource Input Setting Register 153"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x134++0x1
|
|
line.word 0x00 "RIC_RESIN154,Resource Input Setting Register 154"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x136++0x1
|
|
line.word 0x00 "RIC_RESIN155,Resource Input Setting Register 155"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x138++0x1
|
|
line.word 0x00 "RIC_RESIN156,Resource Input Setting Register 156"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13A++0x1
|
|
line.word 0x00 "RIC_RESIN157,Resource Input Setting Register 157"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13C++0x1
|
|
line.word 0x00 "RIC_RESIN158,Resource Input Setting Register 158"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x13E++0x1
|
|
line.word 0x00 "RIC_RESIN159,Resource Input Setting Register 159"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x140++0x1
|
|
line.word 0x00 "RIC_RESIN160,Resource Input Setting Register 160"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x142++0x1
|
|
line.word 0x00 "RIC_RESIN161,Resource Input Setting Register 161"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x144++0x1
|
|
line.word 0x00 "RIC_RESIN162,Resource Input Setting Register 162"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x146++0x1
|
|
line.word 0x00 "RIC_RESIN163,Resource Input Setting Register 163"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x148++0x1
|
|
line.word 0x00 "RIC_RESIN164,Resource Input Setting Register 164"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14A++0x1
|
|
line.word 0x00 "RIC_RESIN165,Resource Input Setting Register 165"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14C++0x1
|
|
line.word 0x00 "RIC_RESIN166,Resource Input Setting Register 166"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x14E++0x1
|
|
line.word 0x00 "RIC_RESIN167,Resource Input Setting Register 167"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x150++0x1
|
|
line.word 0x00 "RIC_RESIN168,Resource Input Setting Register 168"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x152++0x1
|
|
line.word 0x00 "RIC_RESIN169,Resource Input Setting Register 169"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x158++0x1
|
|
line.word 0x00 "RIC_RESIN172,Resource Input Setting Register 172"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15A++0x1
|
|
line.word 0x00 "RIC_RESIN173,Resource Input Setting Register 173"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15C++0x1
|
|
line.word 0x00 "RIC_RESIN174,Resource Input Setting Register 174"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x15E++0x1
|
|
line.word 0x00 "RIC_RESIN175,Resource Input Setting Register 175"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x160++0x1
|
|
line.word 0x00 "RIC_RESIN176,Resource Input Setting Register 176"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x162++0x1
|
|
line.word 0x00 "RIC_RESIN177,Resource Input Setting Register 177"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x164++0x1
|
|
line.word 0x00 "RIC_RESIN178,Resource Input Setting Register 178"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x166++0x1
|
|
line.word 0x00 "RIC_RESIN179,Resource Input Setting Register 179"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16A++0x1
|
|
line.word 0x00 "RIC_RESIN181,Resource Input Setting Register 181"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16C++0x1
|
|
line.word 0x00 "RIC_RESIN182,Resource Input Setting Register 182"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x16E++0x1
|
|
line.word 0x00 "RIC_RESIN183,Resource Input Setting Register 183"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x170++0x1
|
|
line.word 0x00 "RIC_RESIN184,Resource Input Setting Register 184"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x172++0x1
|
|
line.word 0x00 "RIC_RESIN185,Resource Input Setting Register 185"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x174++0x1
|
|
line.word 0x00 "RIC_RESIN186,Resource Input Setting Register 186"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x176++0x1
|
|
line.word 0x00 "RIC_RESIN187,Resource Input Setting Register 187"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x178++0x1
|
|
line.word 0x00 "RIC_RESIN188,Resource Input Setting Register 188"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x17C++0x1
|
|
line.word 0x00 "RIC_RESIN190,Resource Input Setting Register 190"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x182++0x1
|
|
line.word 0x00 "RIC_RESIN193,Resource Input Setting Register 193"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x184++0x1
|
|
line.word 0x00 "RIC_RESIN194,Resource Input Setting Register 194"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x186++0x1
|
|
line.word 0x00 "RIC_RESIN195,Resource Input Setting Register 195"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x188++0x1
|
|
line.word 0x00 "RIC_RESIN196,Resource Input Setting Register 196"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x18A++0x1
|
|
line.word 0x00 "RIC_RESIN197,Resource Input Setting Register 197"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x190++0x1
|
|
line.word 0x00 "RIC_RESIN200,Resource Input Setting Register 200"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x194++0x1
|
|
line.word 0x00 "RIC_RESIN202,Resource Input Setting Register 202"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x19A++0x1
|
|
line.word 0x00 "RIC_RESIN205,Resource Input Setting Register 205"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x19E++0x1
|
|
line.word 0x00 "RIC_RESIN207,Resource Input Setting Register 207"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1A0++0x1
|
|
line.word 0x00 "RIC_RESIN208,Resource Input Setting Register 208"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1A2++0x1
|
|
line.word 0x00 "RIC_RESIN209,Resource Input Setting Register 209"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1A6++0x1
|
|
line.word 0x00 "RIC_RESIN211,Resource Input Setting Register 211"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1A8++0x1
|
|
line.word 0x00 "RIC_RESIN212,Resource Input Setting Register 212"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1AA++0x1
|
|
line.word 0x00 "RIC_RESIN213,Resource Input Setting Register 213"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1AE++0x1
|
|
line.word 0x00 "RIC_RESIN215,Resource Input Setting Register 215"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1B0++0x1
|
|
line.word 0x00 "RIC_RESIN216,Resource Input Setting Register 216"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1B2++0x1
|
|
line.word 0x00 "RIC_RESIN217,Resource Input Setting Register 217"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1B4++0x1
|
|
line.word 0x00 "RIC_RESIN218,Resource Input Setting Register 218"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1B6++0x1
|
|
line.word 0x00 "RIC_RESIN219,Resource Input Setting Register 219"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1B8++0x1
|
|
line.word 0x00 "RIC_RESIN220,Resource Input Setting Register 220"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1BA++0x1
|
|
line.word 0x00 "RIC_RESIN221,Resource Input Setting Register 221"
|
|
bitfld.word 0x00 8.--11. " PORTSEL ,PORTSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " RESSEL ,RESSEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
wgroup.long 0x1400++0x3
|
|
line.long 0x00 "PPC_KEYCDR,PPC Key Code Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PPU (Peripheral Protection Unit)"
|
|
base ad:0xB4750000
|
|
width 13.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "PPU0_CR,PPU Control Register"
|
|
bitfld.long 0x00 29. " MODE ,PPU mode bit" "R/W,R/A"
|
|
bitfld.long 0x00 23. " VCLR ,PPU violation information clear" "No effect,Clear"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "PPU0_SR,PPU Status Register"
|
|
bitfld.long 0x00 23. " VD ,Violation detection bit" "Not generated,Generated"
|
|
bitfld.long 0x00 22. " VP ,Violation privileged level bit" "User,Privilege"
|
|
bitfld.long 0x00 21. " VW ,Violation write access bit" "Read,Write"
|
|
bitfld.long 0x00 16.--20. " VL ,Violation location" ",MCU Config,,Memory Config,CPERI0,CPERI1,CPERI2,EBI,SHE,DDRHSSPI,Application specific area 0,Application specific area 1,Application specific area 2,Application specific area 3,Application specific area 4,Application specific area 5,Application specific area 6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " LST ,Lock status bit" "Unlocked,Locked"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x00 "PPU0_UNLOCK,PPU Unlock Register"
|
|
if (((d.l(ad:0xB4750000+0x04))&0x01)==0x00)
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "PPU0_PPR0,PPU Privileged Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "PPU0_PPR1,PPU Privileged Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "PPU0_PPR2,PPU Privileged Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "PPU0_PPR3,PPU Privileged Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "PPU0_PPR5,PPU Privileged Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "PPU0_PPR6,PPU Privileged Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "PPU0_PPR7,PPU Privileged Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PPU0_PPR8,PPU Privileged Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "PPU0_PPR9,PPU Privileged Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "PPU0_PPR0,PPU Privileged Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "PPU0_PPR1,PPU Privileged Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "PPU0_PPR2,PPU Privileged Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "PPU0_PPR3,PPU Privileged Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "PPU0_PPR4,PPU Privileged Read Attribute Register 4"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "PPU0_PPR5,PPU Privileged Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "PPU0_PPR6,PPU Privileged Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x9C++0x3
|
|
line.long 0x00 "PPU0_PPR7,PPU Privileged Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "PPU0_PPR8,PPU Privileged Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "PPU0_PPR9,PPU Privileged Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "PPU0_PPR10,PPU Privileged Read Attribute Register 10"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0xF8++0x3
|
|
line.long 0x00 "PPU0_LOCK0,PPU Unlock Register 0"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "PPU0_PUR0,PPU User Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "PPU0_PUR1,PPU User Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "PPU0_PUR2,PPU User Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "PPU0_PUR3,PPU User Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "PPU0_PUR5,PPU User Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "PPU0_PUR6,PPU User Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "PPU0_PUR7,PPU User Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "PPU0_PUR8,PPU User Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "PPU0_PUR9,PPU User Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "PPU0_PUR0,PPU User Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "PPU0_PUR1,PPU User Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "PPU0_PUR2,PPU User Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "PPU0_PUR3,PPU User Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "PPU0_PUR4,PPU User Read Attribute Register 4"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "PPU0_PUR5,PPU User Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "PPU0_PUR6,PPU User Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x11C++0x3
|
|
line.long 0x00 "PPU0_PUR7,PPU User Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "PPU0_PUR8,PPU User Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "PPU0_PUR9,PPU User Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "PPU0_PUR10,PPU User Read Attribute Register 10"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x178++0x3
|
|
line.long 0x00 "PPU0_LOCK1,PPU Unlock Register 1"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "PPU0_PPWA0,PPU Privileged Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PPU0_PPWA1,PPU Privileged Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "PPU0_PPWA2,PPU Privileged Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "PPU0_PPWA3,PPU Privileged Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "PPU0_PPWA5,PPU Privileged Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "PPU0_PPWA6,PPU Privileged Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "PPU0_PPWA7,PPU Privileged Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "PPU0_PPWA8,PPU Privileged Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "PPU0_PPWA9,PPU Privileged Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "PPU0_PPWA0,PPU Privileged Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x184++0x3
|
|
line.long 0x00 "PPU0_PPWA1,PPU Privileged Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x188++0x3
|
|
line.long 0x00 "PPU0_PPWA2,PPU Privileged Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x18C++0x3
|
|
line.long 0x00 "PPU0_PPWA3,PPU Privileged Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x190++0x3
|
|
line.long 0x00 "PPU0_PPWA4,PPU Privileged Write or Access Attribute Register 4"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x194++0x3
|
|
line.long 0x00 "PPU0_PPWA5,PPU Privileged Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x198++0x3
|
|
line.long 0x00 "PPU0_PPWA6,PPU Privileged Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x19C++0x3
|
|
line.long 0x00 "PPU0_PPWA7,PPU Privileged Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "PPU0_PPWA8,PPU Privileged Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x1A4++0x3
|
|
line.long 0x00 "PPU0_PPWA9,PPU Privileged Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x1A8++0x3
|
|
line.long 0x00 "PPU0_PPWA10,PPU Privileged Write or Access Attribute Register 10"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1F8++0x3
|
|
line.long 0x00 "PPU0_LOCK2,PPU0 Unlock Register 2"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "PPU0_PUWA0,PPU User Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "PPU0_PUWA1,PPU User Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "PPU0_PUWA2,PPU User Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x20C++0x3
|
|
line.long 0x00 "PPU0_PUWA3,PPU User Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x214++0x3
|
|
line.long 0x00 "PPU0_PUWA5,PPU User Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "PPU0_PUWA6,PPU User Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x21C++0x3
|
|
line.long 0x00 "PPU0_PUWA7,PPU User Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "PPU0_PUWA8,PPU User Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x224++0x3
|
|
line.long 0x00 "PPU0_PUWA9,PPU User Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "PPU0_PUWA0,PPU User Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x204++0x3
|
|
line.long 0x00 "PPU0_PUWA1,PPU User Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x208++0x3
|
|
line.long 0x00 "PPU0_PUWA2,PPU User Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x20C++0x3
|
|
line.long 0x00 "PPU0_PUWA3,PPU User Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "PPU0_PUWA4,PPU User Write or Access Attribute Register 4"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x214++0x3
|
|
line.long 0x00 "PPU0_PUWA5,PPU User Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x218++0x3
|
|
line.long 0x00 "PPU0_PUWA6,PPU User Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x21C++0x3
|
|
line.long 0x00 "PPU0_PUWA7,PPU User Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "PPU0_PUWA8,PPU User Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x224++0x3
|
|
line.long 0x00 "PPU0_PUWA9,PPU User Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
group.long 0x228++0x3
|
|
line.long 0x00 "PPU0_PUWA10,PPU User Write or Access Attribute Register 10"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1F8++0x3
|
|
line.long 0x00 "PPU0_LOCK3,PPU0 Unlock Register 3"
|
|
else
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "PPU0_PPR0,PPU Privileged Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "PPU0_PPR1,PPU Privileged Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "PPU0_PPR2,PPU Privileged Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x00 "PPU0_PPR3,PPU Privileged Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "PPU0_PPR5,PPU Privileged Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "PPU0_PPR6,PPU Privileged Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x9C++0x3
|
|
line.long 0x00 "PPU0_PPR7,PPU Privileged Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "PPU0_PPR8,PPU Privileged Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x00 "PPU0_PPR9,PPU Privileged Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x00 "PPU0_PPR0,PPU Privileged Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "PPU0_PPR1,PPU Privileged Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x00 "PPU0_PPR2,PPU Privileged Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x00 "PPU0_PPR3,PPU Privileged Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x00 "PPU0_PPR4,PPU Privileged Read Attribute Register 4"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x00 "PPU0_PPR5,PPU Privileged Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "PPU0_PPR6,PPU Privileged Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x9C++0x3
|
|
line.long 0x00 "PPU0_PPR7,PPU Privileged Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "PPU0_PPR8,PPU Privileged Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x00 "PPU0_PPR9,PPU Privileged Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x00 "PPU0_PPR10,PPU Privileged Read Attribute Register 10"
|
|
bitfld.long 0x00 31. " PPR_[31] ,PPU privileged mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged mode read attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0xF8++0x3
|
|
line.long 0x00 "PPU0_LOCK0,PPU Unlock Register 0"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "PPU0_PUR0,PPU User Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x00 "PPU0_PUR1,PPU User Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x00 "PPU0_PUR2,PPU User Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x00 "PPU0_PUR3,PPU User Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "PPU0_PUR5,PPU User Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x118++0x3
|
|
line.long 0x00 "PPU0_PUR6,PPU User Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "PPU0_PUR7,PPU User Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "PPU0_PUR8,PPU User Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "PPU0_PUR9,PPU User Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x100++0x3
|
|
line.long 0x00 "PPU0_PUR0,PPU User Read Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x104++0x3
|
|
line.long 0x00 "PPU0_PUR1,PPU User Read Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x108++0x3
|
|
line.long 0x00 "PPU0_PUR2,PPU User Read Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x10C++0x3
|
|
line.long 0x00 "PPU0_PUR3,PPU User Read Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x00 "PPU0_PUR4,PPU User Read Attribute Register 4"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x114++0x3
|
|
line.long 0x00 "PPU0_PUR5,PPU User Read Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x118++0x3
|
|
line.long 0x00 "PPU0_PUR6,PPU User Read Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x11C++0x3
|
|
line.long 0x00 "PPU0_PUR7,PPU User Read Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x120++0x3
|
|
line.long 0x00 "PPU0_PUR8,PPU User Read Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "PPU0_PUR9,PPU User Read Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x128++0x3
|
|
line.long 0x00 "PPU0_PUR10,PPU User Read Attribute Register 10"
|
|
bitfld.long 0x00 31. " PUR_[31] ,PPU user mode read attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user mode read attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user mode read attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user mode read attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user mode read attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user mode read attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user mode read attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user mode read attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user mode read attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user mode read attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user mode read attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user mode read attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user mode read attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user mode read attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user mode read attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user mode read attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user mode read attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user mode read attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user mode read attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user mode read attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user mode read attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user mode read attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user mode read attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user mode read attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user mode read attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user mode read attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user mode read attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user mode read attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user mode read attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user mode read attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user mode read attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user mode read attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x178++0x3
|
|
line.long 0x00 "PPU0_LOCK1,PPU Unlock Register 1"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x00 "PPU0_PPWA0,PPU Privileged Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x184++0x3
|
|
line.long 0x00 "PPU0_PPWA1,PPU Privileged Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x00 "PPU0_PPWA2,PPU Privileged Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x18C++0x3
|
|
line.long 0x00 "PPU0_PPWA3,PPU Privileged Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x194++0x3
|
|
line.long 0x00 "PPU0_PPWA5,PPU Privileged Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x198++0x3
|
|
line.long 0x00 "PPU0_PPWA6,PPU Privileged Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "PPU0_PPWA7,PPU Privileged Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x1A0++0x3
|
|
line.long 0x00 "PPU0_PPWA8,PPU Privileged Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x1A4++0x3
|
|
line.long 0x00 "PPU0_PPWA9,PPU Privileged Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x180++0x3
|
|
line.long 0x00 "PPU0_PPWA0,PPU Privileged Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x184++0x3
|
|
line.long 0x00 "PPU0_PPWA1,PPU Privileged Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x188++0x3
|
|
line.long 0x00 "PPU0_PPWA2,PPU Privileged Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x18C++0x3
|
|
line.long 0x00 "PPU0_PPWA3,PPU Privileged Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x190++0x3
|
|
line.long 0x00 "PPU0_PPWA4,PPU Privileged Write or Access Attribute Register 4"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x194++0x3
|
|
line.long 0x00 "PPU0_PPWA5,PPU Privileged Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x198++0x3
|
|
line.long 0x00 "PPU0_PPWA6,PPU Privileged Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x19C++0x3
|
|
line.long 0x00 "PPU0_PPWA7,PPU Privileged Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x1A0++0x3
|
|
line.long 0x00 "PPU0_PPWA8,PPU Privileged Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x1A4++0x3
|
|
line.long 0x00 "PPU0_PPWA9,PPU Privileged Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x1A8++0x3
|
|
line.long 0x00 "PPU0_PPWA10,PPU Privileged Write or Access Attribute Register 10"
|
|
bitfld.long 0x00 31. " PPWA_[31] ,PPU privileged write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU privileged write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU privileged write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU privileged write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU privileged write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU privileged write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU privileged write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU privileged write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU privileged write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU privileged write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU privileged write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU privileged write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU privileged write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU privileged write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU privileged write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU privileged write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU privileged write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU privileged write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU privileged write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU privileged write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU privileged write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU privileged write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU privileged write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU privileged write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU privileged write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU privileged write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU privileged write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU privileged write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU privileged write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU privileged write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU privileged write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU privileged write or access attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x1F8++0x3
|
|
line.long 0x00 "PPU0_LOCK2,PPU0 Unlock Register 2"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "PPU0_PUWA0,PPU User Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x00 "PPU0_PUWA1,PPU User Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "PPU0_PUWA2,PPU User Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x00 "PPU0_PUWA3,PPU User Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x00 "PPU0_PUWA5,PPU User Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x00 "PPU0_PUWA6,PPU User Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x00 "PPU0_PUWA7,PPU User Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "PPU0_PUWA8,PPU User Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "PPU0_PUWA9,PPU User Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x200++0x3
|
|
line.long 0x00 "PPU0_PUWA0,PPU User Write or Access Attribute Register 0"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x204++0x3
|
|
line.long 0x00 "PPU0_PUWA1,PPU User Write or Access Attribute Register 1"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x208++0x3
|
|
line.long 0x00 "PPU0_PUWA2,PPU User Write or Access Attribute Register 2"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x20C++0x3
|
|
line.long 0x00 "PPU0_PUWA3,PPU User Write or Access Attribute Register 3"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "PPU0_PUWA4,PPU User Write or Access Attribute Register 4"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x214++0x3
|
|
line.long 0x00 "PPU0_PUWA5,PPU User Write or Access Attribute Register 5"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x00 "PPU0_PUWA6,PPU User Write or Access Attribute Register 6"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x21C++0x3
|
|
line.long 0x00 "PPU0_PUWA7,PPU User Write or Access Attribute Register 7"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x220++0x3
|
|
line.long 0x00 "PPU0_PUWA8,PPU User Write or Access Attribute Register 8"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x224++0x3
|
|
line.long 0x00 "PPU0_PUWA9,PPU User Write or Access Attribute Register 9"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x00 "PPU0_PUWA10,PPU User Write or Access Attribute Register 10"
|
|
bitfld.long 0x00 31. " PUWA_[31] ,PPU user write or access attribute bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,PPU user write or access attribute bit 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,PPU user write or access attribute bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,PPU user write or access attribute bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,PPU user write or access attribute bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,PPU user write or access attribute bit 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,PPU user write or access attribute bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,PPU user write or access attribute bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,PPU user write or access attribute bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,PPU user write or access attribute bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,PPU user write or access attribute bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,PPU user write or access attribute bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,PPU user write or access attribute bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,PPU user write or access attribute bit 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,PPU user write or access attribute bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,PPU user write or access attribute bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,PPU user write or access attribute bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,PPU user write or access attribute bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,PPU user write or access attribute bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,PPU user write or access attribute bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,PPU user write or access attribute bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,PPU user write or access attribute bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,PPU user write or access attribute bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,PPU user write or access attribute bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,PPU user write or access attribute bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,PPU user write or access attribute bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,PPU user write or access attribute bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,PPU user write or access attribute bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,PPU user write or access attribute bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,PPU user write or access attribute bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,PPU user write or access attribute bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,PPU user write or access attribute bit 0" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x278++0x03
|
|
line.long 0x00 "PPU0_LOCK3,PPU Unlock Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("S6J312?HAA")
|
|
tree "DDRHSSPI (DDR HIGH SPEED SPI CONTROLER)"
|
|
base ad:0xB0101000
|
|
width 29.
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DDRHSSPI0_MCTRL,Module Control Register"
|
|
bitfld.long 0x00 5. " DLPEN ,Data learning pattern enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MES ,Module enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSEN ,Command sequencer mode enable" "Direct Mode,Command Sequencer Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "DDRHSSPI0_MCTRL,Module Control Register"
|
|
bitfld.long 0x00 4. " MES ,Module enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSEN ,Command sequencer mode enable" "Direct Mode,Command Sequencer Mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MEN ,Module enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.b(ad:0xB0101000+0x3B)&0x20)==0x20)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC0,Peripheral Communication Configuration Register 0"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.l(ad:0xB0101000+0x14C)&0x08)==0x08)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC0,Peripheral Communication Configuration Register 0"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC0,Peripheral Communication Configuration Register 0"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC0,Peripheral Communication Configuration Register 0"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
endif
|
|
if ((per.b(ad:0xB0101000+0x3B)&0x20)==0x20)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC1,Peripheral Communication Configuration Register 1"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.l(ad:0xB0101000+0x14C)&0x08)==0x08)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC1,Peripheral Communication Configuration Register 1"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC1,Peripheral Communication Configuration Register 1"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC1,Peripheral Communication Configuration Register 1"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
endif
|
|
if ((per.b(ad:0xB0101000+0x3B)&0x20)==0x20)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC2,Peripheral Communication Configuration Register 2"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.l(ad:0xB0101000+0x14C)&0x08)==0x08)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC2,Peripheral Communication Configuration Register 2"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC2,Peripheral Communication Configuration Register 2"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC2,Peripheral Communication Configuration Register 2"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
endif
|
|
if ((per.b(ad:0xB0101000+0x3B)&0x20)==0x20)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC3,Peripheral Communication Configuration Register 3"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.l(ad:0xB0101000+0x14C)&0x08)==0x08)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC3,Peripheral Communication Configuration Register 3"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",3.5xSCLK,4.0xSCLK,4.5xSCLK,5.0xSCLK,5.5xSCLK,6.0xSCLK,6.5xSCLK,7.0xSCLK,7.5xSCLK,8.0xSCLK,8.5xSCLK,9.0xSCLK,9.5xSCLK,10.0xSCLK,10.5xSCLK,11.0xSCLK,11.5xSCLK,12.0xSCLK,12.5xSCLK,13.0xSCLK,13.5xSCLK,14.0xSCLK,14.5xSCLK,15.0xSCLK,15.5xSCLK,16.0xSCLK,16.5xSCLK,17.0xSCLK,17.5xSCLK,18.0xSCLK,18.5xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC3,Peripheral Communication Configuration Register 3"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
elif ((per.b(ad:0xB0101000+0x3B)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DDRHSSPI0_PCC3,Peripheral Communication Configuration Register 3"
|
|
bitfld.long 0x00 16.--20. " SSELDEASRT ,Slave selection deassertion timeout" ",4xSCLK,5xSCLK,6xSCLK,7xSCLK,8xSCLK,9xSCLK,10xSCLK,11xSCLK,12xSCLK,13xSCLK,14xSCLK,15xSCLK,16xSCLK,17xSCLK,18xSCLK,19xSCLK,20xSCLK,21xSCLK,22xSCLK,23xSCLK,24xSCLK,25xSCLK,26xSCLK,27xSCLK,28xSCLK,29xSCLK,30xSCLK,31xSCLK,32xSCLK,33xSCLK,34xSCLK"
|
|
bitfld.long 0x00 9.--12. " CDRS ,Clock division ratio select for peripheral" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32"
|
|
bitfld.long 0x00 5.--6. " SS2CD ,Slave select to clock delay" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ACES ,Active clock edges are same or peripheral" "No,Yes"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXF,TX Interrupt Flag Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TSSRS_set/clr ,Slave select released" "Not generated,Generated"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " TFMTS_set/clr ,TX-FIFO fill level is more than threshold" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " TFLETS_set/clr ,TX-FIFO fill level is less than or equal to threshold" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TFOS_set/clr ,TX-FIFO overrun" "No,Yes"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TFES_set/clr ,TX-FIFO and shift register are empty" "Not empty,Empty"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TFFS_set/clr ,TX-FIFO full" "Not full,Full"
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DDRHSSPI0_RXF,RX Interrupt Flag Register"
|
|
bitfld.long 0x00 8. " TEST ,Test" "0,1"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DLPERR_set/clr ,Data learning pattern reception error" "No error,Error"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RSSRS_set/clr ,Slave select released" "Not generated,Generated"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " RFMTS_set/clr ,RX-FIFO fill level is more than threshold" "No,Yes"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " RFLETS_set/clr ,RX-FIFO fill level is less than or equal to threshold" "No,Yes"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " RFUS_set/clr ,RX-FIFO underrun" "No,Yes"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RFES_set/clr ,RX-FIFO empty" "Not empty,Empty"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " RFFS_set/clr ,RX-FIFO full" "Not full,Full"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DDRHSSPI0_RXF,RX Interrupt Flag Register"
|
|
bitfld.long 0x00 8. " TEST ,Test" "0,1"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "DDRHSSPI0_FAULTF,Fault Status Flag Register"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " DLPFS_set/clr ,DLP error fault" "Not detected,Detected"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DRCBSFS_set/clr ,DMA read channel block size fault" "Not detected,Detected"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DWCBSFS_set/clr ,DMA write channel block size fault" "Not detected,Detected"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " PVFS_set/clr ,Protection violation fault" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " UMAFS_set/clr ,Unmapped memory access fault" "Not detected,Detected"
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.byte 0x34++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMCFG,Direct Mode Configuration Register"
|
|
bitfld.byte 0x00 1. " SSDC ,Slave select deassertion control" ",Byte counter mode"
|
|
group.byte 0x35++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMAEN,DMA Enable Register"
|
|
bitfld.byte 0x00 1. " TXDMAEN ,TX DMA enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " RXDMAEN ,RX DMA enable" "Disabled,Enabled"
|
|
group.byte 0x38++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMSTART,Direct Mode Start Register"
|
|
bitfld.byte 0x00 0. " START ,Start transfer" "No effect,Start"
|
|
group.byte 0x3A++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMPSEL,Direct Mode Peripheral Select Register"
|
|
bitfld.byte 0x00 0.--1. " PSEL ,Peripheral select" "0,1,2,3"
|
|
else
|
|
hgroup.byte 0x34++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_DMCFG,Direct Mode Configuration Register"
|
|
hgroup.byte 0x35++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_DMAEN,DMA Enable Register"
|
|
hgroup.byte 0x38++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_DMSTART,Direct Mode Start Register"
|
|
hgroup.byte 0x3A++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_DMPSEL,Direct Mode Peripheral Select Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.byte 0x3B++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMTRP,Direct Mode Transfer Protocol Register"
|
|
bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR"
|
|
bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol" "TX-and-RX in Legacy mode,,,TX-and-RX in Octal mode,,,,,TX-Only in Legacy mode,,TX-Only in Quad mode,TX-Only in Octal mode,?..."
|
|
elif ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)&&((per.l(ad:0xB0101000+0x120)&0x00000100)!=0x00000100)
|
|
group.byte 0x3B++0x0
|
|
line.byte 0x00 "DDRHSSPI0_DMTRP,Direct Mode Transfer Protocol Register"
|
|
bitfld.byte 0x00 5. " DDRM ,DDR mode" "SDR,DDR"
|
|
bitfld.byte 0x00 0.--3. " TRP ,Transfer protocol" "TX-and-RX in Legacy mode,,,,,,,,TX-Only in Legacy mode,,TX-Only in Quad mode,?..."
|
|
else
|
|
hgroup.byte 0x3B++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_DMTRP,Direct Mode Transfer Protocol Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)&&((per.b(ad:0xB0101000+0x34)&0x01)==0x01)
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "DDRHSSPI0_DMBCC,Byte Count Control Register"
|
|
else
|
|
hgroup.word 0x3C++0x1
|
|
hide.word 0x00 "DDRHSSPI0_DMBCC,Byte Count Control Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)&&((per.b(ad:0xB0101000+0x34)&0x01)==0x01)
|
|
group.word 0x3E++0x1
|
|
line.word 0x00 "DDRHSSPI0_DMBCS,Byte Count Status Register"
|
|
else
|
|
hgroup.word 0x3E++0x1
|
|
hide.word 0x00 "DDRHSSPI0_DMBCS,Byte Count Status Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DDRHSSPI0_DMFIFOSTATUS,Direct Mode FIFO Status Register"
|
|
bitfld.long 0x00 16. " SSACTIVE ,Slave select active" "Inactive,Active"
|
|
bitfld.long 0x00 8.--12. " TXFLEVEL ,Current fill level of TX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " RXFLEVEL ,Current fill level of RX-FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.long 0x40++0x3
|
|
hide.long 0x00 "DDRHSSPI0_DMFIFOSTATUS,Direct Mode FIFO Status Register"
|
|
endif
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "DDRHSSPI0_DMFIFOCFG,Direct Mode FIFO Configuration Register"
|
|
bitfld.long 0x00 20. " TXFLSH ,TX-FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 19. " RXFLSH ,RX-FIFO flush" "No effect,Flush"
|
|
bitfld.long 0x00 18. " TXCTRL ,TXCTRL bit to be written to TX-FIFO" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " FWIDTH ,FIFO width" "8-bit,16-bit,32-bit,"
|
|
bitfld.long 0x00 8.--12. " TXFTH ,TX-FIFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
bitfld.long 0x00 0.--4. " RXFTH ,RX-FIFO threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,?..."
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
wgroup.long 0x48++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO0,TX-FIFO Data Register 0"
|
|
wgroup.long 0x4C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO1,TX-FIFO Data Register 1"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO2,TX-FIFO Data Register 2"
|
|
wgroup.long 0x54++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO3,TX-FIFO Data Register 3"
|
|
wgroup.long 0x58++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO4,TX-FIFO Data Register 4"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO5,TX-FIFO Data Register 5"
|
|
wgroup.long 0x60++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO6,TX-FIFO Data Register 6"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO7,TX-FIFO Data Register 7"
|
|
wgroup.long 0x68++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO8,TX-FIFO Data Register 8"
|
|
wgroup.long 0x6C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO9,TX-FIFO Data Register 9"
|
|
wgroup.long 0x70++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO10,TX-FIFO Data Register 10"
|
|
wgroup.long 0x74++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO11,TX-FIFO Data Register 11"
|
|
wgroup.long 0x78++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO12,TX-FIFO Data Register 12"
|
|
wgroup.long 0x7C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO13,TX-FIFO Data Register 13"
|
|
wgroup.long 0x80++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO14,TX-FIFO Data Register 14"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO15,TX-FIFO Data Register 15"
|
|
wgroup.long 0x88++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO16,TX-FIFO Data Register 16"
|
|
wgroup.long 0x8C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO17,TX-FIFO Data Register 17"
|
|
wgroup.long 0x90++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO18,TX-FIFO Data Register 18"
|
|
wgroup.long 0x94++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO19,TX-FIFO Data Register 19"
|
|
wgroup.long 0x98++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO20,TX-FIFO Data Register 20"
|
|
wgroup.long 0x9C++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO21,TX-FIFO Data Register 21"
|
|
wgroup.long 0xA0++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO22,TX-FIFO Data Register 22"
|
|
wgroup.long 0xA4++0x3
|
|
line.long 0x00 "DDRHSSPI0_TXFIFO23,TX-FIFO Data Register 23"
|
|
else
|
|
hgroup.long 0x48++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO0,TX-FIFO Data Register 0"
|
|
hgroup.long 0x4C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO1,TX-FIFO Data Register 1"
|
|
hgroup.long 0x50++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO2,TX-FIFO Data Register 2"
|
|
hgroup.long 0x54++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO3,TX-FIFO Data Register 3"
|
|
hgroup.long 0x58++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO4,TX-FIFO Data Register 4"
|
|
hgroup.long 0x5C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO5,TX-FIFO Data Register 5"
|
|
hgroup.long 0x60++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO6,TX-FIFO Data Register 6"
|
|
hgroup.long 0x64++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO7,TX-FIFO Data Register 7"
|
|
hgroup.long 0x68++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO8,TX-FIFO Data Register 8"
|
|
hgroup.long 0x6C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO9,TX-FIFO Data Register 9"
|
|
hgroup.long 0x70++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO10,TX-FIFO Data Register 10"
|
|
hgroup.long 0x74++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO11,TX-FIFO Data Register 11"
|
|
hgroup.long 0x78++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO12,TX-FIFO Data Register 12"
|
|
hgroup.long 0x7C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO13,TX-FIFO Data Register 13"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO14,TX-FIFO Data Register 14"
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO15,TX-FIFO Data Register 15"
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO16,TX-FIFO Data Register 16"
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO17,TX-FIFO Data Register 17"
|
|
hgroup.long 0x90++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO18,TX-FIFO Data Register 18"
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO19,TX-FIFO Data Register 19"
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO20,TX-FIFO Data Register 20"
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO21,TX-FIFO Data Register 21"
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO22,TX-FIFO Data Register 22"
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_TXFIFO23,TX-FIFO Data Register 23"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x00)
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO0,RX-FIFO Data Register 0"
|
|
in
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO1,RX-FIFO Data Register 1"
|
|
in
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO2,RX-FIFO Data Register 2"
|
|
in
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO3,RX-FIFO Data Register 3"
|
|
in
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO4,RX-FIFO Data Register 4"
|
|
in
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO5,RX-FIFO Data Register 5"
|
|
in
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO6,RX-FIFO Data Register 6"
|
|
in
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO7,RX-FIFO Data Register 7"
|
|
in
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO8,RX-FIFO Data Register 8"
|
|
in
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO9,RX-FIFO Data Register 9"
|
|
in
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO10,RX-FIFO Data Register 10"
|
|
in
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO11,RX-FIFO Data Register 11"
|
|
in
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO12,RX-FIFO Data Register 12"
|
|
in
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO13,RX-FIFO Data Register 13"
|
|
in
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO14,RX-FIFO Data Register 14"
|
|
in
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO15,RX-FIFO Data Register 15"
|
|
in
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO16,RX-FIFO Data Register 16"
|
|
in
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO17,RX-FIFO Data Register 17"
|
|
in
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO18,RX-FIFO Data Register 18"
|
|
in
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO19,RX-FIFO Data Register 19"
|
|
in
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO20,RX-FIFO Data Register 20"
|
|
in
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO21,RX-FIFO Data Register 21"
|
|
in
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO22,RX-FIFO Data Register 22"
|
|
in
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO23,RX-FIFO Data Register 23"
|
|
in
|
|
else
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO0,RX-FIFO Data Register 0"
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO1,RX-FIFO Data Register 1"
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO2,RX-FIFO Data Register 2"
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO3,RX-FIFO Data Register 3"
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO4,RX-FIFO Data Register 4"
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO5,RX-FIFO Data Register 5"
|
|
hgroup.long 0xC0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO6,RX-FIFO Data Register 6"
|
|
hgroup.long 0xC4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO7,RX-FIFO Data Register 7"
|
|
hgroup.long 0xC8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO8,RX-FIFO Data Register 8"
|
|
hgroup.long 0xCC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO9,RX-FIFO Data Register 9"
|
|
hgroup.long 0xD0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO10,RX-FIFO Data Register 10"
|
|
hgroup.long 0xD4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO11,RX-FIFO Data Register 11"
|
|
hgroup.long 0xD8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO12,RX-FIFO Data Register 12"
|
|
hgroup.long 0xDC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO13,RX-FIFO Data Register 13"
|
|
hgroup.long 0xE0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO14,RX-FIFO Data Register 14"
|
|
hgroup.long 0xE4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO15,RX-FIFO Data Register 15"
|
|
hgroup.long 0xE8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO16,RX-FIFO Data Register 16"
|
|
hgroup.long 0xEC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO17,RX-FIFO Data Register 17"
|
|
hgroup.long 0xF0++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO18,RX-FIFO Data Register 18"
|
|
hgroup.long 0xF4++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO19,RX-FIFO Data Register 19"
|
|
hgroup.long 0xF8++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO20,RX-FIFO Data Register 20"
|
|
hgroup.long 0xFC++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO21,RX-FIFO Data Register 21"
|
|
hgroup.long 0x100++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO22,RX-FIFO Data Register 22"
|
|
hgroup.long 0x104++0x3
|
|
hide.long 0x00 "DDRHSSPI0_RXFIFO23,RX-FIFO Data Register 23"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC0,Read Command Sequencer Data/Control Register 0"
|
|
else
|
|
group.word 0x108++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC0,Read Command Sequencer Data/Control Register 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC1,Read Command Sequencer Data/Control Register 1"
|
|
else
|
|
group.word 0x10A++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC1,Read Command Sequencer Data/Control Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC2,Read Command Sequencer Data/Control Register 2"
|
|
else
|
|
group.word 0x10C++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC2,Read Command Sequencer Data/Control Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC3,Read Command Sequencer Data/Control Register 3"
|
|
else
|
|
group.word 0x10E++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC3,Read Command Sequencer Data/Control Register 3"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC4,Read Command Sequencer Data/Control Register 4"
|
|
else
|
|
group.word 0x110++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC4,Read Command Sequencer Data/Control Register 4"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC5,Read Command Sequencer Data/Control Register 5"
|
|
else
|
|
group.word 0x112++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC5,Read Command Sequencer Data/Control Register 5"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC6,Read Command Sequencer Data/Control Register 6"
|
|
else
|
|
group.word 0x114++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC6,Read Command Sequencer Data/Control Register 6"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC7,Read Command Sequencer Data/Control Register 7"
|
|
else
|
|
group.word 0x116++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC7,Read Command Sequencer Data/Control Register 7"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC8,Read Command Sequencer Data/Control Register 8"
|
|
else
|
|
group.word 0x118++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC8,Read Command Sequencer Data/Control Register 8"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC9,Read Command Sequencer Data/Control Register 9"
|
|
else
|
|
group.word 0x11A++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC9,Read Command Sequencer Data/Control Register 9"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC10,Read Command Sequencer Data/Control Register 10"
|
|
else
|
|
group.word 0x11C++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC10,Read Command Sequencer Data/Control Register 10"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC11,Read Command Sequencer Data/Control Register 11"
|
|
else
|
|
group.word 0x11E++0x1
|
|
line.word 0x00 "DDRHSSPI0_RDCSDC11,Read Command Sequencer Data/Control Register 11"
|
|
hexmask.word.byte 0x00 8.--15. 1. " RDCSDATA ,Command sequencer data/Control byte for memory-read transactions"
|
|
bitfld.word 0x00 0. " DEC ,Decode" "Normal,Decoded"
|
|
endif
|
|
else
|
|
hgroup.word 0x108++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC0,Read Command Sequencer Data/Control Register 0"
|
|
hgroup.word 0x10A++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC1,Read Command Sequencer Data/Control Register 1"
|
|
hgroup.word 0x10C++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC2,Read Command Sequencer Data/Control Register 2"
|
|
hgroup.word 0x10E++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC3,Read Command Sequencer Data/Control Register 3"
|
|
hgroup.word 0x110++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC4,Read Command Sequencer Data/Control Register 4"
|
|
hgroup.word 0x112++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC5,Read Command Sequencer Data/Control Register 5"
|
|
hgroup.word 0x114++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC6,Read Command Sequencer Data/Control Register 6"
|
|
hgroup.word 0x116++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC7,Read Command Sequencer Data/Control Register 7"
|
|
hgroup.word 0x118++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC8,Read Command Sequencer Data/Control Register 8"
|
|
hgroup.word 0x11A++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC9,Read Command Sequencer Data/Control Register 9"
|
|
hgroup.word 0x11C++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC10,Read Command Sequencer Data/Control Register 10"
|
|
hgroup.word 0x11E++0x1
|
|
hide.word 0x00 "DDRHSSPI0_RDCSDC11,Read Command Sequencer Data/Control Register 11"
|
|
endif
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "DDRHSSPI0_MID,Module ID Register"
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "DDRHSSPI0_CSPREFETCHADDR,Command Sequencer Prefetch Address Register"
|
|
in
|
|
else
|
|
hgroup.long 0x124++0x3
|
|
hide.long 0x00 "DDRHSSPI0_CSPREFETCHADDR,Command Sequencer Prefetch Address Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.byte 0x128++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x129++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12A++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12B++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12C++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12D++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12E++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x12F++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTCNT ,SDATA center clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x128++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT0,SDATA Center Clock Sample Point Register 0"
|
|
hgroup.byte 0x129++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT1,SDATA Center Clock Sample Point Register 1"
|
|
hgroup.byte 0x12A++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT2,SDATA Center Clock Sample Point Register 2"
|
|
hgroup.byte 0x12B++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT3,SDATA Center Clock Sample Point Register 3"
|
|
hgroup.byte 0x12C++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT4,SDATA Center Clock Sample Point Register 4"
|
|
hgroup.byte 0x12D++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT5,SDATA Center Clock Sample Point Register 5"
|
|
hgroup.byte 0x12E++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT6,SDATA Center Clock Sample Point Register 6"
|
|
hgroup.byte 0x12F++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTCNT7,SDATA Center Clock Sample Point Register 7"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.byte 0x130++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x131++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x132++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x133++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x134++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x135++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x136++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x137++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTLFT ,SDATA left clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x130++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT0,SDATA Left Clock Sample Point Register 0"
|
|
hgroup.byte 0x131++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT1,SDATA Left Clock Sample Point Register 1"
|
|
hgroup.byte 0x132++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT2,SDATA Left Clock Sample Point Register 2"
|
|
hgroup.byte 0x133++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT3,SDATA Left Clock Sample Point Register 3"
|
|
hgroup.byte 0x134++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT4,SDATA Left Clock Sample Point Register 4"
|
|
hgroup.byte 0x135++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT5,SDATA Left Clock Sample Point Register 5"
|
|
hgroup.byte 0x136++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT6,SDATA Left Clock Sample Point Register 6"
|
|
hgroup.byte 0x137++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTLFT7,SDATA Left Clock Sample Point Register 7"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.byte 0x138++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x139++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13A++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13B++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13C++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13D++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13E++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x13F++0x0
|
|
line.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7"
|
|
bitfld.byte 0x00 0.--5. " SDATASMPTRGH ,SDATA right clock sample point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.byte 0x138++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH0,SDATA Right Clock Sample Point Register 0"
|
|
hgroup.byte 0x139++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH1,SDATA Right Clock Sample Point Register 1"
|
|
hgroup.byte 0x13A++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH2,SDATA Right Clock Sample Point Register 2"
|
|
hgroup.byte 0x13B++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH3,SDATA Right Clock Sample Point Register 3"
|
|
hgroup.byte 0x13C++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH4,SDATA Right Clock Sample Point Register 4"
|
|
hgroup.byte 0x13D++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH5,SDATA Right Clock Sample Point Register 5"
|
|
hgroup.byte 0x13E++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH6,SDATA Right Clock Sample Point Register 6"
|
|
hgroup.byte 0x13F++0x0
|
|
hide.byte 0x00 "DDRHSSPI0_SDATASAMPLEPTRGH7,SDATA Right Clock Sample Point Register 7"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "DDRHSSPI0_DLP,Data Learning Pattern Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLP ,Data learning pattern"
|
|
else
|
|
hgroup.long 0x144++0x3
|
|
hide.long 0x00 "DDRHSSPI0_DLP,Data Learning Pattern Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "DDRHSSPI0_DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register"
|
|
bitfld.long 0x00 30. " DLPSMPLST7R ,Sampled data on the SDATA[7] port" "0,1"
|
|
bitfld.long 0x00 29. " DLPSMPLST7C ,Sampled data on the SDATA[7] port" "0,1"
|
|
bitfld.long 0x00 28. " DLPSMPLST7L ,Sampled data on the SDATA[7] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DLPSMPLST6R ,Sampled data on the SDATA[6] port" "0,1"
|
|
bitfld.long 0x00 25. " DLPSMPLST6C ,Sampled data on the SDATA[6] port" "0,1"
|
|
bitfld.long 0x00 24. " DLPSMPLST6L ,Sampled data on the SDATA[6] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLPSMPLST5R ,Sampled data on the SDATA[5] port" "0,1"
|
|
bitfld.long 0x00 21. " DLPSMPLST5C ,Sampled data on the SDATA[5] port" "0,1"
|
|
bitfld.long 0x00 20. " DLPSMPLST5L ,Sampled data on the SDATA[5] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DLPSMPLST4R ,Sampled data on the SDATA[4] port" "0,1"
|
|
bitfld.long 0x00 17. " DLPSMPLST4C ,Sampled data on the SDATA[4] port" "0,1"
|
|
bitfld.long 0x00 16. " DLPSMPLST4L ,Sampled data on the SDATA[4] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLPSMPLST3R ,Sampled data on the SDATA[3] port" "0,1"
|
|
bitfld.long 0x00 13. " DLPSMPLST3C ,Sampled data on the SDATA[3] port" "0,1"
|
|
bitfld.long 0x00 12. " DLPSMPLST3L ,Sampled data on the SDATA[3] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DLPSMPLST2R ,Sampled data on the SDATA[2] port" "0,1"
|
|
bitfld.long 0x00 9. " DLPSMPLST2C ,Sampled data on the SDATA[2] port" "0,1"
|
|
bitfld.long 0x00 8. " DLPSMPLST2L ,Sampled data on the SDATA[2] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DLPSMPLST1R ,Sampled data on the SDATA[1] port" "0,1"
|
|
bitfld.long 0x00 5. " DLPSMPLST1C ,Sampled data on the SDATA[1] port" "0,1"
|
|
bitfld.long 0x00 4. " DLPSMPLST1L ,Sampled data on the SDATA[1] port" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DLPSMPLST0R ,Sampled data on the SDATA[0] port" "0,1"
|
|
bitfld.long 0x00 1. " DLPSMPLST0C ,Sampled data on the SDATA[0] port" "0,1"
|
|
bitfld.long 0x00 0. " DLPSMPLST0L ,Sampled data on the SDATA[0] port" "0,1"
|
|
else
|
|
hgroup.long 0x148++0x3
|
|
hide.long 0x00 "DDRHSSPI0_DLPSAMPLESTATUS,Data Learning Pattern Sample Status Register"
|
|
endif
|
|
if ((per.l(ad:0xB0101000+0x120)&0x00000100)==0x00000100)
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSCFG,Command Sequencer Configuration Register"
|
|
bitfld.long 0x00 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DDRMODE ,DDR mode" "SDR,DDR"
|
|
bitfld.long 0x00 1.--2. " MBM ,Multi bit mode" ",,Quad protocol,Dual Quad protocol"
|
|
else
|
|
group.long 0x14C++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSCFG,Command Sequencer Configuration Register"
|
|
bitfld.long 0x00 23. " ITIMEREN ,Idle timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " MSEL ,Memory selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " SSEL3EN ,Slave select 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSEL2EN ,Slave select 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSEL1EN ,Slave select 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SSEL0EN ,Slave select 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DDRMODE ,DDR mode" "SDR,DDR"
|
|
bitfld.long 0x00 1.--2. " MBM ,Multi bit mode" ",,Quad protocol,"
|
|
endif
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSITIME,Command Sequencer Idle Time Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ITIME ,Idle time"
|
|
group.long 0x154++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSAEXT,Command Sequencer Address Extension Register"
|
|
hexmask.long.tbyte 0x00 13.--31. 1. " AEXT ,Address extension bits"
|
|
wgroup.long 0x158++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSPBUFFERCFG,Command Sequencer Pretech Buffer Configuration Register"
|
|
bitfld.long 0x00 19. " PBFLSH ,Prefetch buffer flush" "No effect,Flush"
|
|
if ((per.l(ad:0xB0101000+0x00)&0x20)==0x20)
|
|
group.long 0x15C++0x3
|
|
line.long 0x00 "DDRHSSPI0_CSPBUFFERSTATUS,Command Sequencer Prefetch Buffer Status Register"
|
|
bitfld.long 0x00 16. " SSACTIVE ,Slave select active" "Inactive,Active"
|
|
bitfld.long 0x00 0.--5. " PBLEVEL ,Current fill level of pretech buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
hgroup.long 0x15C++0x3
|
|
hide.long 0x00 "DDRHSSPI0_CSPBUFFERSTATUS,Command Sequencer Prefetch Buffer Status Register"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "EBI (External Bus Interface)"
|
|
base ad:0xB0100000
|
|
width 0x0B
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UNLOCK,Unlock Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LSTSR,Lock Status Register"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SFMR0,SRAM/FLASH Mode Control Register"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SFMR1,SRAM/FLASH Mode Control Register"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SFMR2,SRAM/FLASH Mode Control Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SFMR3,SRAM/FLASH Mode Control Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SFMR4,SRAM/FLASH Mode Control Register"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SFMR5,SRAM/FLASH Mode Control Register"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SFMR6,SRAM/FLASH Mode Control Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SFMR7,SRAM/FLASH Mode Control Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SFACCR0,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SFACCR1,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SFACCR2,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SFACCR3,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SFACCR4,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SFACCR5,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SFACCR6,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SFACCR7,SRAM/FLASH Access Configuration Register"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SFADDCR0,SRAM/FLASH Access Control Register"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SFADDCR1,SRAM/FLASH Access Control Register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SFADDCR2,SRAM/FLASH Access Control Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SFADDCR3,SRAM/FLASH Access Control Register"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SFADDCR4,SRAM/FLASH Access Control Register"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SFADDCR5,SRAM/FLASH Access Control Register"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SFADDCR6,SRAM/FLASH Access Control Register"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SFADDCR7,SRAM/FLASH Access Control Register"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ERRR,Error Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "SRCFG (System SRAM Module)"
|
|
base ad:0xB0108000
|
|
width 14.
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "SRCFG_CFG0,SRAM_IF Configuration Register 0"
|
|
bitfld.long 0x00 24.--25. " RDWAIT ,Read data wait state value" "0,1,2,3"
|
|
bitfld.long 0x00 16.--17. " WRWAIT ,Write data wait state value" "0,1,2,3"
|
|
bitfld.long 0x00 8. " LOCK_STATUS ,SRAM_IF lock status" "Unlocked,Locked"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " ERRECC ,ECC ERRBIT value"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "SRCFG_CFG1,SRAM_IF Configuration Register 1"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "SRCFG_CFG2,SRAM_IF Configuration Register 2"
|
|
bitfld.long 0x00 0. " BYPASSEN ,RDB bypass enable" "Disabled,Enabled"
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "SRCFG_KEY,SRAM_IF Unlock/Lock Key Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SRCFG_ERRFLG,SRAM_IF Error Flag Register"
|
|
bitfld.long 0x00 8. " SECCLR ,Single-bit error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " SECFLG ,Single-bit error detection flag" "Not detected,Detected"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SRCFG_INTE,SRAM_IF Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " SEC_INT_EN ,Single-bit error interrupt enable bit" "No interrupt,Interrupt"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "SRCFG_ECCE,SRAM_IF ECC Enable Register"
|
|
bitfld.long 0x00 0. " ECCEN ,ECCEN value" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "SRCFG_ERRADR,SRAM_IF Error Address Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "SRCFG_MID,SRAM_IF Module Identification Register"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "ADC12B (12-bit A/D converter)"
|
|
tree "Analog Input Control Register"
|
|
base ad:0xB4848000
|
|
width 10.
|
|
wgroup.long 0x800++0x03
|
|
line.long 0x00 "KEYCDR,Key Code Register"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "ADER0,Analog Input Control Register 0"
|
|
bitfld.long 0x00 31. " ADE_[31] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Analog input enable bit" "Disabled,Enabled"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "ADER1,Analog Input Control Register 1"
|
|
bitfld.long 0x00 31. " ADE_[63] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [62] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [58] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [54] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [53] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [49] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [45] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [44] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Analog input enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Analog input enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Analog input enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "A/D Activation Compare Register"
|
|
base ad:0xB4848000
|
|
width 12.
|
|
wgroup.byte 0x04++0x00
|
|
line.byte 0x00 "ADTSS0,A/D Software Activation Register 0"
|
|
bitfld.byte 0x00 0. " START ,A/D conversion activation bit" "Not activate,Activate"
|
|
wgroup.byte 0x404++0x00
|
|
line.byte 0x00 "ADTSS1,A/D Software Activation Register 1"
|
|
bitfld.byte 0x00 0. " START ,A/D conversion activation bit" "Not activate,Activate"
|
|
sif cpuis("S6J311?JAA")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADTSE0,A/D Software Activation Channel Selection Register 0"
|
|
bitfld.long 0x00 31. " ADT_[31] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
elif cpuis("S6J311?HAA")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADTSE0,A/D Software Activation Channel Selection Register 0"
|
|
bitfld.long 0x00 31. " ADT_[31] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADTSE0,A/D Software Activation Channel Selection Register 0"
|
|
bitfld.long 0x00 31. " ADT_[31] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "ADTSE1_00,A/D Software Activation Channel Selection Register 1"
|
|
bitfld.long 0x00 31. " ADT_[63] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [62] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [58] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [54] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [53] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [49] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [45] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [44] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
elif cpuis("S6J311?HAA")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "ADTSE1_00,A/D Software Activation Channel Selection Register 1"
|
|
bitfld.long 0x00 30. " ADT_[62] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [59] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [55] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [54] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [53] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [51] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [50] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [49] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [47] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [46] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [45] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [44] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [43] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [42] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [39] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [38] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [35] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [34] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "ADTSE1_00,A/D Software Activation Channel Selection Register 1"
|
|
bitfld.long 0x00 30. " ADT_[62] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [59] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [55] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [51] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [49] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [47] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Software activation channel selection bit" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
wgroup.word 0xC++0x01
|
|
line.word 0x00 "ADCOMPB0,Compare Buffer Register 0"
|
|
wgroup.word 0xE++0x01
|
|
line.word 0x00 "ADCOMPB1,Compare Buffer Register 1"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB2,Compare Buffer Register 2"
|
|
wgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
wgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
wgroup.word 0x18++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
wgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
wgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMPB8,Compare Buffer Register 8"
|
|
wgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMPB9,Compare Buffer Register 9"
|
|
wgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCOMPB10,Compare Buffer Register 10"
|
|
wgroup.word 0x22++0x01
|
|
line.word 0x00 "ADCOMPB11,Compare Buffer Register 11"
|
|
wgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCOMPB12,Compare Buffer Register 12"
|
|
wgroup.word 0x26++0x01
|
|
line.word 0x00 "ADCOMPB13,Compare Buffer Register 13"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCOMPB14,Compare Buffer Register 14"
|
|
wgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMPB15,Compare Buffer Register 15"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMPB16,Compare Buffer Register 16"
|
|
wgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMPB17,Compare Buffer Register 17"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCOMPB18,Compare Buffer Register 18"
|
|
wgroup.word 0x32++0x01
|
|
line.word 0x00 "ADCOMPB19,Compare Buffer Register 19"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCOMPB20,Compare Buffer Register 20"
|
|
wgroup.word 0x36++0x01
|
|
line.word 0x00 "ADCOMPB21,Compare Buffer Register 21"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCOMPB22,Compare Buffer Register 22"
|
|
wgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMPB23,Compare Buffer Register 23"
|
|
wgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMPB24,Compare Buffer Register 24"
|
|
wgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMPB25,Compare Buffer Register 25"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCOMPB26,Compare Buffer Register 26"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "ADCOMPB27,Compare Buffer Register 27"
|
|
wgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCOMPB28,Compare Buffer Register 28"
|
|
wgroup.word 0x46++0x01
|
|
line.word 0x00 "ADCOMPB29,Compare Buffer Register 29"
|
|
wgroup.word 0x48++0x01
|
|
line.word 0x00 "ADCOMPB30,Compare Buffer Register 30"
|
|
wgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADCOMPB31,Compare Buffer Register 31"
|
|
elif cpuis("S6J312?HAA")
|
|
wgroup.word 0xC++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
wgroup.word 0xE++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
wgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
wgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB8,Compare Buffer Register 8"
|
|
wgroup.word 0x18++0x01
|
|
line.word 0x00 "ADCOMPB9,Compare Buffer Register 9"
|
|
wgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMPB10,Compare Buffer Register 10"
|
|
wgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMPB11,Compare Buffer Register 11"
|
|
wgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMPB12,Compare Buffer Register 12"
|
|
wgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCOMPB13,Compare Buffer Register 13"
|
|
wgroup.word 0x22++0x01
|
|
line.word 0x00 "ADCOMPB14,Compare Buffer Register 14"
|
|
wgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCOMPB15,Compare Buffer Register 15"
|
|
wgroup.word 0x26++0x01
|
|
line.word 0x00 "ADCOMPB16,Compare Buffer Register 16"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCOMPB17,Compare Buffer Register 17"
|
|
wgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMPB18,Compare Buffer Register 18"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMPB19,Compare Buffer Register 19"
|
|
wgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMPB20,Compare Buffer Register 20"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCOMPB21,Compare Buffer Register 21"
|
|
wgroup.word 0x32++0x01
|
|
line.word 0x00 "ADCOMPB22,Compare Buffer Register 22"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCOMPB23,Compare Buffer Register 23"
|
|
wgroup.word 0x36++0x01
|
|
line.word 0x00 "ADCOMPB24,Compare Buffer Register 24"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCOMPB25,Compare Buffer Register 25"
|
|
wgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMPB26,Compare Buffer Register 26"
|
|
wgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMPB27,Compare Buffer Register 27"
|
|
wgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMPB28,Compare Buffer Register 28"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCOMPB29,Compare Buffer Register 29"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "ADCOMPB30,Compare Buffer Register 30"
|
|
wgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCOMPB31,Compare Buffer Register 31"
|
|
endif
|
|
wgroup.word 0x40C++0x01
|
|
line.word 0x00 "ADCOMPB32,Compare Buffer Register 32"
|
|
wgroup.word 0x40E++0x01
|
|
line.word 0x00 "ADCOMPB33,Compare Buffer Register 33"
|
|
wgroup.word 0x410++0x01
|
|
line.word 0x00 "ADCOMPB34,Compare Buffer Register 34"
|
|
wgroup.word 0x412++0x01
|
|
line.word 0x00 "ADCOMPB35,Compare Buffer Register 35"
|
|
wgroup.word 0x414++0x01
|
|
line.word 0x00 "ADCOMPB36,Compare Buffer Register 36"
|
|
wgroup.word 0x416++0x01
|
|
line.word 0x00 "ADCOMPB37,Compare Buffer Register 37"
|
|
wgroup.word 0x418++0x01
|
|
line.word 0x00 "ADCOMPB38,Compare Buffer Register 38"
|
|
wgroup.word 0x41A++0x01
|
|
line.word 0x00 "ADCOMPB39,Compare Buffer Register 39"
|
|
wgroup.word 0x41C++0x01
|
|
line.word 0x00 "ADCOMPB40,Compare Buffer Register 40"
|
|
wgroup.word 0x41E++0x01
|
|
line.word 0x00 "ADCOMPB41,Compare Buffer Register 41"
|
|
wgroup.word 0x420++0x01
|
|
line.word 0x00 "ADCOMPB42,Compare Buffer Register 42"
|
|
wgroup.word 0x422++0x01
|
|
line.word 0x00 "ADCOMPB43,Compare Buffer Register 43"
|
|
wgroup.word 0x424++0x01
|
|
line.word 0x00 "ADCOMPB44,Compare Buffer Register 44"
|
|
wgroup.word 0x426++0x01
|
|
line.word 0x00 "ADCOMPB45,Compare Buffer Register 45"
|
|
wgroup.word 0x428++0x01
|
|
line.word 0x00 "ADCOMPB46,Compare Buffer Register 46"
|
|
wgroup.word 0x42A++0x01
|
|
line.word 0x00 "ADCOMPB47,Compare Buffer Register 47"
|
|
wgroup.word 0x42C++0x01
|
|
line.word 0x00 "ADCOMPB48,Compare Buffer Register 48"
|
|
wgroup.word 0x42E++0x01
|
|
line.word 0x00 "ADCOMPB49,Compare Buffer Register 49"
|
|
wgroup.word 0x430++0x01
|
|
line.word 0x00 "ADCOMPB50,Compare Buffer Register 50"
|
|
wgroup.word 0x432++0x01
|
|
line.word 0x00 "ADCOMPB51,Compare Buffer Register 51"
|
|
wgroup.word 0x434++0x01
|
|
line.word 0x00 "ADCOMPB52,Compare Buffer Register 52"
|
|
wgroup.word 0x436++0x01
|
|
line.word 0x00 "ADCOMPB53,Compare Buffer Register 53"
|
|
wgroup.word 0x438++0x01
|
|
line.word 0x00 "ADCOMPB54,Compare Buffer Register 54"
|
|
wgroup.word 0x43A++0x01
|
|
line.word 0x00 "ADCOMPB55,Compare Buffer Register 55"
|
|
wgroup.word 0x43C++0x01
|
|
line.word 0x00 "ADCOMPB56,Compare Buffer Register 56"
|
|
wgroup.word 0x43E++0x01
|
|
line.word 0x00 "ADCOMPB57,Compare Buffer Register 57"
|
|
wgroup.word 0x440++0x01
|
|
line.word 0x00 "ADCOMPB58,Compare Buffer Register 58"
|
|
wgroup.word 0x442++0x01
|
|
line.word 0x00 "ADCOMPB59,Compare Buffer Register 59"
|
|
wgroup.word 0x444++0x01
|
|
line.word 0x00 "ADCOMPB60,Compare Buffer Register 60"
|
|
wgroup.word 0x446++0x01
|
|
line.word 0x00 "ADCOMPB61,Compare Buffer Register 61"
|
|
wgroup.word 0x448++0x01
|
|
line.word 0x00 "ADCOMPB62,Compare Buffer Register 62"
|
|
wgroup.word 0x44A++0x01
|
|
line.word 0x00 "ADCOMPB63,Compare Buffer Register 63"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.word 0xC++0x01
|
|
line.word 0x00 "ADCOMP0,Compare Register 0"
|
|
rgroup.word 0xE++0x01
|
|
line.word 0x00 "ADCOMP1,Compare Register 1"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMP2,Compare Register 2"
|
|
rgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMP3,Compare Register 3"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMP4,Compare Register 4"
|
|
rgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMP5,Compare Register 5"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADCOMP6,Compare Register 6"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMP7,Compare Register 7"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMP8,Compare Register 8"
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMP9,Compare Register 9"
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCOMP10,Compare Register 10"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADCOMP11,Compare Register 11"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCOMP12,Compare Register 12"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADCOMP13,Compare Register 13"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCOMP14,Compare Register 14"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMP15,Compare Register 15"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMP16,Compare Register 16"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMP17,Compare Register 17"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCOMP18,Compare Register 18"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADCOMP19,Compare Register 19"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCOMP20,Compare Register 20"
|
|
rgroup.word 0x36++0x01
|
|
line.word 0x00 "ADCOMP21,Compare Register 21"
|
|
rgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCOMP22,Compare Register 22"
|
|
rgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMP23,Compare Register 23"
|
|
rgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMP24,Compare Register 24"
|
|
rgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMP25,Compare Register 25"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCOMP26,Compare Register 26"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADCOMP27,Compare Register 27"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCOMP28,Compare Register 28"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADCOMP29,Compare Register 29"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADCOMP30,Compare Register 30"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADCOMP31,Compare Register 31"
|
|
elif cpuis("S6J312?HAA")
|
|
wgroup.word 0xC++0x01
|
|
line.word 0x00 "ADCOMPB3,Compare Buffer Register 3"
|
|
wgroup.word 0xE++0x01
|
|
line.word 0x00 "ADCOMPB4,Compare Buffer Register 4"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "ADCOMPB5,Compare Buffer Register 5"
|
|
wgroup.word 0x12++0x01
|
|
line.word 0x00 "ADCOMPB6,Compare Buffer Register 6"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "ADCOMPB7,Compare Buffer Register 7"
|
|
wgroup.word 0x16++0x01
|
|
line.word 0x00 "ADCOMPB8,Compare Buffer Register 8"
|
|
wgroup.word 0x18++0x01
|
|
line.word 0x00 "ADCOMPB9,Compare Buffer Register 9"
|
|
wgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADCOMPB10,Compare Buffer Register 10"
|
|
wgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADCOMPB11,Compare Buffer Register 11"
|
|
wgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADCOMPB12,Compare Buffer Register 12"
|
|
wgroup.word 0x20++0x01
|
|
line.word 0x00 "ADCOMPB13,Compare Buffer Register 13"
|
|
wgroup.word 0x22++0x01
|
|
line.word 0x00 "ADCOMPB14,Compare Buffer Register 14"
|
|
wgroup.word 0x24++0x01
|
|
line.word 0x00 "ADCOMPB15,Compare Buffer Register 15"
|
|
wgroup.word 0x26++0x01
|
|
line.word 0x00 "ADCOMPB16,Compare Buffer Register 16"
|
|
wgroup.word 0x28++0x01
|
|
line.word 0x00 "ADCOMPB17,Compare Buffer Register 17"
|
|
wgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADCOMPB18,Compare Buffer Register 18"
|
|
wgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADCOMPB19,Compare Buffer Register 19"
|
|
wgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADCOMPB20,Compare Buffer Register 20"
|
|
wgroup.word 0x30++0x01
|
|
line.word 0x00 "ADCOMPB21,Compare Buffer Register 21"
|
|
wgroup.word 0x32++0x01
|
|
line.word 0x00 "ADCOMPB22,Compare Buffer Register 22"
|
|
wgroup.word 0x34++0x01
|
|
line.word 0x00 "ADCOMPB23,Compare Buffer Register 23"
|
|
wgroup.word 0x36++0x01
|
|
line.word 0x00 "ADCOMPB24,Compare Buffer Register 24"
|
|
wgroup.word 0x38++0x01
|
|
line.word 0x00 "ADCOMPB25,Compare Buffer Register 25"
|
|
wgroup.word 0x3A++0x01
|
|
line.word 0x00 "ADCOMPB26,Compare Buffer Register 26"
|
|
wgroup.word 0x3C++0x01
|
|
line.word 0x00 "ADCOMPB27,Compare Buffer Register 27"
|
|
wgroup.word 0x3E++0x01
|
|
line.word 0x00 "ADCOMPB28,Compare Buffer Register 28"
|
|
wgroup.word 0x40++0x01
|
|
line.word 0x00 "ADCOMPB29,Compare Buffer Register 29"
|
|
wgroup.word 0x42++0x01
|
|
line.word 0x00 "ADCOMPB30,Compare Buffer Register 30"
|
|
wgroup.word 0x44++0x01
|
|
line.word 0x00 "ADCOMPB31,Compare Buffer Register 31"
|
|
endif
|
|
rgroup.word 0x40C++0x01
|
|
line.word 0x00 "ADCOMP32,Compare Register 32"
|
|
rgroup.word 0x40E++0x01
|
|
line.word 0x00 "ADCOMP33,Compare Register 33"
|
|
rgroup.word 0x410++0x01
|
|
line.word 0x00 "ADCOMP34,Compare Register 34"
|
|
rgroup.word 0x412++0x01
|
|
line.word 0x00 "ADCOMP35,Compare Register 35"
|
|
rgroup.word 0x414++0x01
|
|
line.word 0x00 "ADCOMP36,Compare Register 36"
|
|
rgroup.word 0x416++0x01
|
|
line.word 0x00 "ADCOMP37,Compare Register 37"
|
|
rgroup.word 0x418++0x01
|
|
line.word 0x00 "ADCOMP38,Compare Register 38"
|
|
rgroup.word 0x41A++0x01
|
|
line.word 0x00 "ADCOMP39,Compare Register 39"
|
|
rgroup.word 0x41C++0x01
|
|
line.word 0x00 "ADCOMP40,Compare Register 40"
|
|
rgroup.word 0x41E++0x01
|
|
line.word 0x00 "ADCOMP41,Compare Register 41"
|
|
rgroup.word 0x420++0x01
|
|
line.word 0x00 "ADCOMP42,Compare Register 42"
|
|
rgroup.word 0x422++0x01
|
|
line.word 0x00 "ADCOMP43,Compare Register 43"
|
|
rgroup.word 0x424++0x01
|
|
line.word 0x00 "ADCOMP44,Compare Register 44"
|
|
rgroup.word 0x426++0x01
|
|
line.word 0x00 "ADCOMP45,Compare Register 45"
|
|
rgroup.word 0x428++0x01
|
|
line.word 0x00 "ADCOMP46,Compare Register 46"
|
|
rgroup.word 0x42A++0x01
|
|
line.word 0x00 "ADCOMP47,Compare Register 47"
|
|
rgroup.word 0x42C++0x01
|
|
line.word 0x00 "ADCOMP48,Compare Register 48"
|
|
rgroup.word 0x42E++0x01
|
|
line.word 0x00 "ADCOMP49,Compare Register 49"
|
|
rgroup.word 0x430++0x01
|
|
line.word 0x00 "ADCOMP50,Compare Register 50"
|
|
rgroup.word 0x432++0x01
|
|
line.word 0x00 "ADCOMP51,Compare Register 51"
|
|
rgroup.word 0x434++0x01
|
|
line.word 0x00 "ADCOMP52,Compare Register 52"
|
|
rgroup.word 0x436++0x01
|
|
line.word 0x00 "ADCOMP53,Compare Register 53"
|
|
rgroup.word 0x438++0x01
|
|
line.word 0x00 "ADCOMP54,Compare Register 54"
|
|
rgroup.word 0x43A++0x01
|
|
line.word 0x00 "ADCOMP55,Compare Register 55"
|
|
rgroup.word 0x43C++0x01
|
|
line.word 0x00 "ADCOMP56,Compare Register 56"
|
|
rgroup.word 0x43E++0x01
|
|
line.word 0x00 "ADCOMP57,Compare Register 57"
|
|
rgroup.word 0x440++0x01
|
|
line.word 0x00 "ADCOMP58,Compare Register 58"
|
|
rgroup.word 0x442++0x01
|
|
line.word 0x00 "ADCOMP59,Compare Register 59"
|
|
rgroup.word 0x444++0x01
|
|
line.word 0x00 "ADCOMP60,Compare Register 60"
|
|
rgroup.word 0x446++0x01
|
|
line.word 0x00 "ADCOMP61,Compare Register 61"
|
|
rgroup.word 0x448++0x01
|
|
line.word 0x00 "ADCOMP62,Compare Register 62"
|
|
rgroup.word 0x44A++0x01
|
|
line.word 0x00 "ADCOMP63,Compare Register 63"
|
|
if ((d.b(ad:0xB4848000+0x4C)&0x100)==0x00)
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "ADTCS0,A/D Activation Trigger Control Status Register 0"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x4C++0x01
|
|
line.word 0x00 "ADTCS0,A/D Activation Trigger Control Status Register 0"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x4E)&0x100)==0x00)
|
|
group.word 0x4E++0x01
|
|
line.word 0x00 "ADTCS1,A/D Activation Trigger Control Status Register 1"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x4E++0x01
|
|
line.word 0x00 "ADTCS1,A/D Activation Trigger Control Status Register 1"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x50)&0x100)==0x00)
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "ADTCS2,A/D Activation Trigger Control Status Register 2"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x50++0x01
|
|
line.word 0x00 "ADTCS2,A/D Activation Trigger Control Status Register 2"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x52)&0x100)==0x00)
|
|
group.word 0x52++0x01
|
|
line.word 0x00 "ADTCS3,A/D Activation Trigger Control Status Register 3"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x52++0x01
|
|
line.word 0x00 "ADTCS3,A/D Activation Trigger Control Status Register 3"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x54)&0x100)==0x00)
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "ADTCS4,A/D Activation Trigger Control Status Register 4"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x54++0x01
|
|
line.word 0x00 "ADTCS4,A/D Activation Trigger Control Status Register 4"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x56)&0x100)==0x00)
|
|
group.word 0x56++0x01
|
|
line.word 0x00 "ADTCS5,A/D Activation Trigger Control Status Register 5"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x56++0x01
|
|
line.word 0x00 "ADTCS5,A/D Activation Trigger Control Status Register 5"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x58)&0x100)==0x00)
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "ADTCS6,A/D Activation Trigger Control Status Register 6"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x58++0x01
|
|
line.word 0x00 "ADTCS6,A/D Activation Trigger Control Status Register 6"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x5A)&0x100)==0x00)
|
|
group.word 0x5A++0x01
|
|
line.word 0x00 "ADTCS7,A/D Activation Trigger Control Status Register 7"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x5A++0x01
|
|
line.word 0x00 "ADTCS7,A/D Activation Trigger Control Status Register 7"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x5C)&0x100)==0x00)
|
|
group.word 0x5C++0x01
|
|
line.word 0x00 "ADTCS8,A/D Activation Trigger Control Status Register 8"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x5C++0x01
|
|
line.word 0x00 "ADTCS8,A/D Activation Trigger Control Status Register 8"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x5E)&0x100)==0x00)
|
|
group.word 0x5E++0x01
|
|
line.word 0x00 "ADTCS9,A/D Activation Trigger Control Status Register 9"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x5E++0x01
|
|
line.word 0x00 "ADTCS9,A/D Activation Trigger Control Status Register 9"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x60)&0x100)==0x00)
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "ADTCS10,A/D Activation Trigger Control Status Register 10"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x60++0x01
|
|
line.word 0x00 "ADTCS10,A/D Activation Trigger Control Status Register 10"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x62)&0x100)==0x00)
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "ADTCS11,A/D Activation Trigger Control Status Register 11"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x62++0x01
|
|
line.word 0x00 "ADTCS11,A/D Activation Trigger Control Status Register 11"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x64)&0x100)==0x00)
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "ADTCS12,A/D Activation Trigger Control Status Register 12"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x64++0x01
|
|
line.word 0x00 "ADTCS12,A/D Activation Trigger Control Status Register 12"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x66)&0x100)==0x00)
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "ADTCS13,A/D Activation Trigger Control Status Register 13"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x66++0x01
|
|
line.word 0x00 "ADTCS13,A/D Activation Trigger Control Status Register 13"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x68)&0x100)==0x00)
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "ADTCS14,A/D Activation Trigger Control Status Register 14"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x68++0x01
|
|
line.word 0x00 "ADTCS14,A/D Activation Trigger Control Status Register 14"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x6A)&0x100)==0x00)
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "ADTCS15,A/D Activation Trigger Control Status Register 15"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x6A++0x01
|
|
line.word 0x00 "ADTCS15,A/D Activation Trigger Control Status Register 15"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x6C)&0x100)==0x00)
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "ADTCS16,A/D Activation Trigger Control Status Register 16"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x6C++0x01
|
|
line.word 0x00 "ADTCS16,A/D Activation Trigger Control Status Register 16"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x6E)&0x100)==0x00)
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "ADTCS17,A/D Activation Trigger Control Status Register 17"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x6E++0x01
|
|
line.word 0x00 "ADTCS17,A/D Activation Trigger Control Status Register 17"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x70)&0x100)==0x00)
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "ADTCS18,A/D Activation Trigger Control Status Register 18"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x70++0x01
|
|
line.word 0x00 "ADTCS18,A/D Activation Trigger Control Status Register 18"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x72)&0x100)==0x00)
|
|
group.word 0x72++0x01
|
|
line.word 0x00 "ADTCS19,A/D Activation Trigger Control Status Register 19"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x72++0x01
|
|
line.word 0x00 "ADTCS19,A/D Activation Trigger Control Status Register 19"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x74)&0x100)==0x00)
|
|
group.word 0x74++0x01
|
|
line.word 0x00 "ADTCS20,A/D Activation Trigger Control Status Register 20"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x74++0x01
|
|
line.word 0x00 "ADTCS20,A/D Activation Trigger Control Status Register 20"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x76)&0x100)==0x00)
|
|
group.word 0x76++0x01
|
|
line.word 0x00 "ADTCS21,A/D Activation Trigger Control Status Register 21"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x76++0x01
|
|
line.word 0x00 "ADTCS21,A/D Activation Trigger Control Status Register 21"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x78)&0x100)==0x00)
|
|
group.word 0x78++0x01
|
|
line.word 0x00 "ADTCS22,A/D Activation Trigger Control Status Register 22"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x78++0x01
|
|
line.word 0x00 "ADTCS22,A/D Activation Trigger Control Status Register 22"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x7A)&0x100)==0x00)
|
|
group.word 0x7A++0x01
|
|
line.word 0x00 "ADTCS23,A/D Activation Trigger Control Status Register 23"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x7A++0x01
|
|
line.word 0x00 "ADTCS23,A/D Activation Trigger Control Status Register 23"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x7C)&0x100)==0x00)
|
|
group.word 0x7C++0x01
|
|
line.word 0x00 "ADTCS24,A/D Activation Trigger Control Status Register 24"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x7C++0x01
|
|
line.word 0x00 "ADTCS24,A/D Activation Trigger Control Status Register 24"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x7E)&0x100)==0x00)
|
|
group.word 0x7E++0x01
|
|
line.word 0x00 "ADTCS25,A/D Activation Trigger Control Status Register 25"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x7E++0x01
|
|
line.word 0x00 "ADTCS25,A/D Activation Trigger Control Status Register 25"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x80)&0x100)==0x00)
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADTCS26,A/D Activation Trigger Control Status Register 26"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x80++0x01
|
|
line.word 0x00 "ADTCS26,A/D Activation Trigger Control Status Register 26"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x82)&0x100)==0x00)
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "ADTCS27,A/D Activation Trigger Control Status Register 27"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x82++0x01
|
|
line.word 0x00 "ADTCS27,A/D Activation Trigger Control Status Register 27"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x84)&0x100)==0x00)
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "ADTCS28,A/D Activation Trigger Control Status Register 28"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x84++0x01
|
|
line.word 0x00 "ADTCS28,A/D Activation Trigger Control Status Register 28"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x86)&0x100)==0x00)
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "ADTCS29,A/D Activation Trigger Control Status Register 29"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x86++0x01
|
|
line.word 0x00 "ADTCS29,A/D Activation Trigger Control Status Register 29"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x88)&0x100)==0x00)
|
|
group.word 0x88++0x01
|
|
line.word 0x00 "ADTCS30,A/D Activation Trigger Control Status Register 30"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x88++0x01
|
|
line.word 0x00 "ADTCS30,A/D Activation Trigger Control Status Register 30"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x8A)&0x100)==0x00)
|
|
group.word 0x8A++0x01
|
|
line.word 0x00 "ADTCS31,A/D Activation Trigger Control Status Register 31"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x8A++0x01
|
|
line.word 0x00 "ADTCS31,A/D Activation Trigger Control Status Register 31"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
if ((d.b(ad:0xB4848000+0x44C)&0x100)==0x00)
|
|
group.word 0x44C++0x01
|
|
line.word 0x00 "ADTCS32,A/D Activation Trigger Control Status Register 32"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x44C++0x01
|
|
line.word 0x00 "ADTCS32,A/D Activation Trigger Control Status Register 32"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x44E)&0x100)==0x00)
|
|
group.word 0x44E++0x01
|
|
line.word 0x00 "ADTCS33,A/D Activation Trigger Control Status Register 33"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x44E++0x01
|
|
line.word 0x00 "ADTCS33,A/D Activation Trigger Control Status Register 33"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x450)&0x100)==0x00)
|
|
group.word 0x450++0x01
|
|
line.word 0x00 "ADTCS34,A/D Activation Trigger Control Status Register 34"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x450++0x01
|
|
line.word 0x00 "ADTCS34,A/D Activation Trigger Control Status Register 34"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x452)&0x100)==0x00)
|
|
group.word 0x452++0x01
|
|
line.word 0x00 "ADTCS35,A/D Activation Trigger Control Status Register 35"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x452++0x01
|
|
line.word 0x00 "ADTCS35,A/D Activation Trigger Control Status Register 35"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x454)&0x100)==0x00)
|
|
group.word 0x454++0x01
|
|
line.word 0x00 "ADTCS36,A/D Activation Trigger Control Status Register 36"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x454++0x01
|
|
line.word 0x00 "ADTCS36,A/D Activation Trigger Control Status Register 36"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x456)&0x100)==0x00)
|
|
group.word 0x456++0x01
|
|
line.word 0x00 "ADTCS37,A/D Activation Trigger Control Status Register 37"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x456++0x01
|
|
line.word 0x00 "ADTCS37,A/D Activation Trigger Control Status Register 37"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x458)&0x100)==0x00)
|
|
group.word 0x458++0x01
|
|
line.word 0x00 "ADTCS38,A/D Activation Trigger Control Status Register 38"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x458++0x01
|
|
line.word 0x00 "ADTCS38,A/D Activation Trigger Control Status Register 38"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45A)&0x100)==0x00)
|
|
group.word 0x45A++0x01
|
|
line.word 0x00 "ADTCS39,A/D Activation Trigger Control Status Register 39"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45A++0x01
|
|
line.word 0x00 "ADTCS39,A/D Activation Trigger Control Status Register 39"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45C)&0x100)==0x00)
|
|
group.word 0x45C++0x01
|
|
line.word 0x00 "ADTCS40,A/D Activation Trigger Control Status Register 40"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45C++0x01
|
|
line.word 0x00 "ADTCS40,A/D Activation Trigger Control Status Register 40"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45E)&0x100)==0x00)
|
|
group.word 0x45E++0x01
|
|
line.word 0x00 "ADTCS41,A/D Activation Trigger Control Status Register 41"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45E++0x01
|
|
line.word 0x00 "ADTCS41,A/D Activation Trigger Control Status Register 41"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x460)&0x100)==0x00)
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "ADTCS42,A/D Activation Trigger Control Status Register 42"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x460++0x01
|
|
line.word 0x00 "ADTCS42,A/D Activation Trigger Control Status Register 42"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x462)&0x100)==0x00)
|
|
group.word 0x462++0x01
|
|
line.word 0x00 "ADTCS43,A/D Activation Trigger Control Status Register 43"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x462++0x01
|
|
line.word 0x00 "ADTCS43,A/D Activation Trigger Control Status Register 43"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x464)&0x100)==0x00)
|
|
group.word 0x464++0x01
|
|
line.word 0x00 "ADTCS44,A/D Activation Trigger Control Status Register 44"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x464++0x01
|
|
line.word 0x00 "ADTCS44,A/D Activation Trigger Control Status Register 44"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x466)&0x100)==0x00)
|
|
group.word 0x466++0x01
|
|
line.word 0x00 "ADTCS45,A/D Activation Trigger Control Status Register 45"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x466++0x01
|
|
line.word 0x00 "ADTCS45,A/D Activation Trigger Control Status Register 45"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x468)&0x100)==0x00)
|
|
group.word 0x468++0x01
|
|
line.word 0x00 "ADTCS46,A/D Activation Trigger Control Status Register 46"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x468++0x01
|
|
line.word 0x00 "ADTCS46,A/D Activation Trigger Control Status Register 46"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46A)&0x100)==0x00)
|
|
group.word 0x46A++0x01
|
|
line.word 0x00 "ADTCS47,A/D Activation Trigger Control Status Register 47"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46A++0x01
|
|
line.word 0x00 "ADTCS47,A/D Activation Trigger Control Status Register 47"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46C)&0x100)==0x00)
|
|
group.word 0x46C++0x01
|
|
line.word 0x00 "ADTCS48,A/D Activation Trigger Control Status Register 48"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46C++0x01
|
|
line.word 0x00 "ADTCS48,A/D Activation Trigger Control Status Register 48"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46E)&0x100)==0x00)
|
|
group.word 0x46E++0x01
|
|
line.word 0x00 "ADTCS49,A/D Activation Trigger Control Status Register 49"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46E++0x01
|
|
line.word 0x00 "ADTCS49,A/D Activation Trigger Control Status Register 49"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x470)&0x100)==0x00)
|
|
group.word 0x470++0x01
|
|
line.word 0x00 "ADTCS50,A/D Activation Trigger Control Status Register 50"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x470++0x01
|
|
line.word 0x00 "ADTCS50,A/D Activation Trigger Control Status Register 50"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x472)&0x100)==0x00)
|
|
group.word 0x472++0x01
|
|
line.word 0x00 "ADTCS51,A/D Activation Trigger Control Status Register 51"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x472++0x01
|
|
line.word 0x00 "ADTCS51,A/D Activation Trigger Control Status Register 51"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x474)&0x100)==0x00)
|
|
group.word 0x474++0x01
|
|
line.word 0x00 "ADTCS52,A/D Activation Trigger Control Status Register 52"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x474++0x01
|
|
line.word 0x00 "ADTCS52,A/D Activation Trigger Control Status Register 52"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x476)&0x100)==0x00)
|
|
group.word 0x476++0x01
|
|
line.word 0x00 "ADTCS53,A/D Activation Trigger Control Status Register 53"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x476++0x01
|
|
line.word 0x00 "ADTCS53,A/D Activation Trigger Control Status Register 53"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x478)&0x100)==0x00)
|
|
group.word 0x478++0x01
|
|
line.word 0x00 "ADTCS54,A/D Activation Trigger Control Status Register 54"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x478++0x01
|
|
line.word 0x00 "ADTCS54,A/D Activation Trigger Control Status Register 54"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47A)&0x100)==0x00)
|
|
group.word 0x47A++0x01
|
|
line.word 0x00 "ADTCS55,A/D Activation Trigger Control Status Register 55"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47A++0x01
|
|
line.word 0x00 "ADTCS55,A/D Activation Trigger Control Status Register 55"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47C)&0x100)==0x00)
|
|
group.word 0x47C++0x01
|
|
line.word 0x00 "ADTCS56,A/D Activation Trigger Control Status Register 56"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47C++0x01
|
|
line.word 0x00 "ADTCS56,A/D Activation Trigger Control Status Register 56"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47E)&0x100)==0x00)
|
|
group.word 0x47E++0x01
|
|
line.word 0x00 "ADTCS57,A/D Activation Trigger Control Status Register 57"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47E++0x01
|
|
line.word 0x00 "ADTCS57,A/D Activation Trigger Control Status Register 57"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x480)&0x100)==0x00)
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "ADTCS58,A/D Activation Trigger Control Status Register 58"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x480++0x01
|
|
line.word 0x00 "ADTCS58,A/D Activation Trigger Control Status Register 58"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x482)&0x100)==0x00)
|
|
group.word 0x482++0x01
|
|
line.word 0x00 "ADTCS59,A/D Activation Trigger Control Status Register 59"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x482++0x01
|
|
line.word 0x00 "ADTCS59,A/D Activation Trigger Control Status Register 59"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x484)&0x100)==0x00)
|
|
group.word 0x484++0x01
|
|
line.word 0x00 "ADTCS60,A/D Activation Trigger Control Status Register 60"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x484++0x01
|
|
line.word 0x00 "ADTCS60,A/D Activation Trigger Control Status Register 60"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x486)&0x100)==0x00)
|
|
group.word 0x486++0x01
|
|
line.word 0x00 "ADTCS61,A/D Activation Trigger Control Status Register 61"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x486++0x01
|
|
line.word 0x00 "ADTCS61,A/D Activation Trigger Control Status Register 61"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x488)&0x100)==0x00)
|
|
group.word 0x488++0x01
|
|
line.word 0x00 "ADTCS62,A/D Activation Trigger Control Status Register 62"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x488++0x01
|
|
line.word 0x00 "ADTCS62,A/D Activation Trigger Control Status Register 62"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x48A)&0x100)==0x00)
|
|
group.word 0x48A++0x01
|
|
line.word 0x00 "ADTCS63,A/D Activation Trigger Control Status Register 63"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x48A++0x01
|
|
line.word 0x00 "ADTCS63,A/D Activation Trigger Control Status Register 63"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
elif cpuis("S6J312?HAA")
|
|
if ((d.b(ad:0xB4848000+0x44C)&0x100)==0x00)
|
|
group.word 0x44C++0x01
|
|
line.word 0x00 "ADTCS3,A/D Activation Trigger Control Status Register 3"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x44C++0x01
|
|
line.word 0x00 "ADTCS3,A/D Activation Trigger Control Status Register 3"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x44E)&0x100)==0x00)
|
|
group.word 0x44E++0x01
|
|
line.word 0x00 "ADTCS4,A/D Activation Trigger Control Status Register 4"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x44E++0x01
|
|
line.word 0x00 "ADTCS4,A/D Activation Trigger Control Status Register 4"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x450)&0x100)==0x00)
|
|
group.word 0x450++0x01
|
|
line.word 0x00 "ADTCS5,A/D Activation Trigger Control Status Register 5"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x450++0x01
|
|
line.word 0x00 "ADTCS5,A/D Activation Trigger Control Status Register 5"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x452)&0x100)==0x00)
|
|
group.word 0x452++0x01
|
|
line.word 0x00 "ADTCS6,A/D Activation Trigger Control Status Register 6"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x452++0x01
|
|
line.word 0x00 "ADTCS6,A/D Activation Trigger Control Status Register 6"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x454)&0x100)==0x00)
|
|
group.word 0x454++0x01
|
|
line.word 0x00 "ADTCS7,A/D Activation Trigger Control Status Register 7"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x454++0x01
|
|
line.word 0x00 "ADTCS7,A/D Activation Trigger Control Status Register 7"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x456)&0x100)==0x00)
|
|
group.word 0x456++0x01
|
|
line.word 0x00 "ADTCS8,A/D Activation Trigger Control Status Register 8"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x456++0x01
|
|
line.word 0x00 "ADTCS8,A/D Activation Trigger Control Status Register 8"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x458)&0x100)==0x00)
|
|
group.word 0x458++0x01
|
|
line.word 0x00 "ADTCS9,A/D Activation Trigger Control Status Register 9"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x458++0x01
|
|
line.word 0x00 "ADTCS9,A/D Activation Trigger Control Status Register 9"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45A)&0x100)==0x00)
|
|
group.word 0x45A++0x01
|
|
line.word 0x00 "ADTCS10,A/D Activation Trigger Control Status Register 10"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45A++0x01
|
|
line.word 0x00 "ADTCS10,A/D Activation Trigger Control Status Register 10"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45C)&0x100)==0x00)
|
|
group.word 0x45C++0x01
|
|
line.word 0x00 "ADTCS11,A/D Activation Trigger Control Status Register 11"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45C++0x01
|
|
line.word 0x00 "ADTCS11,A/D Activation Trigger Control Status Register 11"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x45E)&0x100)==0x00)
|
|
group.word 0x45E++0x01
|
|
line.word 0x00 "ADTCS12,A/D Activation Trigger Control Status Register 12"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x45E++0x01
|
|
line.word 0x00 "ADTCS12,A/D Activation Trigger Control Status Register 12"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x460)&0x100)==0x00)
|
|
group.word 0x460++0x01
|
|
line.word 0x00 "ADTCS13,A/D Activation Trigger Control Status Register 13"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x460++0x01
|
|
line.word 0x00 "ADTCS13,A/D Activation Trigger Control Status Register 13"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x462)&0x100)==0x00)
|
|
group.word 0x462++0x01
|
|
line.word 0x00 "ADTCS14,A/D Activation Trigger Control Status Register 14"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x462++0x01
|
|
line.word 0x00 "ADTCS14,A/D Activation Trigger Control Status Register 14"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x464)&0x100)==0x00)
|
|
group.word 0x464++0x01
|
|
line.word 0x00 "ADTCS15,A/D Activation Trigger Control Status Register 15"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x464++0x01
|
|
line.word 0x00 "ADTCS15,A/D Activation Trigger Control Status Register 15"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x466)&0x100)==0x00)
|
|
group.word 0x466++0x01
|
|
line.word 0x00 "ADTCS16,A/D Activation Trigger Control Status Register 16"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x466++0x01
|
|
line.word 0x00 "ADTCS16,A/D Activation Trigger Control Status Register 16"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x468)&0x100)==0x00)
|
|
group.word 0x468++0x01
|
|
line.word 0x00 "ADTCS17,A/D Activation Trigger Control Status Register 17"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x468++0x01
|
|
line.word 0x00 "ADTCS17,A/D Activation Trigger Control Status Register 17"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46A)&0x100)==0x00)
|
|
group.word 0x46A++0x01
|
|
line.word 0x00 "ADTCS18,A/D Activation Trigger Control Status Register 18"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46A++0x01
|
|
line.word 0x00 "ADTCS18,A/D Activation Trigger Control Status Register 18"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46C)&0x100)==0x00)
|
|
group.word 0x46C++0x01
|
|
line.word 0x00 "ADTCS19,A/D Activation Trigger Control Status Register 19"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46C++0x01
|
|
line.word 0x00 "ADTCS19,A/D Activation Trigger Control Status Register 19"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x46E)&0x100)==0x00)
|
|
group.word 0x46E++0x01
|
|
line.word 0x00 "ADTCS20,A/D Activation Trigger Control Status Register 20"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x46E++0x01
|
|
line.word 0x00 "ADTCS20,A/D Activation Trigger Control Status Register 20"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x470)&0x100)==0x00)
|
|
group.word 0x470++0x01
|
|
line.word 0x00 "ADTCS21,A/D Activation Trigger Control Status Register 21"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x470++0x01
|
|
line.word 0x00 "ADTCS21,A/D Activation Trigger Control Status Register 21"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x472)&0x100)==0x00)
|
|
group.word 0x472++0x01
|
|
line.word 0x00 "ADTCS22,A/D Activation Trigger Control Status Register 22"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x472++0x01
|
|
line.word 0x00 "ADTCS22,A/D Activation Trigger Control Status Register 22"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x474)&0x100)==0x00)
|
|
group.word 0x474++0x01
|
|
line.word 0x00 "ADTCS23,A/D Activation Trigger Control Status Register 23"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x474++0x01
|
|
line.word 0x00 "ADTCS23,A/D Activation Trigger Control Status Register 23"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x476)&0x100)==0x00)
|
|
group.word 0x476++0x01
|
|
line.word 0x00 "ADTCS24,A/D Activation Trigger Control Status Register 24"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x476++0x01
|
|
line.word 0x00 "ADTCS24,A/D Activation Trigger Control Status Register 24"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x478)&0x100)==0x00)
|
|
group.word 0x478++0x01
|
|
line.word 0x00 "ADTCS25,A/D Activation Trigger Control Status Register 25"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x478++0x01
|
|
line.word 0x00 "ADTCS25,A/D Activation Trigger Control Status Register 25"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47A)&0x100)==0x00)
|
|
group.word 0x47A++0x01
|
|
line.word 0x00 "ADTCS26,A/D Activation Trigger Control Status Register 26"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47A++0x01
|
|
line.word 0x00 "ADTCS26,A/D Activation Trigger Control Status Register 26"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47C)&0x100)==0x00)
|
|
group.word 0x47C++0x01
|
|
line.word 0x00 "ADTCS27,A/D Activation Trigger Control Status Register 27"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47C++0x01
|
|
line.word 0x00 "ADTCS27,A/D Activation Trigger Control Status Register 27"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x47E)&0x100)==0x00)
|
|
group.word 0x47E++0x01
|
|
line.word 0x00 "ADTCS28,A/D Activation Trigger Control Status Register 28"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x47E++0x01
|
|
line.word 0x00 "ADTCS28,A/D Activation Trigger Control Status Register 28"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x480)&0x100)==0x00)
|
|
group.word 0x480++0x01
|
|
line.word 0x00 "ADTCS29,A/D Activation Trigger Control Status Register 29"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x480++0x01
|
|
line.word 0x00 "ADTCS29,A/D Activation Trigger Control Status Register 29"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x482)&0x100)==0x00)
|
|
group.word 0x482++0x01
|
|
line.word 0x00 "ADTCS30,A/D Activation Trigger Control Status Register 30"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x482++0x01
|
|
line.word 0x00 "ADTCS30,A/D Activation Trigger Control Status Register 30"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
if ((d.b(ad:0xB4848000+0x484)&0x100)==0x00)
|
|
group.word 0x484++0x01
|
|
line.word 0x00 "ADTCS31,A/D Activation Trigger Control Status Register 31"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Software activation,,Rising edge,Compare match activation"
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
else
|
|
group.byte 0x484++0x01
|
|
line.word 0x00 "ADTCS31,A/D Activation Trigger Control Status Register 31"
|
|
rbitfld.word 0x00 15. " BUSY ,A/D activation request in progress bit" "Idle,Busy"
|
|
rbitfld.word 0x00 14. " INT ,Interrupt request flag bit" "Not completed,Completed"
|
|
bitfld.word 0x00 13. " INTE ,Interrupt Request Enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--12. " STS ,A/D activation factor selection bits" "Rising edge,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " RPT ,Repeat conversion selection bit" "Single,Repeat"
|
|
bitfld.word 0x00 9. " PRT ,A/D data register protection enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " PRTS ,A/D data register protection release selection bit" "Cleared,Reading"
|
|
bitfld.word 0x00 6.--7. " SEL ,Count direction selection bits" "Both up/down,Only up,Only down,"
|
|
textline " "
|
|
bitfld.word 0x00 5. " BUFX ,Compare register buffer function control bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " BTS ,Compare register buffer transfer control bit" "0 detected,Compare clear"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "ADTCD0,A/D Data Register 0"
|
|
in
|
|
hgroup.word 0x8E++0x01
|
|
hide.word 0x00 "ADTCD1,A/D Data Register 1"
|
|
in
|
|
hgroup.word 0x90++0x01
|
|
hide.word 0x00 "ADTCD2,A/D Data Register 2"
|
|
in
|
|
hgroup.word 0x92++0x01
|
|
hide.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
in
|
|
hgroup.word 0x94++0x01
|
|
hide.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
in
|
|
hgroup.word 0x96++0x01
|
|
hide.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
in
|
|
hgroup.word 0x98++0x01
|
|
hide.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
in
|
|
hgroup.word 0x9A++0x01
|
|
hide.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
in
|
|
hgroup.word 0x9C++0x01
|
|
hide.word 0x00 "ADTCD8,A/D Data Register 8"
|
|
in
|
|
hgroup.word 0x9E++0x01
|
|
hide.word 0x00 "ADTCD9,A/D Data Register 9"
|
|
in
|
|
hgroup.word 0xA0++0x01
|
|
hide.word 0x00 "ADTCD10,A/D Data Register 10"
|
|
in
|
|
hgroup.word 0xA2++0x01
|
|
hide.word 0x00 "ADTCD11,A/D Data Register 11"
|
|
in
|
|
hgroup.word 0xA4++0x01
|
|
hide.word 0x00 "ADTCD12,A/D Data Register 12"
|
|
in
|
|
hgroup.word 0xA6++0x01
|
|
hide.word 0x00 "ADTCD13,A/D Data Register 13"
|
|
in
|
|
hgroup.word 0xA8++0x01
|
|
hide.word 0x00 "ADTCD14,A/D Data Register 14"
|
|
in
|
|
hgroup.word 0xAA++0x01
|
|
hide.word 0x00 "ADTCD15,A/D Data Register 15"
|
|
in
|
|
hgroup.word 0xAC++0x01
|
|
hide.word 0x00 "ADTCD16,A/D Data Register 16"
|
|
in
|
|
hgroup.word 0xAE++0x01
|
|
hide.word 0x00 "ADTCD17,A/D Data Register 17"
|
|
in
|
|
hgroup.word 0xB0++0x01
|
|
hide.word 0x00 "ADTCD18,A/D Data Register 18"
|
|
in
|
|
hgroup.word 0xB2++0x01
|
|
hide.word 0x00 "ADTCD19,A/D Data Register 19"
|
|
in
|
|
hgroup.word 0xB4++0x01
|
|
hide.word 0x00 "ADTCD20,A/D Data Register 20"
|
|
in
|
|
hgroup.word 0xB6++0x01
|
|
hide.word 0x00 "ADTCD21,A/D Data Register 21"
|
|
in
|
|
hgroup.word 0xB8++0x01
|
|
hide.word 0x00 "ADTCD22,A/D Data Register 22"
|
|
in
|
|
hgroup.word 0xBA++0x01
|
|
hide.word 0x00 "ADTCD23,A/D Data Register 23"
|
|
in
|
|
hgroup.word 0xBC++0x01
|
|
hide.word 0x00 "ADTCD24,A/D Data Register 24"
|
|
in
|
|
hgroup.word 0xBE++0x01
|
|
hide.word 0x00 "ADTCD25,A/D Data Register 25"
|
|
in
|
|
hgroup.word 0xC0++0x01
|
|
hide.word 0x00 "ADTCD26,A/D Data Register 26"
|
|
in
|
|
hgroup.word 0xC2++0x01
|
|
hide.word 0x00 "ADTCD27,A/D Data Register 27"
|
|
in
|
|
hgroup.word 0xC4++0x01
|
|
hide.word 0x00 "ADTCD28,A/D Data Register 28"
|
|
in
|
|
hgroup.word 0xC6++0x01
|
|
hide.word 0x00 "ADTCD29,A/D Data Register 29"
|
|
in
|
|
hgroup.word 0xC8++0x01
|
|
hide.word 0x00 "ADTCD30,A/D Data Register 30"
|
|
in
|
|
hgroup.word 0xCA++0x01
|
|
hide.word 0x00 "ADTCD31,A/D Data Register 31"
|
|
in
|
|
elif cpuis("S6J312?HAA")
|
|
hgroup.word 0x8C++0x01
|
|
hide.word 0x00 "ADTCD3,A/D Data Register 3"
|
|
in
|
|
hgroup.word 0x8E++0x01
|
|
hide.word 0x00 "ADTCD4,A/D Data Register 4"
|
|
in
|
|
hgroup.word 0x90++0x01
|
|
hide.word 0x00 "ADTCD5,A/D Data Register 5"
|
|
in
|
|
hgroup.word 0x92++0x01
|
|
hide.word 0x00 "ADTCD6,A/D Data Register 6"
|
|
in
|
|
hgroup.word 0x94++0x01
|
|
hide.word 0x00 "ADTCD7,A/D Data Register 7"
|
|
in
|
|
hgroup.word 0x96++0x01
|
|
hide.word 0x00 "ADTCD8,A/D Data Register 8"
|
|
in
|
|
hgroup.word 0x98++0x01
|
|
hide.word 0x00 "ADTCD9,A/D Data Register 9"
|
|
in
|
|
hgroup.word 0x9A++0x01
|
|
hide.word 0x00 "ADTCD10,A/D Data Register 10"
|
|
in
|
|
hgroup.word 0x9C++0x01
|
|
hide.word 0x00 "ADTCD11,A/D Data Register 11"
|
|
in
|
|
hgroup.word 0x9E++0x01
|
|
hide.word 0x00 "ADTCD12,A/D Data Register 12"
|
|
in
|
|
hgroup.word 0xA0++0x01
|
|
hide.word 0x00 "ADTCD13,A/D Data Register 13"
|
|
in
|
|
hgroup.word 0xA2++0x01
|
|
hide.word 0x00 "ADTCD14,A/D Data Register 14"
|
|
in
|
|
hgroup.word 0xA4++0x01
|
|
hide.word 0x00 "ADTCD15,A/D Data Register 15"
|
|
in
|
|
hgroup.word 0xA6++0x01
|
|
hide.word 0x00 "ADTCD16,A/D Data Register 16"
|
|
in
|
|
hgroup.word 0xA8++0x01
|
|
hide.word 0x00 "ADTCD17,A/D Data Register 17"
|
|
in
|
|
hgroup.word 0xAA++0x01
|
|
hide.word 0x00 "ADTCD18,A/D Data Register 18"
|
|
in
|
|
hgroup.word 0xAC++0x01
|
|
hide.word 0x00 "ADTCD19,A/D Data Register 19"
|
|
in
|
|
hgroup.word 0xAE++0x01
|
|
hide.word 0x00 "ADTCD20,A/D Data Register 20"
|
|
in
|
|
hgroup.word 0xB0++0x01
|
|
hide.word 0x00 "ADTCD21,A/D Data Register 21"
|
|
in
|
|
hgroup.word 0xB2++0x01
|
|
hide.word 0x00 "ADTCD22,A/D Data Register 22"
|
|
in
|
|
hgroup.word 0xB4++0x01
|
|
hide.word 0x00 "ADTCD23,A/D Data Register 23"
|
|
in
|
|
hgroup.word 0xB6++0x01
|
|
hide.word 0x00 "ADTCD24,A/D Data Register 24"
|
|
in
|
|
hgroup.word 0xB8++0x01
|
|
hide.word 0x00 "ADTCD25,A/D Data Register 25"
|
|
in
|
|
hgroup.word 0xBA++0x01
|
|
hide.word 0x00 "ADTCD26,A/D Data Register 26"
|
|
in
|
|
hgroup.word 0xBC++0x01
|
|
hide.word 0x00 "ADTCD27,A/D Data Register 27"
|
|
in
|
|
hgroup.word 0xBE++0x01
|
|
hide.word 0x00 "ADTCD28,A/D Data Register 28"
|
|
in
|
|
hgroup.word 0xC0++0x01
|
|
hide.word 0x00 "ADTCD29,A/D Data Register 29"
|
|
in
|
|
hgroup.word 0xC2++0x01
|
|
hide.word 0x00 "ADTCD30,A/D Data Register 30"
|
|
in
|
|
hgroup.word 0xC4++0x01
|
|
hide.word 0x00 "ADTCD31,A/D Data Register 31"
|
|
in
|
|
endif
|
|
hgroup.word 0x48C++0x01
|
|
hide.word 0x00 "ADTCD32,A/D Data Register 32"
|
|
in
|
|
hgroup.word 0x48E++0x01
|
|
hide.word 0x00 "ADTCD33,A/D Data Register 33"
|
|
in
|
|
hgroup.word 0x490++0x01
|
|
hide.word 0x00 "ADTCD34,A/D Data Register 34"
|
|
in
|
|
hgroup.word 0x492++0x01
|
|
hide.word 0x00 "ADTCD35,A/D Data Register 35"
|
|
in
|
|
hgroup.word 0x494++0x01
|
|
hide.word 0x00 "ADTCD36,A/D Data Register 36"
|
|
in
|
|
hgroup.word 0x496++0x01
|
|
hide.word 0x00 "ADTCD37,A/D Data Register 37"
|
|
in
|
|
hgroup.word 0x498++0x01
|
|
hide.word 0x00 "ADTCD38,A/D Data Register 38"
|
|
in
|
|
hgroup.word 0x49A++0x01
|
|
hide.word 0x00 "ADTCD39,A/D Data Register 39"
|
|
in
|
|
hgroup.word 0x49C++0x01
|
|
hide.word 0x00 "ADTCD40,A/D Data Register 40"
|
|
in
|
|
hgroup.word 0x49E++0x01
|
|
hide.word 0x00 "ADTCD41,A/D Data Register 41"
|
|
in
|
|
hgroup.word 0x4A0++0x01
|
|
hide.word 0x00 "ADTCD42,A/D Data Register 42"
|
|
in
|
|
hgroup.word 0x4A2++0x01
|
|
hide.word 0x00 "ADTCD43,A/D Data Register 43"
|
|
in
|
|
hgroup.word 0x4A4++0x01
|
|
hide.word 0x00 "ADTCD44,A/D Data Register 44"
|
|
in
|
|
hgroup.word 0x4A6++0x01
|
|
hide.word 0x00 "ADTCD45,A/D Data Register 45"
|
|
in
|
|
hgroup.word 0x4A8++0x01
|
|
hide.word 0x00 "ADTCD46,A/D Data Register 46"
|
|
in
|
|
hgroup.word 0x4AA++0x01
|
|
hide.word 0x00 "ADTCD47,A/D Data Register 47"
|
|
in
|
|
hgroup.word 0x4AC++0x01
|
|
hide.word 0x00 "ADTCD48,A/D Data Register 48"
|
|
in
|
|
hgroup.word 0x4AE++0x01
|
|
hide.word 0x00 "ADTCD49,A/D Data Register 49"
|
|
in
|
|
hgroup.word 0x4B0++0x01
|
|
hide.word 0x00 "ADTCD50,A/D Data Register 50"
|
|
in
|
|
hgroup.word 0x4B2++0x01
|
|
hide.word 0x00 "ADTCD51,A/D Data Register 51"
|
|
in
|
|
hgroup.word 0x4B4++0x01
|
|
hide.word 0x00 "ADTCD52,A/D Data Register 52"
|
|
in
|
|
hgroup.word 0x4B6++0x01
|
|
hide.word 0x00 "ADTCD53,A/D Data Register 53"
|
|
in
|
|
hgroup.word 0x4B8++0x01
|
|
hide.word 0x00 "ADTCD54,A/D Data Register 54"
|
|
in
|
|
hgroup.word 0x4BA++0x01
|
|
hide.word 0x00 "ADTCD55,A/D Data Register 55"
|
|
in
|
|
hgroup.word 0x4BC++0x01
|
|
hide.word 0x00 "ADTCD56,A/D Data Register 56"
|
|
in
|
|
hgroup.word 0x4BE++0x01
|
|
hide.word 0x00 "ADTCD57,A/D Data Register 57"
|
|
in
|
|
hgroup.word 0x4C0++0x01
|
|
hide.word 0x00 "ADTCD58,A/D Data Register 58"
|
|
in
|
|
hgroup.word 0x4C2++0x01
|
|
hide.word 0x00 "ADTCD59,A/D Data Register 59"
|
|
in
|
|
hgroup.word 0x4C4++0x01
|
|
hide.word 0x00 "ADTCD60,A/D Data Register 60"
|
|
in
|
|
hgroup.word 0x4C6++0x01
|
|
hide.word 0x00 "ADTCD61,A/D Data Register 61"
|
|
in
|
|
hgroup.word 0x4C8++0x01
|
|
hide.word 0x00 "ADTCD62,A/D Data Register 62"
|
|
in
|
|
hgroup.word 0x4CA++0x01
|
|
hide.word 0x00 "ADTCD63,A/D Data Register 63"
|
|
in
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "ADTECS0,A/D Activation Trigger Extended Control Register 0"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xCE++0x01
|
|
line.word 0x00 "ADTECS1,A/D Activation Trigger Extended Control Register 1"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "ADTECS2,A/D Activation Trigger Extended Control Register 2"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "ADTECS3,A/D Activation Trigger Extended Control Register 3"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "ADTECS4,A/D Activation Trigger Extended Control Register 4"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "ADTECS5,A/D Activation Trigger Extended Control Register 5"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "ADTECS6,A/D Activation Trigger Extended Control Register 6"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "ADTECS7,A/D Activation Trigger Extended Control Register 7"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "ADTECS8,A/D Activation Trigger Extended Control Register 8"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDE++0x01
|
|
line.word 0x00 "ADTECS9,A/D Activation Trigger Extended Control Register 9"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE0++0x01
|
|
line.word 0x00 "ADTECS10,A/D Activation Trigger Extended Control Register 10"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE2++0x01
|
|
line.word 0x00 "ADTECS11,A/D Activation Trigger Extended Control Register 11"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE4++0x01
|
|
line.word 0x00 "ADTECS12,A/D Activation Trigger Extended Control Register 12"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE6++0x01
|
|
line.word 0x00 "ADTECS13,A/D Activation Trigger Extended Control Register 13"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE8++0x01
|
|
line.word 0x00 "ADTECS14,A/D Activation Trigger Extended Control Register 14"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEA++0x01
|
|
line.word 0x00 "ADTECS15,A/D Activation Trigger Extended Control Register 15"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEC++0x01
|
|
line.word 0x00 "ADTECS16,A/D Activation Trigger Extended Control Register 16"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEE++0x01
|
|
line.word 0x00 "ADTECS17,A/D Activation Trigger Extended Control Register 17"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF0++0x01
|
|
line.word 0x00 "ADTECS18,A/D Activation Trigger Extended Control Register 18"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF2++0x01
|
|
line.word 0x00 "ADTECS19,A/D Activation Trigger Extended Control Register 19"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF4++0x01
|
|
line.word 0x00 "ADTECS20,A/D Activation Trigger Extended Control Register 20"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF6++0x01
|
|
line.word 0x00 "ADTECS21,A/D Activation Trigger Extended Control Register 21"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF8++0x01
|
|
line.word 0x00 "ADTECS22,A/D Activation Trigger Extended Control Register 22"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFA++0x01
|
|
line.word 0x00 "ADTECS23,A/D Activation Trigger Extended Control Register 23"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "ADTECS24,A/D Activation Trigger Extended Control Register 24"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFE++0x01
|
|
line.word 0x00 "ADTECS25,A/D Activation Trigger Extended Control Register 25"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "ADTECS26,A/D Activation Trigger Extended Control Register 26"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "ADTECS27,A/D Activation Trigger Extended Control Register 27"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "ADTECS28,A/D Activation Trigger Extended Control Register 28"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x106++0x01
|
|
line.word 0x00 "ADTECS29,A/D Activation Trigger Extended Control Register 29"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x108++0x01
|
|
line.word 0x00 "ADTECS30,A/D Activation Trigger Extended Control Register 30"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x10A++0x01
|
|
line.word 0x00 "ADTECS31,A/D Activation Trigger Extended Control Register 31"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif cpuis("S6J312?HAA")
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "ADTECS3,A/D Activation Trigger Extended Control Register 3"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xCE++0x01
|
|
line.word 0x00 "ADTECS4,A/D Activation Trigger Extended Control Register 4"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD0++0x01
|
|
line.word 0x00 "ADTECS5,A/D Activation Trigger Extended Control Register 5"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD2++0x01
|
|
line.word 0x00 "ADTECS6,A/D Activation Trigger Extended Control Register 6"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD4++0x01
|
|
line.word 0x00 "ADTECS7,A/D Activation Trigger Extended Control Register 7"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD6++0x01
|
|
line.word 0x00 "ADTECS8,A/D Activation Trigger Extended Control Register 8"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xD8++0x01
|
|
line.word 0x00 "ADTECS9,A/D Activation Trigger Extended Control Register 9"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDA++0x01
|
|
line.word 0x00 "ADTECS10,A/D Activation Trigger Extended Control Register 10"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDC++0x01
|
|
line.word 0x00 "ADTECS11,A/D Activation Trigger Extended Control Register 11"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xDE++0x01
|
|
line.word 0x00 "ADTECS12,A/D Activation Trigger Extended Control Register 12"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE0++0x01
|
|
line.word 0x00 "ADTECS13,A/D Activation Trigger Extended Control Register 13"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE2++0x01
|
|
line.word 0x00 "ADTECS14,A/D Activation Trigger Extended Control Register 14"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE4++0x01
|
|
line.word 0x00 "ADTECS15,A/D Activation Trigger Extended Control Register 15"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE6++0x01
|
|
line.word 0x00 "ADTECS16,A/D Activation Trigger Extended Control Register 16"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xE8++0x01
|
|
line.word 0x00 "ADTECS17,A/D Activation Trigger Extended Control Register 17"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEA++0x01
|
|
line.word 0x00 "ADTECS18,A/D Activation Trigger Extended Control Register 18"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEC++0x01
|
|
line.word 0x00 "ADTECS19,A/D Activation Trigger Extended Control Register 19"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xEE++0x01
|
|
line.word 0x00 "ADTECS20,A/D Activation Trigger Extended Control Register 20"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF0++0x01
|
|
line.word 0x00 "ADTECS21,A/D Activation Trigger Extended Control Register 21"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF2++0x01
|
|
line.word 0x00 "ADTECS22,A/D Activation Trigger Extended Control Register 22"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF4++0x01
|
|
line.word 0x00 "ADTECS23,A/D Activation Trigger Extended Control Register 23"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF6++0x01
|
|
line.word 0x00 "ADTECS24,A/D Activation Trigger Extended Control Register 24"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xF8++0x01
|
|
line.word 0x00 "ADTECS25,A/D Activation Trigger Extended Control Register 25"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFA++0x01
|
|
line.word 0x00 "ADTECS26,A/D Activation Trigger Extended Control Register 26"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFC++0x01
|
|
line.word 0x00 "ADTECS27,A/D Activation Trigger Extended Control Register 27"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0xFE++0x01
|
|
line.word 0x00 "ADTECS28,A/D Activation Trigger Extended Control Register 28"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "ADTECS29,A/D Activation Trigger Extended Control Register 29"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "ADTECS30,A/D Activation Trigger Extended Control Register 30"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "ADTECS31,A/D Activation Trigger Extended Control Register 31"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word 0x4CC++0x01
|
|
line.word 0x00 "ADTECS32,A/D Activation Trigger Extended Control Register 32"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4CE++0x01
|
|
line.word 0x00 "ADTECS33,A/D Activation Trigger Extended Control Register 33"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4D0++0x01
|
|
line.word 0x00 "ADTECS34,A/D Activation Trigger Extended Control Register 34"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4D2++0x01
|
|
line.word 0x00 "ADTECS35,A/D Activation Trigger Extended Control Register 35"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4D4++0x01
|
|
line.word 0x00 "ADTECS36,A/D Activation Trigger Extended Control Register 36"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4D6++0x01
|
|
line.word 0x00 "ADTECS37,A/D Activation Trigger Extended Control Register 37"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4D8++0x01
|
|
line.word 0x00 "ADTECS38,A/D Activation Trigger Extended Control Register 38"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4DA++0x01
|
|
line.word 0x00 "ADTECS39,A/D Activation Trigger Extended Control Register 39"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4DC++0x01
|
|
line.word 0x00 "ADTECS40,A/D Activation Trigger Extended Control Register 40"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4DE++0x01
|
|
line.word 0x00 "ADTECS41,A/D Activation Trigger Extended Control Register 41"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4E0++0x01
|
|
line.word 0x00 "ADTECS42,A/D Activation Trigger Extended Control Register 42"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4E2++0x01
|
|
line.word 0x00 "ADTECS43,A/D Activation Trigger Extended Control Register 43"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4E4++0x01
|
|
line.word 0x00 "ADTECS44,A/D Activation Trigger Extended Control Register 44"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4E6++0x01
|
|
line.word 0x00 "ADTECS45,A/D Activation Trigger Extended Control Register 45"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4E8++0x01
|
|
line.word 0x00 "ADTECS46,A/D Activation Trigger Extended Control Register 46"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4EA++0x01
|
|
line.word 0x00 "ADTECS47,A/D Activation Trigger Extended Control Register 47"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4EC++0x01
|
|
line.word 0x00 "ADTECS48,A/D Activation Trigger Extended Control Register 48"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4EE++0x01
|
|
line.word 0x00 "ADTECS49,A/D Activation Trigger Extended Control Register 49"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4F0++0x01
|
|
line.word 0x00 "ADTECS50,A/D Activation Trigger Extended Control Register 50"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4F2++0x01
|
|
line.word 0x00 "ADTECS51,A/D Activation Trigger Extended Control Register 51"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4F4++0x01
|
|
line.word 0x00 "ADTECS52,A/D Activation Trigger Extended Control Register 52"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4F6++0x01
|
|
line.word 0x00 "ADTECS53,A/D Activation Trigger Extended Control Register 53"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4F8++0x01
|
|
line.word 0x00 "ADTECS54,A/D Activation Trigger Extended Control Register 54"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4FA++0x01
|
|
line.word 0x00 "ADTECS55,A/D Activation Trigger Extended Control Register 55"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4FC++0x01
|
|
line.word 0x00 "ADTECS56,A/D Activation Trigger Extended Control Register 56"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x4FE++0x01
|
|
line.word 0x00 "ADTECS57,A/D Activation Trigger Extended Control Register 57"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x500++0x01
|
|
line.word 0x00 "ADTECS58,A/D Activation Trigger Extended Control Register 58"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x502++0x01
|
|
line.word 0x00 "ADTECS59,A/D Activation Trigger Extended Control Register 59"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x504++0x01
|
|
line.word 0x00 "ADTECS60,A/D Activation Trigger Extended Control Register 60"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x506++0x01
|
|
line.word 0x00 "ADTECS61,A/D Activation Trigger Extended Control Register 61"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x508++0x01
|
|
line.word 0x00 "ADTECS62,A/D Activation Trigger Extended Control Register 62"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x50A++0x01
|
|
line.word 0x00 "ADTECS63,A/D Activation Trigger Extended Control Register 63"
|
|
bitfld.word 0x00 8. " STS2 ,A/D activation factor selection bit" "0,1"
|
|
bitfld.word 0x00 0.--4. " CHSEL ,Analog channel selection bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.word 0x10C++0x03
|
|
line.word 0x00 "ADRCUT0,Upper Threshold Setting Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT0,Lower Threshold Setting Register 0"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x110++0x03
|
|
line.word 0x00 "ADRCUT1,Upper Threshold Setting Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT1,Lower Threshold Setting Register 1"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x114++0x03
|
|
line.word 0x00 "ADRCUT2,Upper Threshold Setting Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT2,Lower Threshold Setting Register 2"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x118++0x03
|
|
line.word 0x00 "ADRCUT3,Upper Threshold Setting Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT3,Lower Threshold Setting Register 3"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x50C++0x03
|
|
line.word 0x00 "ADRCUT4,Upper Threshold Setting Register 4"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT4,Lower Threshold Setting Register 4"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x510++0x03
|
|
line.word 0x00 "ADRCUT5,Upper Threshold Setting Register 5"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT5,Lower Threshold Setting Register 5"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x514++0x03
|
|
line.word 0x00 "ADRCUT6,Upper Threshold Setting Register 6"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT6,Lower Threshold Setting Register 6"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
group.word 0x518++0x03
|
|
line.word 0x00 "ADRCUT7,Upper Threshold Setting Register 7"
|
|
hexmask.word 0x00 0.--11. 1. " C ,Lower threshold bit"
|
|
line.word 0x02 "ADRCLT7,Lower Threshold Setting Register 7"
|
|
hexmask.word 0x02 0.--11. 1. " C ,Lower threshold bit"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "ADRCCS0,Range Comparison Control Status Register 0"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "ADRCCS1,Range Comparison Control Status Register 1"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "ADRCCS2,Range Comparison Control Status Register 2"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "ADRCCS8,Range Comparison Control Status Register 8"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "ADRCCS9,Range Comparison Control Status Register 9"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "ADRCCS10,Range Comparison Control Status Register 10"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "ADRCCS11,Range Comparison Control Status Register 11"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "ADRCCS12,Range Comparison Control Status Register 12"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "ADRCCS13,Range Comparison Control Status Register 13"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "ADRCCS14,Range Comparison Control Status Register 14"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "ADRCCS15,Range Comparison Control Status Register 15"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "ADRCCS16,Range Comparison Control Status Register 16"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "ADRCCS17,Range Comparison Control Status Register 17"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "ADRCCS18,Range Comparison Control Status Register 18"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "ADRCCS19,Range Comparison Control Status Register 19"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "ADRCCS20,Range Comparison Control Status Register 20"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "ADRCCS21,Range Comparison Control Status Register 21"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "ADRCCS22,Range Comparison Control Status Register 22"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "ADRCCS23,Range Comparison Control Status Register 23"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "ADRCCS24,Range Comparison Control Status Register 24"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "ADRCCS25,Range Comparison Control Status Register 25"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "ADRCCS26,Range Comparison Control Status Register 26"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "ADRCCS27,Range Comparison Control Status Register 27"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "ADRCCS28,Range Comparison Control Status Register 28"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "ADRCCS29,Range Comparison Control Status Register 29"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "ADRCCS30,Range Comparison Control Status Register 30"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "ADRCCS31,Range Comparison Control Status Register 31"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
elif cpuis("S6J312?HAA")
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "ADRCCS3,Range Comparison Control Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "ADRCCS4,Range Comparison Control Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "ADRCCS5,Range Comparison Control Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "ADRCCS6,Range Comparison Control Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "ADRCCS7,Range Comparison Control Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "ADRCCS8,Range Comparison Control Status Register 8"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "ADRCCS9,Range Comparison Control Status Register 9"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "ADRCCS10,Range Comparison Control Status Register 10"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "ADRCCS11,Range Comparison Control Status Register 11"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "ADRCCS12,Range Comparison Control Status Register 12"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "ADRCCS13,Range Comparison Control Status Register 13"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "ADRCCS14,Range Comparison Control Status Register 14"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "ADRCCS15,Range Comparison Control Status Register 15"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "ADRCCS16,Range Comparison Control Status Register 16"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "ADRCCS17,Range Comparison Control Status Register 17"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "ADRCCS18,Range Comparison Control Status Register 18"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "ADRCCS19,Range Comparison Control Status Register 19"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "ADRCCS20,Range Comparison Control Status Register 20"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "ADRCCS21,Range Comparison Control Status Register 21"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "ADRCCS22,Range Comparison Control Status Register 22"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "ADRCCS23,Range Comparison Control Status Register 23"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "ADRCCS24,Range Comparison Control Status Register 24"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "ADRCCS25,Range Comparison Control Status Register 25"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "ADRCCS26,Range Comparison Control Status Register 26"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "ADRCCS27,Range Comparison Control Status Register 27"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "ADRCCS28,Range Comparison Control Status Register 28"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "ADRCCS29,Range Comparison Control Status Register 29"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "ADRCCS30,Range Comparison Control Status Register 30"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "ADRCCS31,Range Comparison Control Status Register 31"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
endif
|
|
group.byte 0x51C++0x00
|
|
line.byte 0x00 "ADRCCS32,Range Comparison Control Status Register 32"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x51D++0x00
|
|
line.byte 0x00 "ADRCCS33,Range Comparison Control Status Register 33"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x51E++0x00
|
|
line.byte 0x00 "ADRCCS34,Range Comparison Control Status Register 34"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x51F++0x00
|
|
line.byte 0x00 "ADRCCS35,Range Comparison Control Status Register 35"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x520++0x00
|
|
line.byte 0x00 "ADRCCS36,Range Comparison Control Status Register 36"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x521++0x00
|
|
line.byte 0x00 "ADRCCS37,Range Comparison Control Status Register 37"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x522++0x00
|
|
line.byte 0x00 "ADRCCS38,Range Comparison Control Status Register 38"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x523++0x00
|
|
line.byte 0x00 "ADRCCS39,Range Comparison Control Status Register 39"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x524++0x00
|
|
line.byte 0x00 "ADRCCS40,Range Comparison Control Status Register 40"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x525++0x00
|
|
line.byte 0x00 "ADRCCS41,Range Comparison Control Status Register 41"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x526++0x00
|
|
line.byte 0x00 "ADRCCS42,Range Comparison Control Status Register 42"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x527++0x00
|
|
line.byte 0x00 "ADRCCS43,Range Comparison Control Status Register 43"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x528++0x00
|
|
line.byte 0x00 "ADRCCS44,Range Comparison Control Status Register 44"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x529++0x00
|
|
line.byte 0x00 "ADRCCS45,Range Comparison Control Status Register 45"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52A++0x00
|
|
line.byte 0x00 "ADRCCS46,Range Comparison Control Status Register 46"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52B++0x00
|
|
line.byte 0x00 "ADRCCS47,Range Comparison Control Status Register 47"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52C++0x00
|
|
line.byte 0x00 "ADRCCS48,Range Comparison Control Status Register 48"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52D++0x00
|
|
line.byte 0x00 "ADRCCS49,Range Comparison Control Status Register 49"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52E++0x00
|
|
line.byte 0x00 "ADRCCS50,Range Comparison Control Status Register 50"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x52F++0x00
|
|
line.byte 0x00 "ADRCCS51,Range Comparison Control Status Register 51"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x530++0x00
|
|
line.byte 0x00 "ADRCCS52,Range Comparison Control Status Register 52"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x531++0x00
|
|
line.byte 0x00 "ADRCCS53,Range Comparison Control Status Register 53"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x532++0x00
|
|
line.byte 0x00 "ADRCCS54,Range Comparison Control Status Register 54"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x533++0x00
|
|
line.byte 0x00 "ADRCCS55,Range Comparison Control Status Register 55"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x534++0x00
|
|
line.byte 0x00 "ADRCCS56,Range Comparison Control Status Register 56"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x535++0x00
|
|
line.byte 0x00 "ADRCCS57,Range Comparison Control Status Register 57"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x536++0x00
|
|
line.byte 0x00 "ADRCCS58,Range Comparison Control Status Register 58"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x537++0x00
|
|
line.byte 0x00 "ADRCCS59,Range Comparison Control Status Register 59"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x538++0x00
|
|
line.byte 0x00 "ADRCCS60,Range Comparison Control Status Register 60"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x539++0x00
|
|
line.byte 0x00 "ADRCCS61,Range Comparison Control Status Register 61"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x53A++0x00
|
|
line.byte 0x00 "ADRCCS62,Range Comparison Control Status Register 62"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
group.byte 0x53B++0x00
|
|
line.byte 0x00 "ADRCCS63,Range Comparison Control Status Register 63"
|
|
bitfld.byte 0x00 5.--7. " RCOCD ,Continuous detection count specification bits" ",1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRS ,Inside/outside-range check selection bit" "Outside,Inside"
|
|
bitfld.byte 0x00 3. " RCOIE ,Range comparison interrupt request enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RCOE ,Range comparison execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTS ,Upper and lower threshold selection bits" "0,1,2,3"
|
|
sif cpuis("S6J311?JAA")
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ADRCOT0_00,Range Comparison Threshold Excess Flag Register 0"
|
|
bitfld.long 0x00 31. " RCOOF_[31] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 26. " [26] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 25. " [25] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 16. " [16] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 8. " [8] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 4. " [4] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 2. " [2] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 1. " [1] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 0. " [0] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
elif cpuis("S6J311?HAA")
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ADRCOT0_00,Range Comparison Threshold Excess Flag Register 0"
|
|
bitfld.long 0x00 31. " RCOOF_[31] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 2. " [2] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 1. " [1] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "ADRCOT0_00,Range Comparison Threshold Excess Flag Register 0"
|
|
bitfld.long 0x00 31. " RCOOF_[31] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
endif
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "ADRCOT1,Range Comparison Threshold Excess Flag Register 1"
|
|
bitfld.long 0x00 31. " RCOOF_[63] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 30. " [62] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 29. " [61] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 28. " [60] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 26. " [58] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 25. " [57] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 24. " [56] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 22. " [54] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 21. " [53] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 20. " [52] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 18. " [49] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 17. " [48] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 16. " [47] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [46] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 14. " [45] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 13. " [44] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 12. " [43] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [42] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 10. " [41] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 9. " [30] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 8. " [39] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [38] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 6. " [37] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 5. " [36] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 4. " [35] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [34] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 2. " [33] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 1. " [32] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 0. " [31] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "ADRCOT1,Range Comparison Threshold Excess Flag Register 1"
|
|
bitfld.long 0x00 30. " RCOOF_[62] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 29. " [61] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 28. " [60] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 27. " [59] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 25. " [57] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 24. " [56] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 23. " [55] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 20. " [52] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 19. " [51] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 18. " [49] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [48] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 16. " [47] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 15. " [46] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 12. " [43] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [42] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 10. " [41] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 9. " [30] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 8. " [39] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [38] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 6. " [37] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 5. " [36] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 4. " [35] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [34] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 2. " [33] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 1. " [32] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
bitfld.long 0x00 0. " [31] ,Conversion data error flag bit" "Below lower,Over upper"
|
|
endif
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ADRCIF0,Range Comparison Flag Register 0"
|
|
bitfld.long 0x00 31. " RCINT_[31] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 25. " [25] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 16. " [16] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Conversion data error flag bit" "0,1"
|
|
elif cpuis("S6J311?HAA")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ADRCIF0,Range Comparison Flag Register 0"
|
|
bitfld.long 0x00 31. " RCINT_[31] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Conversion data error flag bit" "0,1"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "ADRCIF0,Range Comparison Flag Register 0"
|
|
bitfld.long 0x00 31. " RCINT_[31] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [28] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 23. " [23] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 22. " [22] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 19. " [19] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 15. " [15] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 13. " [13] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Conversion data error flag bit" "0,1"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "ADRCIF1,Range Comparison Flag Register 1"
|
|
bitfld.long 0x00 31. " RCINT_[63] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 30. " [62] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [61] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [60] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 26. " [58] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 25. " [57] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [56] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 22. " [54] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 21. " [53] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [52] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 18. " [49] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 17. " [48] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 16. " [47] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [46] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 14. " [45] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 13. " [44] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 12. " [43] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [42] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 10. " [41] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 8. " [39] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [38] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 6. " [37] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 5. " [36] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 4. " [35] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [34] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 2. " [33] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 1. " [32] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 0. " [31] ,Conversion data error flag bit" "0,1"
|
|
elif cpuis("S6J311?HAA")
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "ADRCIF1,Range Comparison Flag Register 1"
|
|
bitfld.long 0x00 30. " RCINT_[62] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [61] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [60] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 27. " [59] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 25. " [57] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [56] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 23. " [55] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [54] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 21. " [53] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [52] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 19. " [51] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [49] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 17. " [48] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 16. " [47] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 15. " [46] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [45] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 13. " [44] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 12. " [43] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 11. " [42] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [41] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 8. " [39] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 7. " [38] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [37] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 5. " [36] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 4. " [35] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 3. " [34] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [33] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 1. " [32] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 0. " [31] ,Conversion data error flag bit" "0,1"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "ADRCIF1,Range Comparison Flag Register 1"
|
|
bitfld.long 0x00 30. " RCINT_[62] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 29. " [61] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 28. " [60] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 27. " [59] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 25. " [57] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 24. " [56] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 23. " [55] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 20. " [52] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 19. " [51] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 18. " [49] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [48] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 16. " [47] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 15. " [46] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 12. " [43] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [42] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 10. " [41] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 9. " [30] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 8. " [39] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [38] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 6. " [37] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 5. " [36] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 4. " [35] ,Conversion data error flag bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [34] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 2. " [33] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 1. " [32] ,Conversion data error flag bit" "0,1"
|
|
bitfld.long 0x00 0. " [31] ,Conversion data error flag bit" "0,1"
|
|
endif
|
|
textline " "
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "ADSCANS0,Scan Conversion Control Status Register 0"
|
|
rbitfld.byte 0x00 7. " SCINT ,Scan conversion completion interrupt factor flag bit" "0,1"
|
|
bitfld.byte 0x00 6. " SCIE ,Scan conversion completion interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SCMD ,Continuous/pause scan conversion mode selection bit" "Continuous,Paused"
|
|
group.byte 0x544++0x00
|
|
line.byte 0x00 "ADSCANS1,Scan Conversion Control Status Register 1"
|
|
rbitfld.byte 0x00 7. " SCINT ,Scan conversion completion interrupt factor flag bit" "0,1"
|
|
bitfld.byte 0x00 6. " SCIE ,Scan conversion completion interrupt request enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SCMD ,Continuous/pause scan conversion mode selection bit" "Continuous,Paused"
|
|
textline " "
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "ADNCS0,Activation Channel Conversion Count Setting Register 0"
|
|
bitfld.byte 0x00 7. " CNTEN1 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT1 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN0 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT0 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "ADNCS1,Activation Channel Conversion Count Setting Register 1"
|
|
bitfld.byte 0x00 7. " CNTEN3 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT3 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN2 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT2 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "ADNCS2,Activation Channel Conversion Count Setting Register 2"
|
|
bitfld.byte 0x00 7. " CNTEN5 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT5 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN4 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT4 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "ADNCS3,Activation Channel Conversion Count Setting Register 3"
|
|
bitfld.byte 0x00 7. " CNTEN7 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT7 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN6 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT6 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "ADNCS4,Activation Channel Conversion Count Setting Register 4"
|
|
bitfld.byte 0x00 7. " CNTEN9 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT9 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN8 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT8 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "ADNCS5,Activation Channel Conversion Count Setting Register 5"
|
|
bitfld.byte 0x00 7. " CNTEN11 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT11 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN10 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT10 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "ADNCS6,Activation Channel Conversion Count Setting Register 6"
|
|
bitfld.byte 0x00 7. " CNTEN13 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT13 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN12 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT12 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "ADNCS7,Activation Channel Conversion Count Setting Register 7"
|
|
bitfld.byte 0x00 7. " CNTEN15 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT15 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN14 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT14 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "ADNCS8,Activation Channel Conversion Count Setting Register 8"
|
|
bitfld.byte 0x00 7. " CNTEN17 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT17 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN16 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT16 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "ADNCS9,Activation Channel Conversion Count Setting Register 9"
|
|
bitfld.byte 0x00 7. " CNTEN19 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT19 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN18 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT18 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "ADNCS10,Activation Channel Conversion Count Setting Register 10"
|
|
bitfld.byte 0x00 7. " CNTEN21 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT21 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN20 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT20 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "ADNCS11,Activation Channel Conversion Count Setting Register 11"
|
|
bitfld.byte 0x00 7. " CNTEN23 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT23 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN22 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT22 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "ADNCS12,Activation Channel Conversion Count Setting Register 12"
|
|
bitfld.byte 0x00 7. " CNTEN25 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT25 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN24 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT24 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "ADNCS13,Activation Channel Conversion Count Setting Register 13"
|
|
bitfld.byte 0x00 7. " CNTEN27 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT27 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN26 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT26 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "ADNCS14,Activation Channel Conversion Count Setting Register 14"
|
|
bitfld.byte 0x00 7. " CNTEN29 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT29 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN28 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT28 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "ADNCS15,Activation Channel Conversion Count Setting Register 15"
|
|
bitfld.byte 0x00 7. " CNTEN31 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT31 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN30 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT30 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x548++0x00
|
|
line.byte 0x00 "ADNCS16,Activation Channel Conversion Count Setting Register 16"
|
|
bitfld.byte 0x00 7. " CNTEN32 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT32 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN31 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT31 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x549++0x00
|
|
line.byte 0x00 "ADNCS17,Activation Channel Conversion Count Setting Register 17"
|
|
bitfld.byte 0x00 7. " CNTEN34 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT34 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN33 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT33 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54A++0x00
|
|
line.byte 0x00 "ADNCS18,Activation Channel Conversion Count Setting Register 18"
|
|
bitfld.byte 0x00 7. " CNTEN36 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT36 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN35 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT35 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54B++0x00
|
|
line.byte 0x00 "ADNCS19,Activation Channel Conversion Count Setting Register 19"
|
|
bitfld.byte 0x00 7. " CNTEN38 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT38 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN37 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT37 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54C++0x00
|
|
line.byte 0x00 "ADNCS20,Activation Channel Conversion Count Setting Register 20"
|
|
bitfld.byte 0x00 7. " CNTEN40 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT40 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN39 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT39 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54D++0x00
|
|
line.byte 0x00 "ADNCS21,Activation Channel Conversion Count Setting Register 21"
|
|
bitfld.byte 0x00 7. " CNTEN42 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT42 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN41 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT41 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54E++0x00
|
|
line.byte 0x00 "ADNCS22,Activation Channel Conversion Count Setting Register 22"
|
|
bitfld.byte 0x00 7. " CNTEN44 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT44 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN43 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT43 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x54F++0x00
|
|
line.byte 0x00 "ADNCS23,Activation Channel Conversion Count Setting Register 23"
|
|
bitfld.byte 0x00 7. " CNTEN46 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT46 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN45 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT45 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x550++0x00
|
|
line.byte 0x00 "ADNCS24,Activation Channel Conversion Count Setting Register 24"
|
|
bitfld.byte 0x00 7. " CNTEN48 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT48 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN47 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT47 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x551++0x00
|
|
line.byte 0x00 "ADNCS25,Activation Channel Conversion Count Setting Register 25"
|
|
bitfld.byte 0x00 7. " CNTEN50 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT50 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN49 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT49 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x552++0x00
|
|
line.byte 0x00 "ADNCS26,Activation Channel Conversion Count Setting Register 26"
|
|
bitfld.byte 0x00 7. " CNTEN52 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT52 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN51 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT51 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x553++0x00
|
|
line.byte 0x00 "ADNCS27,Activation Channel Conversion Count Setting Register 27"
|
|
bitfld.byte 0x00 7. " CNTEN54 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT54 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN53 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT53 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x554++0x00
|
|
line.byte 0x00 "ADNCS28,Activation Channel Conversion Count Setting Register 28"
|
|
bitfld.byte 0x00 7. " CNTEN56 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT56 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN55 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT55 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x555++0x00
|
|
line.byte 0x00 "ADNCS29,Activation Channel Conversion Count Setting Register 29"
|
|
bitfld.byte 0x00 7. " CNTEN58 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT58 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN57 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT57 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x556++0x00
|
|
line.byte 0x00 "ADNCS30,Activation Channel Conversion Count Setting Register 30"
|
|
bitfld.byte 0x00 7. " CNTEN60 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT60 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN59 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT59 ,Conversion count specification bit" "1,2,3,4"
|
|
group.byte 0x557++0x00
|
|
line.byte 0x00 "ADNCS31,Activation Channel Conversion Count Setting Register 31"
|
|
bitfld.byte 0x00 7. " CNTEN62 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " CCNT62 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CNTEN61 ,Conversion count specification scan conversion execution enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CCNT61 ,Conversion count specification bit" "1,2,3,4"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ADPRTF0,Data Protection Status Flag Register 0"
|
|
bitfld.long 0x00 31. " PRTF_[31] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
elif cpuis("S6J311?HAA")
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ADPRTF0,Data Protection Status Flag Register 0"
|
|
bitfld.long 0x00 31. " PRTF_[31] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x158++0x03
|
|
line.long 0x00 "ADPRTF0,Data Protection Status Flag Register 0"
|
|
bitfld.long 0x00 31. " PRTF_[31] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
rgroup.long 0x558++0x03
|
|
line.long 0x00 "ADPRTF1_00,Data Protection Status Flag Register 1"
|
|
bitfld.long 0x00 31. " PRTF_[63] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [62] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [58] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [54] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [53] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [49] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [45] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [44] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
elif cpuis("S6J311?HAA")
|
|
rgroup.long 0x558++0x03
|
|
line.long 0x00 "ADPRTF1_00,Data Protection Status Flag Register 1"
|
|
bitfld.long 0x00 30. " PRTF_[62] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [58] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [54] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [53] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [49] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [45] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [44] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.long 0x558++0x03
|
|
line.long 0x00 "ADPRTF1_00,Data Protection Status Flag Register 1"
|
|
bitfld.long 0x00 30. " PRTF_[62] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [61] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [60] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [59] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [57] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [56] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [55] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [52] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [51] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [50] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [49] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [48] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [47] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [46] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [42] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [41] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [40] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [38] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [37] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [36] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [34] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [33] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [32] ,Data Protection Status Flag Register" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "ADEOCF0,Activation Channel Conversion Completion Flag Register 0"
|
|
bitfld.long 0x00 31. " EOCF_[31] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " [30] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [29] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [28] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " [26] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " [25] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [24] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " [22] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " [21] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [20] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " [18] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " [17] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " [16] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " [14] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " [13] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " [12] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " [10] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [9] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " [8] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " [6] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " [5] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " [4] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " [2] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " [1] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " [0] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
elif cpuis("S6J311?HAA")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "ADEOCF0,Activation Channel Conversion Completion Flag Register 0"
|
|
bitfld.long 0x00 31. " EOCF_[31] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " [30] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [29] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [28] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [24] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " [23] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " [22] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [20] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 19. " [19] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " [18] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " [15] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " [14] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " [13] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " [10] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [9] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " [6] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 3. " [3] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " [2] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " [1] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "ADEOCF0,Activation Channel Conversion Completion Flag Register 0"
|
|
bitfld.long 0x00 31. " EOCF_[31] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " [30] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [29] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [28] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [24] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " [23] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " [22] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [20] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 19. " [19] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " [18] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " [15] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " [14] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " [13] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " [10] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [9] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " [6] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 3. " [3] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "ADEOCF1,Activation Channel Conversion Completion Flag Register 1"
|
|
bitfld.long 0x00 31. " EOCF_[63] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 30. " [62] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [61] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [60] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 26. " [58] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " [57] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [56] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 22. " [54] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " [53] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [52] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " [50] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " [49] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " [48] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " [46] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " [45] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " [44] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " [42] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [41] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " [40] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " [38] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " [37] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " [36] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " [34] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " [33] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " [32] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
elif cpuis("S6J311?HAA")
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "ADEOCF1,Activation Channel Conversion Completion Flag Register 1"
|
|
bitfld.long 0x00 30. " EOCF_[62] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [61] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [60] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 27. " [59] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " [57] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [56] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " [55] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [54] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " [53] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [52] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 19. " [51] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [50] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 17. " [49] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " [48] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " [47] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [46] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 13. " [45] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " [44] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 11. " [43] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [42] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [41] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " [40] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 7. " [39] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [38] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " [37] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " [36] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 3. " [35] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [34] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " [33] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " [32] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
elif cpuis("S6J312?HAA")
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "ADEOCF1,Activation Channel Conversion Completion Flag Register 1"
|
|
bitfld.long 0x00 30. " EOCF_[62] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 29. " [61] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 28. " [60] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 27. " [59] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " [57] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " [56] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " [55] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " [52] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 19. " [51] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 18. " [50] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [49] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " [48] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " [47] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 14. " [46] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 10. " [42] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " [41] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " [40] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 6. " [38] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 5. " [37] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " [36] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " [34] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " [33] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " [32] ,Conversion count completion flag bit" "Not completed,Completed"
|
|
endif
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
wgroup.word 0x160++0x01
|
|
line.word 0x00 "ADTCSC0,A/D Activation Trigger Control Status Clear Register 0"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x162++0x01
|
|
line.word 0x00 "ADTCSC1,A/D Activation Trigger Control Status Clear Register 1"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x164++0x01
|
|
line.word 0x00 "ADTCSC2,A/D Activation Trigger Control Status Clear Register 2"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x166++0x01
|
|
line.word 0x00 "ADTCSC3,A/D Activation Trigger Control Status Clear Register 3"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x168++0x01
|
|
line.word 0x00 "ADTCSC4,A/D Activation Trigger Control Status Clear Register 4"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16A++0x01
|
|
line.word 0x00 "ADTCSC5,A/D Activation Trigger Control Status Clear Register 5"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16C++0x01
|
|
line.word 0x00 "ADTCSC6,A/D Activation Trigger Control Status Clear Register 6"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16E++0x01
|
|
line.word 0x00 "ADTCSC7,A/D Activation Trigger Control Status Clear Register 7"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x170++0x01
|
|
line.word 0x00 "ADTCSC8,A/D Activation Trigger Control Status Clear Register 8"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x172++0x01
|
|
line.word 0x00 "ADTCSC9,A/D Activation Trigger Control Status Clear Register 9"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x174++0x01
|
|
line.word 0x00 "ADTCSC10,A/D Activation Trigger Control Status Clear Register 10"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x176++0x01
|
|
line.word 0x00 "ADTCSC11,A/D Activation Trigger Control Status Clear Register 11"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x178++0x01
|
|
line.word 0x00 "ADTCSC12,A/D Activation Trigger Control Status Clear Register 12"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17A++0x01
|
|
line.word 0x00 "ADTCSC13,A/D Activation Trigger Control Status Clear Register 13"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17C++0x01
|
|
line.word 0x00 "ADTCSC14,A/D Activation Trigger Control Status Clear Register 14"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17E++0x01
|
|
line.word 0x00 "ADTCSC15,A/D Activation Trigger Control Status Clear Register 15"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x180++0x01
|
|
line.word 0x00 "ADTCSC16,A/D Activation Trigger Control Status Clear Register 16"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x182++0x01
|
|
line.word 0x00 "ADTCSC17,A/D Activation Trigger Control Status Clear Register 17"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x184++0x01
|
|
line.word 0x00 "ADTCSC18,A/D Activation Trigger Control Status Clear Register 18"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x186++0x01
|
|
line.word 0x00 "ADTCSC19,A/D Activation Trigger Control Status Clear Register 19"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x188++0x01
|
|
line.word 0x00 "ADTCSC20,A/D Activation Trigger Control Status Clear Register 20"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18A++0x01
|
|
line.word 0x00 "ADTCSC21,A/D Activation Trigger Control Status Clear Register 21"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18C++0x01
|
|
line.word 0x00 "ADTCSC22,A/D Activation Trigger Control Status Clear Register 22"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18E++0x01
|
|
line.word 0x00 "ADTCSC23,A/D Activation Trigger Control Status Clear Register 23"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x190++0x01
|
|
line.word 0x00 "ADTCSC24,A/D Activation Trigger Control Status Clear Register 24"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x192++0x01
|
|
line.word 0x00 "ADTCSC25,A/D Activation Trigger Control Status Clear Register 25"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x194++0x01
|
|
line.word 0x00 "ADTCSC26,A/D Activation Trigger Control Status Clear Register 26"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x196++0x01
|
|
line.word 0x00 "ADTCSC27,A/D Activation Trigger Control Status Clear Register 27"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x198++0x01
|
|
line.word 0x00 "ADTCSC28,A/D Activation Trigger Control Status Clear Register 28"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x19A++0x01
|
|
line.word 0x00 "ADTCSC29,A/D Activation Trigger Control Status Clear Register 29"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x19C++0x01
|
|
line.word 0x00 "ADTCSC30,A/D Activation Trigger Control Status Clear Register 30"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x19E++0x01
|
|
line.word 0x00 "ADTCSC31,A/D Activation Trigger Control Status Clear Register 31"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
elif cpuis("S6J312?HAA")
|
|
wgroup.word 0x160++0x01
|
|
line.word 0x00 "ADTCSC3,A/D Activation Trigger Control Status Clear Register 3"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x162++0x01
|
|
line.word 0x00 "ADTCSC4,A/D Activation Trigger Control Status Clear Register 4"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x164++0x01
|
|
line.word 0x00 "ADTCSC5,A/D Activation Trigger Control Status Clear Register 5"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x166++0x01
|
|
line.word 0x00 "ADTCSC6,A/D Activation Trigger Control Status Clear Register 6"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x168++0x01
|
|
line.word 0x00 "ADTCSC7,A/D Activation Trigger Control Status Clear Register 7"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16A++0x01
|
|
line.word 0x00 "ADTCSC8,A/D Activation Trigger Control Status Clear Register 8"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16C++0x01
|
|
line.word 0x00 "ADTCSC9,A/D Activation Trigger Control Status Clear Register 9"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x16E++0x01
|
|
line.word 0x00 "ADTCSC10,A/D Activation Trigger Control Status Clear Register 10"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x170++0x01
|
|
line.word 0x00 "ADTCSC11,A/D Activation Trigger Control Status Clear Register 11"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x172++0x01
|
|
line.word 0x00 "ADTCSC12,A/D Activation Trigger Control Status Clear Register 12"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x174++0x01
|
|
line.word 0x00 "ADTCSC13,A/D Activation Trigger Control Status Clear Register 13"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x176++0x01
|
|
line.word 0x00 "ADTCSC14,A/D Activation Trigger Control Status Clear Register 14"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x178++0x01
|
|
line.word 0x00 "ADTCSC15,A/D Activation Trigger Control Status Clear Register 15"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17A++0x01
|
|
line.word 0x00 "ADTCSC16,A/D Activation Trigger Control Status Clear Register 16"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17C++0x01
|
|
line.word 0x00 "ADTCSC17,A/D Activation Trigger Control Status Clear Register 17"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x17E++0x01
|
|
line.word 0x00 "ADTCSC18,A/D Activation Trigger Control Status Clear Register 18"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x180++0x01
|
|
line.word 0x00 "ADTCSC19,A/D Activation Trigger Control Status Clear Register 19"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x182++0x01
|
|
line.word 0x00 "ADTCSC20,A/D Activation Trigger Control Status Clear Register 20"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x184++0x01
|
|
line.word 0x00 "ADTCSC21,A/D Activation Trigger Control Status Clear Register 21"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x186++0x01
|
|
line.word 0x00 "ADTCSC22,A/D Activation Trigger Control Status Clear Register 22"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x188++0x01
|
|
line.word 0x00 "ADTCSC23,A/D Activation Trigger Control Status Clear Register 23"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18A++0x01
|
|
line.word 0x00 "ADTCSC24,A/D Activation Trigger Control Status Clear Register 24"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18C++0x01
|
|
line.word 0x00 "ADTCSC25,A/D Activation Trigger Control Status Clear Register 25"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x18E++0x01
|
|
line.word 0x00 "ADTCSC26,A/D Activation Trigger Control Status Clear Register 26"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x190++0x01
|
|
line.word 0x00 "ADTCSC27,A/D Activation Trigger Control Status Clear Register 27"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x192++0x01
|
|
line.word 0x00 "ADTCSC28,A/D Activation Trigger Control Status Clear Register 28"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x194++0x01
|
|
line.word 0x00 "ADTCSC29,A/D Activation Trigger Control Status Clear Register 29"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x196++0x01
|
|
line.word 0x00 "ADTCSC30,A/D Activation Trigger Control Status Clear Register 30"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x198++0x01
|
|
line.word 0x00 "ADTCSC31,A/D Activation Trigger Control Status Clear Register 31"
|
|
bitfld.word 0x00 15. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 14. " INTC ,INT clear bit" "No effect,Clear"
|
|
endif
|
|
wgroup.word 0x560++0x01
|
|
line.word 0x00 "ADTCSC32,A/D Activation Trigger Control Status Clear Register 32"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x562++0x01
|
|
line.word 0x00 "ADTCSC33,A/D Activation Trigger Control Status Clear Register 33"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x564++0x01
|
|
line.word 0x00 "ADTCSC34,A/D Activation Trigger Control Status Clear Register 34"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x566++0x01
|
|
line.word 0x00 "ADTCSC35,A/D Activation Trigger Control Status Clear Register 35"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x568++0x01
|
|
line.word 0x00 "ADTCSC36,A/D Activation Trigger Control Status Clear Register 36"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x56A++0x01
|
|
line.word 0x00 "ADTCSC37,A/D Activation Trigger Control Status Clear Register 37"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x56C++0x01
|
|
line.word 0x00 "ADTCSC38,A/D Activation Trigger Control Status Clear Register 38"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x56E++0x01
|
|
line.word 0x00 "ADTCSC39,A/D Activation Trigger Control Status Clear Register 39"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x570++0x01
|
|
line.word 0x00 "ADTCSC40,A/D Activation Trigger Control Status Clear Register 40"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x572++0x01
|
|
line.word 0x00 "ADTCSC41,A/D Activation Trigger Control Status Clear Register 41"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x574++0x01
|
|
line.word 0x00 "ADTCSC42,A/D Activation Trigger Control Status Clear Register 42"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x576++0x01
|
|
line.word 0x00 "ADTCSC43,A/D Activation Trigger Control Status Clear Register 43"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x578++0x01
|
|
line.word 0x00 "ADTCSC44,A/D Activation Trigger Control Status Clear Register 44"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x57A++0x01
|
|
line.word 0x00 "ADTCSC45,A/D Activation Trigger Control Status Clear Register 45"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x57C++0x01
|
|
line.word 0x00 "ADTCSC46,A/D Activation Trigger Control Status Clear Register 46"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x57E++0x01
|
|
line.word 0x00 "ADTCSC47,A/D Activation Trigger Control Status Clear Register 47"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x580++0x01
|
|
line.word 0x00 "ADTCSC48,A/D Activation Trigger Control Status Clear Register 48"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x582++0x01
|
|
line.word 0x00 "ADTCSC49,A/D Activation Trigger Control Status Clear Register 49"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x584++0x01
|
|
line.word 0x00 "ADTCSC50,A/D Activation Trigger Control Status Clear Register 50"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x586++0x01
|
|
line.word 0x00 "ADTCSC51,A/D Activation Trigger Control Status Clear Register 51"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x588++0x01
|
|
line.word 0x00 "ADTCSC52,A/D Activation Trigger Control Status Clear Register 52"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x58A++0x01
|
|
line.word 0x00 "ADTCSC53,A/D Activation Trigger Control Status Clear Register 53"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x58C++0x01
|
|
line.word 0x00 "ADTCSC54,A/D Activation Trigger Control Status Clear Register 54"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x58E++0x01
|
|
line.word 0x00 "ADTCSC55,A/D Activation Trigger Control Status Clear Register 55"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x590++0x01
|
|
line.word 0x00 "ADTCSC56,A/D Activation Trigger Control Status Clear Register 56"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x592++0x01
|
|
line.word 0x00 "ADTCSC57,A/D Activation Trigger Control Status Clear Register 57"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x594++0x01
|
|
line.word 0x00 "ADTCSC58,A/D Activation Trigger Control Status Clear Register 58"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x596++0x01
|
|
line.word 0x00 "ADTCSC59,A/D Activation Trigger Control Status Clear Register 59"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x598++0x01
|
|
line.word 0x00 "ADTCSC60,A/D Activation Trigger Control Status Clear Register 60"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x59A++0x01
|
|
line.word 0x00 "ADTCSC61,A/D Activation Trigger Control Status Clear Register 61"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x59C++0x01
|
|
line.word 0x00 "ADTCSC62,A/D Activation Trigger Control Status Clear Register 62"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
wgroup.word 0x59E++0x01
|
|
line.word 0x00 "ADTCSC63,A/D Activation Trigger Control Status Clear Register 63"
|
|
bitfld.word 0x00 7. " BUSYC ,BUSY clear bit" "No effect,Clear"
|
|
bitfld.word 0x00 6. " INTC ,INT clear bit" "No effect,Clear"
|
|
sif cpuis("S6J311?JAA")||cpuis("S6J311?HAA")
|
|
rgroup.byte 0x1A0++0x00
|
|
line.byte 0x00 "ADRCS0,Range Comparison Status Register 0"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A1++0x00
|
|
line.byte 0x00 "ADRCS1,Range Comparison Status Register 1"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A2++0x00
|
|
line.byte 0x00 "ADRCS2,Range Comparison Status Register 2"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A3++0x00
|
|
line.byte 0x00 "ADRCS3,Range Comparison Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A4++0x00
|
|
line.byte 0x00 "ADRCS4,Range Comparison Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A5++0x00
|
|
line.byte 0x00 "ADRCS5,Range Comparison Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A6++0x00
|
|
line.byte 0x00 "ADRCS6,Range Comparison Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A7++0x00
|
|
line.byte 0x00 "ADRCS7,Range Comparison Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A8++0x00
|
|
line.byte 0x00 "ADRCS8,Range Comparison Status Register 8"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A9++0x00
|
|
line.byte 0x00 "ADRCS9,Range Comparison Status Register 9"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AA++0x00
|
|
line.byte 0x00 "ADRCS10,Range Comparison Status Register 10"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AB++0x00
|
|
line.byte 0x00 "ADRCS11,Range Comparison Status Register 11"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AC++0x00
|
|
line.byte 0x00 "ADRCS12,Range Comparison Status Register 12"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AD++0x00
|
|
line.byte 0x00 "ADRCS13,Range Comparison Status Register 13"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AE++0x00
|
|
line.byte 0x00 "ADRCS14,Range Comparison Status Register 14"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AF++0x00
|
|
line.byte 0x00 "ADRCS15,Range Comparison Status Register 15"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B0++0x00
|
|
line.byte 0x00 "ADRCS16,Range Comparison Status Register 16"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B1++0x00
|
|
line.byte 0x00 "ADRCS17,Range Comparison Status Register 17"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B2++0x00
|
|
line.byte 0x00 "ADRCS18,Range Comparison Status Register 18"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B3++0x00
|
|
line.byte 0x00 "ADRCS19,Range Comparison Status Register 19"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B4++0x00
|
|
line.byte 0x00 "ADRCS20,Range Comparison Status Register 20"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B5++0x00
|
|
line.byte 0x00 "ADRCS21,Range Comparison Status Register 21"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B6++0x00
|
|
line.byte 0x00 "ADRCS22,Range Comparison Status Register 22"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B7++0x00
|
|
line.byte 0x00 "ADRCS23,Range Comparison Status Register 23"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B8++0x00
|
|
line.byte 0x00 "ADRCS24,Range Comparison Status Register 24"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B9++0x00
|
|
line.byte 0x00 "ADRCS25,Range Comparison Status Register 25"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BA++0x00
|
|
line.byte 0x00 "ADRCS26,Range Comparison Status Register 26"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BB++0x00
|
|
line.byte 0x00 "ADRCS27,Range Comparison Status Register 27"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BC++0x00
|
|
line.byte 0x00 "ADRCS28,Range Comparison Status Register 28"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BD++0x00
|
|
line.byte 0x00 "ADRCS29,Range Comparison Status Register 29"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BE++0x00
|
|
line.byte 0x00 "ADRCS30,Range Comparison Status Register 30"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BF++0x00
|
|
line.byte 0x00 "ADRCS31,Range Comparison Status Register 31"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
elif cpuis("S6J312?HAA")
|
|
rgroup.byte 0x1A0++0x00
|
|
line.byte 0x00 "ADRCS3,Range Comparison Status Register 3"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A1++0x00
|
|
line.byte 0x00 "ADRCS4,Range Comparison Status Register 4"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A2++0x00
|
|
line.byte 0x00 "ADRCS5,Range Comparison Status Register 5"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A3++0x00
|
|
line.byte 0x00 "ADRCS6,Range Comparison Status Register 6"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A4++0x00
|
|
line.byte 0x00 "ADRCS7,Range Comparison Status Register 7"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A5++0x00
|
|
line.byte 0x00 "ADRCS8,Range Comparison Status Register 8"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A6++0x00
|
|
line.byte 0x00 "ADRCS9,Range Comparison Status Register 9"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A7++0x00
|
|
line.byte 0x00 "ADRCS10,Range Comparison Status Register 10"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A8++0x00
|
|
line.byte 0x00 "ADRCS11,Range Comparison Status Register 11"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1A9++0x00
|
|
line.byte 0x00 "ADRCS12,Range Comparison Status Register 12"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AA++0x00
|
|
line.byte 0x00 "ADRCS13,Range Comparison Status Register 13"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AB++0x00
|
|
line.byte 0x00 "ADRCS14,Range Comparison Status Register 14"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AC++0x00
|
|
line.byte 0x00 "ADRCS15,Range Comparison Status Register 15"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AD++0x00
|
|
line.byte 0x00 "ADRCS16,Range Comparison Status Register 16"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AE++0x00
|
|
line.byte 0x00 "ADRCS17,Range Comparison Status Register 17"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1AF++0x00
|
|
line.byte 0x00 "ADRCS18,Range Comparison Status Register 18"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B0++0x00
|
|
line.byte 0x00 "ADRCS19,Range Comparison Status Register 19"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B1++0x00
|
|
line.byte 0x00 "ADRCS20,Range Comparison Status Register 20"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B2++0x00
|
|
line.byte 0x00 "ADRCS21,Range Comparison Status Register 21"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B3++0x00
|
|
line.byte 0x00 "ADRCS22,Range Comparison Status Register 22"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B4++0x00
|
|
line.byte 0x00 "ADRCS23,Range Comparison Status Register 23"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B5++0x00
|
|
line.byte 0x00 "ADRCS24,Range Comparison Status Register 24"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B6++0x00
|
|
line.byte 0x00 "ADRCS25,Range Comparison Status Register 25"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B7++0x00
|
|
line.byte 0x00 "ADRCS26,Range Comparison Status Register 26"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B8++0x00
|
|
line.byte 0x00 "ADRCS27,Range Comparison Status Register 27"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1B9++0x00
|
|
line.byte 0x00 "ADRCS28,Range Comparison Status Register 28"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BA++0x00
|
|
line.byte 0x00 "ADRCS29,Range Comparison Status Register 29"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BB++0x00
|
|
line.byte 0x00 "ADRCS30,Range Comparison Status Register 30"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x1BC++0x00
|
|
line.byte 0x00 "ADRCS31,Range Comparison Status Register 31"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
endif
|
|
rgroup.byte 0x5A0++0x00
|
|
line.byte 0x00 "ADRCS32,Range Comparison Status Register 32"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A1++0x00
|
|
line.byte 0x00 "ADRCS33,Range Comparison Status Register 33"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A2++0x00
|
|
line.byte 0x00 "ADRCS34,Range Comparison Status Register 34"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A3++0x00
|
|
line.byte 0x00 "ADRCS35,Range Comparison Status Register 35"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A4++0x00
|
|
line.byte 0x00 "ADRCS36,Range Comparison Status Register 36"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A5++0x00
|
|
line.byte 0x00 "ADRCS37,Range Comparison Status Register 37"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A6++0x00
|
|
line.byte 0x00 "ADRCS38,Range Comparison Status Register 38"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A7++0x00
|
|
line.byte 0x00 "ADRCS39,Range Comparison Status Register 39"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A8++0x00
|
|
line.byte 0x00 "ADRCS40,Range Comparison Status Register 40"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5A9++0x00
|
|
line.byte 0x00 "ADRCS41,Range Comparison Status Register 41"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AA++0x00
|
|
line.byte 0x00 "ADRCS42,Range Comparison Status Register 42"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AB++0x00
|
|
line.byte 0x00 "ADRCS43,Range Comparison Status Register 43"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AC++0x00
|
|
line.byte 0x00 "ADRCS44,Range Comparison Status Register 44"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AD++0x00
|
|
line.byte 0x00 "ADRCS45,Range Comparison Status Register 45"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AE++0x00
|
|
line.byte 0x00 "ADRCS46,Range Comparison Status Register 46"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5AF++0x00
|
|
line.byte 0x00 "ADRCS47,Range Comparison Status Register 47"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B0++0x00
|
|
line.byte 0x00 "ADRCS48,Range Comparison Status Register 48"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B1++0x00
|
|
line.byte 0x00 "ADRCS49,Range Comparison Status Register 49"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B2++0x00
|
|
line.byte 0x00 "ADRCS50,Range Comparison Status Register 50"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B3++0x00
|
|
line.byte 0x00 "ADRCS51,Range Comparison Status Register 51"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B4++0x00
|
|
line.byte 0x00 "ADRCS52,Range Comparison Status Register 52"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B5++0x00
|
|
line.byte 0x00 "ADRCS53,Range Comparison Status Register 53"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B6++0x00
|
|
line.byte 0x00 "ADRCS54,Range Comparison Status Register 54"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B7++0x00
|
|
line.byte 0x00 "ADRCS55,Range Comparison Status Register 55"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B8++0x00
|
|
line.byte 0x00 "ADRCS56,Range Comparison Status Register 56"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5B9++0x00
|
|
line.byte 0x00 "ADRCS57,Range Comparison Status Register 57"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BA++0x00
|
|
line.byte 0x00 "ADRCS58,Range Comparison Status Register 58"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BB++0x00
|
|
line.byte 0x00 "ADRCS59,Range Comparison Status Register 59"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BC++0x00
|
|
line.byte 0x00 "ADRCS60,Range Comparison Status Register 60"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BD++0x00
|
|
line.byte 0x00 "ADRCS61,Range Comparison Status Register 61"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BE++0x00
|
|
line.byte 0x00 "ADRCS62,Range Comparison Status Register 62"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
rgroup.byte 0x5BF++0x00
|
|
line.byte 0x00 "ADRCS63,Range Comparison Status Register 63"
|
|
bitfld.byte 0x00 5.--7. " RCOCDS ,Continuous detection count status display bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " RCOIRSS ,RCOIRS set value display bit" "Outside range,Inside range"
|
|
bitfld.byte 0x00 3. " RCOIES ,RCOIE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " RCOES ,RCOE set value display bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " RCOTSS ,RCOTS set value display bits" "0,1,2,3"
|
|
textline " "
|
|
sif cpuis("S6J311?JAA")
|
|
wgroup.long 0x1C0++0x03
|
|
line.long 0x00 "ADRCIFC0_00,Range Comparison Flag Clear Register 0"
|
|
bitfld.long 0x00 31. " RCINTC_[31] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [26] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [25] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [23] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [21] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [19] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [17] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [16] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [15] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [12] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [11] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [8] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,RCINT clear bits" "No effect,Clear"
|
|
elif cpuis("S6J311?HAA")
|
|
wgroup.long 0x1C0++0x03
|
|
line.long 0x00 "ADRCIFC0_00,Range Comparison Flag Clear Register 0"
|
|
bitfld.long 0x00 31. " RCINTC_[31] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 23. " [23] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,RCINT clear bits" "No effect,Clear"
|
|
elif cpuis("S6J312?HAA")
|
|
wgroup.long 0x1C0++0x03
|
|
line.long 0x00 "ADRCIFC0_00,Range Comparison Flag Clear Register 0"
|
|
bitfld.long 0x00 31. " RCINTC_[31] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [30] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [29] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [28] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [27] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [24] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 23. " [23] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [22] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [21] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [20] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [19] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [18] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [17] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [15] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [14] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [13] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [10] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [9] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [3] ,RCINT clear bits" "No effect,Clear"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
wgroup.long 0x5C0++0x03
|
|
line.long 0x00 "ADRCIFC1,Range Comparison Flag Clear Register 1"
|
|
bitfld.long 0x00 31. " RCINTC_[63] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 30. " [62] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [61] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [60] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 27. " [59] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 26. " [58] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [57] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [56] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " [55] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 22. " [54] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [53] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [52] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " [51] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [50] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [49] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [48] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " [47] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [46] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [45] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [44] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [42] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [41] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [40] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [38] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [37] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [36] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [34] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [33] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [32] ,RCINT clear bits" "No effect,Clear"
|
|
elif cpuis("S6J311?HAA")
|
|
wgroup.long 0x5C0++0x03
|
|
line.long 0x00 "ADRCIFC1,Range Comparison Flag Clear Register 1"
|
|
bitfld.long 0x00 30. " RCINTC_[62] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [61] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [60] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 27. " [59] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [57] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [56] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 23. " [55] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " [54] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 21. " [53] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [52] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [51] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 18. " [50] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 17. " [49] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [48] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [47] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " [46] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 13. " [45] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 12. " [44] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 11. " [43] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " [42] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [41] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [40] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 7. " [39] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [38] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [37] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [36] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 3. " [35] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " [34] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [33] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [32] ,RCINT clear bits" "No effect,Clear"
|
|
elif cpuis("S6J312?HAA")
|
|
wgroup.long 0x5C0++0x03
|
|
line.long 0x00 "ADRCIFC1,Range Comparison Flag Clear Register 1"
|
|
bitfld.long 0x00 30. " RCINTC_[62] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 29. " [61] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 28. " [60] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 27. " [59] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 26. " [58] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 25. " [57] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 24. " [56] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 23. " [55] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 21. " [53] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 20. " [52] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 19. " [51] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 18. " [50] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " [49] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 16. " [48] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 15. " [47] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 14. " [46] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " [43] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 10. " [42] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 9. " [41] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 8. " [40] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [39] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [38] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [37] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [36] ,RCINT clear bits" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [35] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [34] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [33] ,RCINT clear bits" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [32] ,RCINT clear bits" "No effect,Clear"
|
|
endif
|
|
wgroup.byte 0x1C4++0x00
|
|
line.byte 0x00 "ADSCANSC0,Scan Conversion Control Status Clear Register 0"
|
|
bitfld.byte 0x00 7. " SCINTC ,SCINT clear bit" "No effect,Clear"
|
|
wgroup.byte 0x5C4++0x00
|
|
line.byte 0x00 "ADSCANSC1,Scan Conversion Control Status Clear Register 1"
|
|
bitfld.byte 0x00 7. " SCINTC ,SCINT clear bit" "No effect,Clear"
|
|
width 0x0B
|
|
tree.end
|
|
tree "12-bit A/D Converter Control"
|
|
base ad:0xB4848000
|
|
width 11.
|
|
group.word 0x1C8++0x01
|
|
line.word 0x00 "ADCS0,A/D Control Status Register 0"
|
|
bitfld.word 0x00 15. " BUSY ,A/D conversion in progress bit" "Idle,Busy"
|
|
group.word 0x5C8++0x01
|
|
line.word 0x00 "ADCS1,A/D Control Status Register 1"
|
|
bitfld.word 0x00 15. " BUSY ,A/D conversion in progress bit" "Idle,Busy"
|
|
group.byte 0x1CA++0x00
|
|
line.byte 0x00 "ADCH0,A/D Channel Status Register 0"
|
|
bitfld.byte 0x00 0.--4. " CH ,Analog channel bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x5CA++0x00
|
|
line.byte 0x00 "ADCH1,A/D Channel Status Register 1"
|
|
bitfld.byte 0x00 0.--4. " CH ,Analog channel bits" "32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1CB++0x00
|
|
line.byte 0x00 "ADMD0,A/D Mode Setting Register 0"
|
|
bitfld.byte 0x00 7. " STPCEN ,Sampling time setting per channel enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " CT ,Compare time setting bits" "28 clk cycles,42 clk cycles,56 clk cycles,112 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " ST ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5CB++0x00
|
|
line.byte 0x00 "ADMD1,A/D Mode Setting Register 1"
|
|
bitfld.byte 0x00 7. " STPCEN ,Sampling time setting per channel enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2.--3. " CT ,Compare time setting bits" "28 clk cycles,42 clk cycles,56 clk cycles,112 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " ST ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
sif cpuis("S6J311?JAA")
|
|
group.byte 0x1CC++0x02
|
|
line.byte 0x00 "ADSTPCS0,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH03 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH02 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH01 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH00 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x01 "ADSTPCS1,Sampling Time Setting per A/D Channel Register 1"
|
|
bitfld.byte 0x01 6.--7. " STCH07 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 4.--5. " STCH06 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 2.--3. " STCH05 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 0.--1. " STCH04 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x02 "ADSTPCS2,Sampling Time Setting per A/D Channel Register 2"
|
|
bitfld.byte 0x02 6.--7. " STCH11 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 4.--5. " STCH10 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 2.--3. " STCH09 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 0.--1. " STCH08 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x1CF++0x00
|
|
line.byte 0x00 "ADSTPCS3,Sampling Time Setting per A/D Channel Register 3"
|
|
bitfld.byte 0x00 6.--7. " STCH15 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH14 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH13 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH12 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "ADSTPCS4,Sampling Time Setting per A/D Channel Register 4"
|
|
bitfld.byte 0x00 6.--7. " STCH19 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH18 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH17 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH16 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "ADSTPCS5,Sampling Time Setting per A/D Channel Register 5"
|
|
bitfld.byte 0x00 6.--7. " STCH23 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH22 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH21 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH20 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "ADSTPCS6,Sampling Time Setting per A/D Channel Register 6"
|
|
bitfld.byte 0x00 6.--7. " STCH27 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH26 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH25 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH24 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "ADSTPCS7,Sampling Time Setting per A/D Channel Register 7"
|
|
bitfld.byte 0x00 6.--7. " STCH31 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH30 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH29 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH28 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
elif cpuis("S6J311?HAA")
|
|
group.byte 0x1CC++0x07
|
|
line.byte 0x00 "ADSTPCS0,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH03 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH02 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH01 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH00 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x01 "ADSTPCS1,Sampling Time Setting per A/D Channel Register 1"
|
|
bitfld.byte 0x01 4.--5. " STCH06 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 2.--3. " STCH05 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x02 "ADSTPCS2,Sampling Time Setting per A/D Channel Register 2"
|
|
bitfld.byte 0x02 4.--5. " STCH10 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 2.--3. " STCH09 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x03 "ADSTPCS3,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x03 6.--7. " STCH15 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 4.--5. " STCH14 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 2.--3. " STCH13 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 0.--1. " STCH12 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x04 "ADSTPCS4,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x04 6.--7. " STCH19 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 4.--5. " STCH18 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 2.--3. " STCH17 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x05 "ADSTPCS5,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x05 6.--7. " STCH23 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 4.--5. " STCH22 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 2.--3. " STCH21 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 0.--1. " STCH20 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x06 "ADSTPCS6,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x06 6.--7. " STCH27 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 0.--1. " STCH24 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x07 "ADSTPCS7,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x07 6.--7. " STCH31 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 4.--5. " STCH30 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 2.--3. " STCH29 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 0.--1. " STCH28 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
elif cpuis("S6J312?HAA")
|
|
group.byte 0x1CC++0x07
|
|
line.byte 0x00 "ADSTPCS0,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH03 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x01 "ADSTPCS1,Sampling Time Setting per A/D Channel Register 1"
|
|
bitfld.byte 0x01 4.--5. " STCH06 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 2.--3. " STCH05 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x02 "ADSTPCS2,Sampling Time Setting per A/D Channel Register 2"
|
|
bitfld.byte 0x02 4.--5. " STCH10 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 2.--3. " STCH09 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x03 "ADSTPCS3,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x03 6.--7. " STCH15 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 4.--5. " STCH14 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 2.--3. " STCH13 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 0.--1. " STCH12 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x04 "ADSTPCS4,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x04 6.--7. " STCH19 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 4.--5. " STCH18 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 2.--3. " STCH17 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x05 "ADSTPCS5,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x05 6.--7. " STCH23 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 4.--5. " STCH22 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 2.--3. " STCH21 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 0.--1. " STCH20 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x06 "ADSTPCS6,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x06 6.--7. " STCH27 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 0.--1. " STCH24 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x07 "ADSTPCS7,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x07 6.--7. " STCH31 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 4.--5. " STCH30 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 2.--3. " STCH29 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 0.--1. " STCH28 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
endif
|
|
sif cpuis("S6J311?JAA")
|
|
group.byte 0x5CC++0x00
|
|
line.byte 0x00 "ADSTPCS8,Sampling Time Setting per A/D Channel Register 8"
|
|
bitfld.byte 0x00 6.--7. " STCH35 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH34 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH33 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH32 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5CD++0x00
|
|
line.byte 0x00 "ADSTPCS9,Sampling Time Setting per A/D Channel Register 9"
|
|
bitfld.byte 0x00 6.--7. " STCH39 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH38 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH37 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH36 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5CE++0x00
|
|
line.byte 0x00 "ADSTPCS10,Sampling Time Setting per A/D Channel Register 10"
|
|
bitfld.byte 0x00 6.--7. " STCH43 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH42 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH41 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH40 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5CF++0x00
|
|
line.byte 0x00 "ADSTPCS11,Sampling Time Setting per A/D Channel Register 11"
|
|
bitfld.byte 0x00 6.--7. " STCH47 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH46 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH45 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH44 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5D0++0x00
|
|
line.byte 0x00 "ADSTPCS12,Sampling Time Setting per A/D Channel Register 12"
|
|
bitfld.byte 0x00 6.--7. " STCH51 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH50 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH49 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH48 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5D1++0x00
|
|
line.byte 0x00 "ADSTPCS13,Sampling Time Setting per A/D Channel Register 13"
|
|
bitfld.byte 0x00 6.--7. " STCH55 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH54 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH53 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH52 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5D2++0x00
|
|
line.byte 0x00 "ADSTPCS14,Sampling Time Setting per A/D Channel Register 14"
|
|
bitfld.byte 0x00 6.--7. " STCH59 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH58 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH57 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH56 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
group.byte 0x5D3++0x00
|
|
line.byte 0x00 "ADSTPCS15,Sampling Time Setting per A/D Channel Register 15"
|
|
bitfld.byte 0x00 6.--7. " STCH63 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH62 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH61 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH60 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
elif cpuis("S6J311?HAA")
|
|
group.byte 0x5CC++0x07
|
|
line.byte 0x00 "ADSTPCS8,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH35 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH34 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH33 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH32 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x01 "ADSTPCS9,Sampling Time Setting per A/D Channel Register 1"
|
|
bitfld.byte 0x01 6.--7. " STCH39 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 4.--5. " STCH38 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 2.--3. " STCH37 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 0.--1. " STCH36 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x02 "ADSTPCS10,Sampling Time Setting per A/D Channel Register 2"
|
|
bitfld.byte 0x02 6.--7. " STCH43 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 4.--5. " STCH42 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 2.--3. " STCH41 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 0.--1. " STCH40 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x03 "ADSTPCS11,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x03 6.--7. " STCH47 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 4.--5. " STCH46 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 2.--3. " STCH45 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 0.--1. " STCH44 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x04 "ADSTPCS12,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x04 6.--7. " STCH51 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 4.--5. " STCH50 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 2.--3. " STCH49 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 0.--1. " STCH48 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x05 "ADSTPCS13,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x05 6.--7. " STCH55 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 4.--5. " STCH54 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 2.--3. " STCH53 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 0.--1. " STCH52 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x06 "ADSTPCS14,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x06 6.--7. " STCH59 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 4.--5. " STCH58 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 2.--3. " STCH57 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 0.--1. " STCH56 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x07 "ADSTPCS15,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x07 4.--5. " STCH62 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 2.--3. " STCH61 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 0.--1. " STCH60 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
elif cpuis("S6J312?HAA")
|
|
group.byte 0x5CC++0x07
|
|
line.byte 0x00 "ADSTPCS8,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x00 6.--7. " STCH35 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 4.--5. " STCH34 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 2.--3. " STCH33 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x00 0.--1. " STCH32 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x01 "ADSTPCS9,Sampling Time Setting per A/D Channel Register 1"
|
|
bitfld.byte 0x01 6.--7. " STCH39 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 4.--5. " STCH38 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 2.--3. " STCH37 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x01 0.--1. " STCH36 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x02 "ADSTPCS10,Sampling Time Setting per A/D Channel Register 2"
|
|
bitfld.byte 0x02 6.--7. " STCH43 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 4.--5. " STCH42 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 2.--3. " STCH41 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x02 0.--1. " STCH40 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x03 "ADSTPCS11,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x03 6.--7. " STCH47 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x03 4.--5. " STCH46 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x04 "ADSTPCS12,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x04 6.--7. " STCH51 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 4.--5. " STCH50 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 2.--3. " STCH49 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x04 0.--1. " STCH48 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x05 "ADSTPCS13,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x05 6.--7. " STCH55 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 2.--3. " STCH53 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x05 0.--1. " STCH52 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x06 "ADSTPCS14,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x06 6.--7. " STCH59 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 4.--5. " STCH58 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 2.--3. " STCH57 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x06 0.--1. " STCH56 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
line.byte 0x07 "ADSTPCS15,Sampling Time Setting per A/D Channel Register 0"
|
|
bitfld.byte 0x07 4.--5. " STCH62 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 2.--3. " STCH61 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
bitfld.byte 0x07 0.--1. " STCH60 ,Sampling time setting bits" "12 clk cycles,18 clk cycles,24 clk cycles,48 clk cycles"
|
|
endif
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "ADFDCTR0,Failure Diagnosis Function Control Register"
|
|
bitfld.long 0x00 0.--1. " AVRH0SEL ,AVRH0 voltage input setting bit" "Ordinary A/D conversion,AVRL0,AVRL0,"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "ADFDCTR1,Failure Diagnosis Function Control Register"
|
|
bitfld.long 0x00 0.--1. " AVRH1SEL ,AVRH1 voltage input setting bit" "Ordinary A/D conversion,AVRL0,AVRL0,"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("S6J311?JAA"))
|
|
tree "PWU (Partial Wakeup Control Register)"
|
|
base ad:0xB4848600
|
|
width 6.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PWUC,PWU Control Register"
|
|
bitfld.byte 0x00 7. " PWUE ,PWU mode enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " ADSTS ,A/D conversion start time setting bit" "200 cycles,400 cycles,600 cycles,800 cycles,1000 cycles,1200 cycles,1200 cycles,1200 cycles"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("S6J312?HAA")
|
|
tree "LCDC (LCD CONTROLER)"
|
|
base ad:0xB0641000
|
|
width 8.
|
|
hgroup.byte 0x00++0x00
|
|
hide.byte 0x00 "LCR1,LCDC Control Register 1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "LCR0,LCD Control Register 0"
|
|
bitfld.byte 0x00 7. " CSS ,Clock selection bit" "Main clock,Sub clock"
|
|
bitfld.byte 0x00 6. " LCEN ,PSS Timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " VSEL ,LCD drive power control" "Disconnected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BK ,Blanking selection" "Displayed,Not displayed"
|
|
bitfld.byte 0x00 2.--3. " MS ,Display mode selection" "Stop,1/2 duty,1/3 duty,1/4 duty"
|
|
bitfld.byte 0x00 0.--1. " FP ,Frame cycle" "00,01,10,11"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "LCRS,LCDC Static Control Register"
|
|
bitfld.byte 0x00 7. " SCSS ,Frame cycle generation clock for static drive selection bit" "Main clock,Sub clock"
|
|
bitfld.byte 0x00 6. " LCSEN ,PSS Timer mode (main oscillation operation / sub oscillation operation) operation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--5. " LCS3 ,Static drive selection" "Off,ST0 to ST1,ST0 to ST2,ST0 to ST3,ST0 to ST4,ST0 to ST5,ST0 to ST6,ST0 to ST7,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,ST0 to ST8,"
|
|
bitfld.byte 0x00 0.--1. " FPS1 ,Frame cycle" "00,01,10,11"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "LCDCMR,Common Pin Switching Register"
|
|
bitfld.byte 0x00 7. " DTCH ,Bias selection" "1/3,1/2"
|
|
group.byte 0x04++0x3
|
|
line.byte 0x0 "VRAM3,Data Memory for Display"
|
|
line.byte 0x1 "VRAM2,Data Memory for Display"
|
|
line.byte 0x2 "VRAM1,Data Memory for Display"
|
|
line.byte 0x3 "VRAM0,Data Memory for Display"
|
|
group.byte 0x08++0x3
|
|
line.byte 0x0 "VRAM7,Data Memory for Display"
|
|
line.byte 0x1 "VRAM6,Data Memory for Display"
|
|
line.byte 0x2 "VRAM5,Data Memory for Display"
|
|
line.byte 0x3 "VRAM4,Data Memory for Display"
|
|
group.byte 0x0C++0x3
|
|
line.byte 0x0 "VRAM11,Data Memory for Display"
|
|
line.byte 0x1 "VRAM10,Data Memory for Display"
|
|
line.byte 0x2 "VRAM9,Data Memory for Display"
|
|
line.byte 0x3 "VRAM8,Data Memory for Display"
|
|
group.byte 0x10++0x3
|
|
line.byte 0x0 "VRAM15,Data Memory for Display"
|
|
line.byte 0x1 "VRAM14,Data Memory for Display"
|
|
line.byte 0x2 "VRAM13,Data Memory for Display"
|
|
line.byte 0x3 "VRAM12,Data Memory for Display"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "LDR,Static LCD Display Data Register"
|
|
bitfld.word 0x00 8. " ST8 ,Static output data 8" "0,1"
|
|
bitfld.word 0x00 7. " ST7 ,Static output data 7" "0,1"
|
|
bitfld.word 0x00 6. " ST6 ,Static output data 6" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ST5 ,Static output data 5" "0,1"
|
|
bitfld.word 0x00 4. " ST4 ,Static output data 4" "0,1"
|
|
bitfld.word 0x00 3. " ST3 ,Static output data 3" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ST2 ,Static output data 2" "0,1"
|
|
bitfld.word 0x00 1. " ST1 ,Static output data 1" "0,1"
|
|
bitfld.word 0x00 0. " ST0 ,Static output data 0" "0,1"
|
|
tree "LCDE"
|
|
base ad:0xB0642000
|
|
width 17.
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x00 "LCDE_LCD_KEYCDR,Key Code Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "LCDE_SEGER,Segment Output Register"
|
|
bitfld.long 0x00 31. " SEGE[7] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SEGE[6] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SEGE[5] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SEGE[4] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SEGE[3] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SEGE[2] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SEGE[1] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SEGE[0] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SEGE[15] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SEGE[14] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SEGE[13] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SEGE[12] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SEGE[11] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SEGE[10] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SEGE[9] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SEGE[8] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SEGE[23] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SEGE[22] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SEGE[21] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SEGE[20] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SEGE[19] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SEGE[18] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SEGE[17] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SEGE[16] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SEGE[31] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SEGE[30] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SEGE[29] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEGE[28] ,LCDC segment output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEGE[27] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SEGE[26] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SEGE[25] ,LCDC segment output" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SEGE[24] ,LCDC segment output" "Disabled,Enabled"
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "LCDE_COMVER,Common Output V Pin Control Register"
|
|
bitfld.long 0x00 31. " VE3 ,Use V3 pin as the LCDC V3 reference voltage input" "VCC,V3"
|
|
bitfld.long 0x00 30. " VE2 ,Enable LCDC reference voltage input" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " VE1 ,Enable LCDC reference voltage input" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VE0 ,Enable LCDC reference voltage input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " COME3 ,Enable LCDC common output" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " COME2 ,Enable LCDC common output" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " COME1 ,Enable LCDC common output" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " COME0 ,Enable LCDC common output" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SG (SOUND GENERATOR)"
|
|
tree "SG0"
|
|
base ad:0xB4840000
|
|
width 12.
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840000))&0x800)==0x000)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840000))&0x800)==0x000)&&(((per.w(ad:0xB4840000+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840000))&0x800)==0x800)&&(((per.w(ad:0xB4840000+0x00))&0x201)==(0x01||0x200))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
endif
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SGAR,Amplitude Data Register"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SGFR,Frequency Data Register"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SGNR,Tone Output Number Register"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SGTCR,Time Cycle Register"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SSGIDR,Increase And Decrease Data Register"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SGPCR,PWM Cycle Data Register"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "SGEFR,Extended Frequency Data Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SG1"
|
|
base ad:0xB4840400
|
|
width 12.
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840400))&0x800)==0x000)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840400))&0x800)==0x000)&&(((per.w(ad:0xB4840400+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840400))&0x800)==0x800)&&(((per.w(ad:0xB4840400+0x00))&0x201)==(0x01||0x200))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
endif
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SGAR,Amplitude Data Register"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SGFR,Frequency Data Register"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SGNR,Tone Output Number Register"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SGTCR,Time Cycle Register"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SSGIDR,Increase And Decrease Data Register"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SGPCR,PWM Cycle Data Register"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "SGEFR,Extended Frequency Data Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SG2"
|
|
base ad:0xB4840800
|
|
width 12.
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.word 0x00 8. " EFRE ,Extended frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SGDER,DMA Transfer Update Enable Register"
|
|
bitfld.byte 0x00 7. " ARE1 ,Amplitude data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " ARE0 ,Amplitude data (lower byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " FRE ,Frequency data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 4. " NRE ,Tone output number update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " TCRE ,Time cycle update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " IDRE ,Increase and decrease data update enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.byte 0x00 1. " PCRE1 ,PWM cycle data (upper byte) update enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " PCRE0 ,PWM cycle data (lower byte) update enable bit" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840800))&0x800)==0x000)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x01)==0x01)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
else
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
endif
|
|
newline
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840800))&0x800)==0x000)&&(((per.w(ad:0xB4840800+0x00))&0x201)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
bitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
bitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
elif (((per.w(ad:0xB4840800))&0x800)==0x800)&&(((per.w(ad:0xB4840800+0x00))&0x201)==(0x01||0x200))
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " GID ,Increase/decrease setting bit" "Decreased,Increased"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SGCR,Sound Control Register"
|
|
bitfld.word 0x00 14. " SRST ,Software reset bit" "No effect,Reset"
|
|
rbitfld.word 0x00 13. " DMA ,DMA transfer start interrupt setting enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 11. " GEN ,Automatic increase/decrease enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 9. " BUSY ,Busy status bit" "Inactive,Active"
|
|
rbitfld.word 0x00 8. " TMS ,Tone output mode select" "Normal,Extended"
|
|
newline
|
|
bitfld.word 0x00 6.--7. " S ,Operation clock select bits" "1,2,4,8"
|
|
bitfld.word 0x00 5. " TONE ,Tone output bit" "Mixed signal,Sample square wave"
|
|
bitfld.word 0x00 4. " SGOOE ,SGO signal output enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 3. " SGAOE ,SGA signal output enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " INT ,Interrupt status bit" "Not detected,Detected"
|
|
newline
|
|
bitfld.word 0x00 0. " ST ,Start bit" "Stopped,Started"
|
|
endif
|
|
endif
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SGAR,Amplitude Data Register"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "SGFR,Frequency Data Register"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SGNR,Tone Output Number Register"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "SGTCR,Time Cycle Register"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SSGIDR,Increase And Decrease Data Register"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SGPCR,PWM Cycle Data Register"
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")||cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "SGEFR,Extended Frequency Data Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "SGDMAR,DMA Transfer Intermediate Register"
|
|
wgroup.word 0x10++0x01
|
|
line.word 0x00 "SGCCR,Interrupt Clear Register"
|
|
bitfld.word 0x00 1. " INTC ,Interrupt status clear bit" "No effect,Clear"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "SMC (STEPPER MOTOR CONTROLER)"
|
|
tree "SMC0"
|
|
base ad:0xB48C4000
|
|
width 13.
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
if (((per.w(ad:0xB48C4000))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC0_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC0_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC0_PWC,PWM Control Register"
|
|
bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
if (((per.w(ad:0xB48C4000))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC0_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC0_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4000))&0x04)==0x04)
|
|
if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4000))&0x04)==0x04)
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC0_PWC1,PWM1 Compare Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC0_PWC2,PWM2 Compare Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC0_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4000+0x06))&0x4000)==0x4000)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC0_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC0_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
endif
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC0_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "SMC0_PWSS,PWM Selection Set Register"
|
|
bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set"
|
|
line.word 0x02 "SMC0_PTRGDL,SMC Trigger Delay Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits"
|
|
sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4000))&0x180)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4000))&0x180)==0x80)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4000))&0x180)==0x100)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4000))&0x180)==0x180)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC0_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC1"
|
|
base ad:0xB48C4400
|
|
width 13.
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
if (((per.w(ad:0xB48C4400))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC1_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC1_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC1_PWC,PWM Control Register"
|
|
bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
if (((per.w(ad:0xB48C4400))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC1_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC1_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4400))&0x04)==0x04)
|
|
if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4400))&0x04)==0x04)
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC1_PWC1,PWM1 Compare Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC1_PWC2,PWM2 Compare Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC1_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4400+0x06))&0x4000)==0x4000)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC1_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC1_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
endif
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC1_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "SMC1_PWSS,PWM Selection Set Register"
|
|
bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set"
|
|
line.word 0x02 "SMC1_PTRGDL,SMC Trigger Delay Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits"
|
|
sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4400))&0x180)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4400))&0x180)==0x80)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4400))&0x180)==0x100)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4400))&0x180)==0x180)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC1_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC2"
|
|
base ad:0xB48C4800
|
|
width 13.
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
if (((per.w(ad:0xB48C4800))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC2_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC2_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC2_PWC,PWM Control Register"
|
|
bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
if (((per.w(ad:0xB48C4800))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC2_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC2_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4800))&0x04)==0x04)
|
|
if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4800))&0x04)==0x04)
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC2_PWC1,PWM1 Compare Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC2_PWC2,PWM2 Compare Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC2_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4800+0x06))&0x4000)==0x4000)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC2_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC2_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
endif
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC2_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "SMC2_PWSS,PWM Selection Set Register"
|
|
bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set"
|
|
line.word 0x02 "SMC2_PTRGDL,SMC Trigger Delay Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits"
|
|
sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4800))&0x180)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4800))&0x180)==0x80)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4800))&0x180)==0x100)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4800))&0x180)==0x180)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC2_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMC3"
|
|
base ad:0xB48C4C00
|
|
width 13.
|
|
sif cpuis("S6J323CKS")||cpuis("S6J323CKU")||cpuis("S6J323CLS")||cpuis("S6J323CLU")||cpuis("S6J323CMS")||cpuis("S6J323CMU")||cpuis("S6J324CKS")||cpuis("S6J324CKU")||cpuis("S6J324CLS")||cpuis("S6J324CLU")||cpuis("S6J324CMS")||cpuis("S6J324CMU")||cpuis("S6J325CKS")||cpuis("S6J325CKU")||cpuis("S6J325CLS")||cpuis("S6J325CLU")||cpuis("S6J325CMS")||cpuis("S6J325CMU")||cpuis("S6J326CKS")||cpuis("S6J326CKU")||cpuis("S6J326CLS")||cpuis("S6J326CLU")||cpuis("S6J326CMS")||cpuis("S6J326CMU")||cpuis("S6J327CKS")||cpuis("S6J327CKU")||cpuis("S6J327CLS")||cpuis("S6J327CLU")||cpuis("S6J327CMS")||cpuis("S6J327CMU")||cpuis("S6J328CKS")||cpuis("S6J328CKU")||cpuis("S6J328CLS")||cpuis("S6J328CLU")||cpuis("S6J328CMS")||cpuis("S6J328CMU")||cpuis("S6J32AAKS")||cpuis("S6J32AAKU")||cpuis("S6J32AALS")||cpuis("S6J32AALU")||cpuis("S6J32BAKS")||cpuis("S6J32BAKU")||cpuis("S6J32BALS")||cpuis("S6J32BALU")||cpuis("S6J32CAKS")||cpuis("S6J32CAKU")||cpuis("S6J32CALS")||cpuis("S6J32CALU")||cpuis("S6J32DAKS")||cpuis("S6J32DAKU")||cpuis("S6J32DALS")||cpuis("S6J32DALU")||cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
if (((per.w(ad:0xB48C4C00))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC3_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC3_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC3_PWC,PWM Control Register"
|
|
bitfld.word 0x00 4.--6. 9. " P ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
if (((per.w(ad:0xB48C4C00))&0x200)==0x200)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC3_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12,CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMC3_PWC,PWM Control Register"
|
|
bitfld.word 0x00 9. " P3 ,PWM operating clock prescaler bit" "0,1"
|
|
bitfld.word 0x00 7.--8. " S ,Comparator output sampling clock prescaler bits" "0,1,2,3"
|
|
bitfld.word 0x00 4.--6. " P2_0 ,PWM operating clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6,CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
newline
|
|
bitfld.word 0x00 3. " CE ,Count enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " SC ,Operation mode switching bit" "8-bit,10-bit"
|
|
endif
|
|
endif
|
|
sif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4C00))&0x04)==0x04)
|
|
if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000)
|
|
rgroup.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w(ad:0xB48C4C00))&0x04)==0x04)
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word 0x00 0.--9. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word 0x02 0.--9. 1. " D ,PWM2 compare data value"
|
|
else
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "SMC3_PWC1,PWM1 Compare Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D ,PWM1 compare data value"
|
|
line.word 0x02 "SMC3_PWC2,PWM2 Compare Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,PWM2 compare data value"
|
|
endif
|
|
endif
|
|
sif cpuis("S6J331*")||cpuis("S6J332*")||cpuis("S6J333*")||cpuis("S6J334*")
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC3_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
elif cpuis("s6j336*")||cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4C00+0x06))&0x4000)==0x4000)
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC3_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
rbitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
rbitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC3_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "Low,High,PWM,PWM,Hi-Z,Hi-Z,Hi-Z,Hi-Z"
|
|
endif
|
|
else
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "SMC3_PWS,PWM Selection Register"
|
|
bitfld.word 0x00 14. " BS ,Output update bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 11.--13. " P2 ,Plus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 8.--10. " M2 ,Minus output 2 selection bits" "L,H,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x00 3.--5. " P1 ,Plus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
bitfld.word 0x00 0.--2. " M1 ,Minus output 1 selection bits" "L,H,2,3,4,5,6,7"
|
|
endif
|
|
group.word 0x08++0x03
|
|
line.word 0x00 "SMC3_PWSS,PWM Selection Set Register"
|
|
bitfld.word 0x00 14. " BSS ,Set bit for the Output update bit" "No effect,Set"
|
|
line.word 0x02 "SMC3_PTRGDL,SMC Trigger Delay Register"
|
|
hexmask.word.byte 0x02 0.--7. 1. " D ,Trigger delay bits"
|
|
sif !cpuis("S6J312?HAA")&&!cpuis("S6J323CKS")&&!cpuis("S6J323CKU")&&!cpuis("S6J323CLS")&&!cpuis("S6J323CLU")&&!cpuis("S6J323CMS")&&!cpuis("S6J323CMU")&&!cpuis("S6J324CKS")&&!cpuis("S6J324CKU")&&!cpuis("S6J324CLS")&&!cpuis("S6J324CLU")&&!cpuis("S6J324CMS")&&!cpuis("S6J324CMU")&&!cpuis("S6J325CKS")&&!cpuis("S6J325CKU")&&!cpuis("S6J325CLS")&&!cpuis("S6J325CLU")&&!cpuis("S6J325CMS")&&!cpuis("S6J325CMU")&&!cpuis("S6J326CKS")&&!cpuis("S6J326CKU")&&!cpuis("S6J326CLS")&&!cpuis("S6J326CLU")&&!cpuis("S6J326CMS")&&!cpuis("S6J326CMU")&&!cpuis("S6J327CKS")&&!cpuis("S6J327CKU")&&!cpuis("S6J327CLS")&&!cpuis("S6J327CLU")&&!cpuis("S6J327CMS")&&!cpuis("S6J327CMU")&&!cpuis("S6J328CKS")&&!cpuis("S6J328CKU")&&!cpuis("S6J328CLS")&&!cpuis("S6J328CLU")&&!cpuis("S6J328CMS")&&!cpuis("S6J328CMU")&&!cpuis("S6J32AAKS")&&!cpuis("S6J32AAKU")&&!cpuis("S6J32AALS")&&!cpuis("S6J32AALU")&&!cpuis("S6J32BAKS")&&!cpuis("S6J32BAKU")&&!cpuis("S6J32BALS")&&!cpuis("S6J32BALU")&&!cpuis("S6J32CAKS")&&!cpuis("S6J32CAKU")&&!cpuis("S6J32CALS")&&!cpuis("S6J32CALU")&&!cpuis("S6J32DAKS")&&!cpuis("S6J32DAKU")&&!cpuis("S6J32DALS")&&!cpuis("S6J32DALU")&&!cpuis("S6J331*")&&!cpuis("S6J332*")&&!cpuis("S6J333*")&&!cpuis("S6J334*")&&!cpuis("s6j336*")&&!cpuis("s6j337*")
|
|
if (((per.w(ad:0xB48C4C00))&0x180)==0x00)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP,CLKP/4,CLKP/5,CLKP/6"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4C00))&0x180)==0x80)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/8,CLKP/10,CLKP/12,CLKP/16"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD Operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4C00))&0x180)==0x100)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/2,CLKP/8,CLKP/10,CLKP/12"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
elif (((per.w(ad:0xB48C4C00))&0x180)==0x180)
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SMC3_ZPD,Zero_Position Detection Register"
|
|
bitfld.word 0x00 14.--15. " S ,Comparator output sampling clock prescaler bits" "CLKP/16,CLKP/20,CLKP/24,CLKP/32"
|
|
bitfld.word 0x00 13. " TS ,Sample operation enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10.--12. " T ,Comparator output sampling count selection bits" "Sampling count 1,Sampling count 2,Sampling count 3,Sampling count 4,Sampling count 5,Sampling count 6,Sampling count 7,Sampling count 8"
|
|
newline
|
|
bitfld.word 0x00 9. " PD ,ZPD operation mode switching bit" "Operation mode,Standby mode"
|
|
bitfld.word 0x00 8. " RS ,Detection operation status bit" "No detection,Count exceeded"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SMCTG (Trigger Configuration Of Stepper Motor Controller)"
|
|
base ad:0xB48C5800
|
|
width 14.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SMCTG0_PTRGS,SMC Trigger Selection Register"
|
|
bitfld.word 0x00 13. " S25 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " S24 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " S23 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 10. " S22 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " S21 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " S20 ,Trigger enable for operation of SMC group S2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 5. " S15 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " S14 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " S13 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.word 0x00 2. " S12 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " S11 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " S10 ,Trigger enable for operation of SMC group S1" "Disabled,Enabled"
|
|
wgroup.word 0x02++0x01
|
|
line.word 0x00 "SMCTG0_PTRG,SMC Trigger Register"
|
|
bitfld.word 0x00 1. " TR2 ,SMC trigger 2" "No effect,Select"
|
|
bitfld.word 0x00 0. " TR1 ,SMC trigger 1" "No effect,Select"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|