18224 lines
1.2 MiB
18224 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32C0x On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2025-03-27 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: Generated (TRACE32, build: 178434.), based on:
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; STM32C011.svd (Rev. 1.2), STM32C031.svd (Rev. 1.2),
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; STM32C051.svd (Rev. 1.0), STM32C071.svd (Rev. 1.1),
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; STM32C091.svd (Rev. 1.0), STM32C092.svd (Rev. 1.0)
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; @Core: Cortex-M0+
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; @Chip: STM32C0*
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; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32c0x.per 19317 2025-04-01 12:34:06Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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elif (CORENAME()=="CORTEXM0+")
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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else
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
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bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
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textline " "
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
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textline " "
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abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
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bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
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endif
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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|
else
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|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
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|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40012400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
line.long 0xC "ADC_CFGR1,ADC configuration register 1"
|
|
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
bitfld.long 0xC 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0xC 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
bitfld.long 0xC 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
bitfld.long 0xC 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0xC 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0xC 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0xC 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
bitfld.long 0xC 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0xC 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0xC 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL22),1: Backward scan (from CHSEL22 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
line.long 0x10 "ADC_CFGR2,ADC configuration register 2"
|
|
bitfld.long 0x10 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
bitfld.long 0x10 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift"
|
|
newline
|
|
bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
bitfld.long 0x10 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
line.long 0x14 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x14 30. "SMPSEL22,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 29. "SMPSEL21,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 28. "SMPSEL20,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 27. "SMPSEL19,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
newline
|
|
bitfld.long 0x14 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time use the setting of SMP1[2:0],1: Sampling time use the setting of SMP2[2:0]"
|
|
bitfld.long 0x14 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_MOD0,ADC channel selection register [alternate]"
|
|
bitfld.long 0x0 22. "CHSEL22,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 21. "CHSEL21,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 20. "CHSEL20,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_MOD1,ADC channel selection register [alternate]"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR,ADC channel selection register"
|
|
bitfld.long 0x0 22. "CHSEL22,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 21. "CHSEL21,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 20. "CHSEL20,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_ALTERNATE1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR,ADC channel selection register"
|
|
bitfld.long 0x0 22. "CHSEL22,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 21. "CHSEL21,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 20. "CHSEL20,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_ALTERNATE1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR,ADC channel selection register"
|
|
bitfld.long 0x0 22. "CHSEL22,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 21. "CHSEL21,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 20. "CHSEL20,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_ALTERNATE1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR,ADC channel selection register"
|
|
bitfld.long 0x0 22. "CHSEL22,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 21. "CHSEL21,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 20. "CHSEL20,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x0 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x0 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "ADC_CHSELR_ALTERNATE1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 22. "AWD2CH22,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 21. "AWD2CH21,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 20. "AWD2CH20,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 19. "AWD2CH19,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 22. "AWD3CH22,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 21. "AWD3CH21,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 20. "AWD3CH20,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 19. "AWD3CH19,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
endif
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,CRC data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,CRC independent data register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long 0x4 0.--31. 1. "GPDR,General-purpose 32-bit data register bits"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
|
|
endif
|
|
line.long 0x8 "CRC_CR,CRC control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,CRC initial value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
|
|
line.long 0x4 "CRC_POL,CRC polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
tree.end
|
|
sif (cpuis("STM32C071*"))
|
|
tree "CRS (Clock Recovery System)"
|
|
base ad:0x40006C00
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CRS_CR,CRS control register"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TRIM,HSI48 oscillator smooth trimming"
|
|
bitfld.long 0x0 7. "SWSYNC,Generate software SYNC event" "0: No action,1: A software SYNC event is generated."
|
|
newline
|
|
bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0: Automatic trimming disabled TRIM bits can be..,1: Automatic trimming enabled TRIM bits are.."
|
|
bitfld.long 0x0 5. "CEN,Frequency error counter enable" "0: Frequency error counter disabled,1: Frequency error counter enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt enable" "0: Expected SYNC (ESYNCF) interrupt disabled,1: Expected SYNC (ESYNCF) interrupt enabled"
|
|
bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error interrupt enable" "0: Synchronization or trimming error (ERRF)..,1: Synchronization or trimming error (ERRF).."
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt enable" "0: SYNC warning (SYNCWARNF) interrupt disabled,1: SYNC warning (SYNCWARNF) interrupt enabled"
|
|
bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt enable" "0: SYNC event OK (SYNCOKF) interrupt disabled,1: SYNC event OK (SYNCOKF) interrupt enabled"
|
|
line.long 0x4 "CRS_CFGR,CRS configuration register"
|
|
bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0: SYNC active on rising edge (default),1: SYNC active on falling edge"
|
|
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection" "0: crs_sync_in_1 selected as SYNC signal source,1: crs_sync_in_2 selected as SYNC signal source,2: crs_sync_in_3 selected as SYNC signal source,3: crs_sync_in_4 selected as SYNC signal source"
|
|
newline
|
|
bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider" "0: SYNC not divided (default),1: SYNC divided by 2,2: SYNC divided by 4,3: SYNC divided by 8,4: SYNC divided by 16,5: SYNC divided by 32,6: SYNC divided by 64,7: SYNC divided by 128"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CRS_ISR,CRS interrupt and status register"
|
|
hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture"
|
|
bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0: Up-counting direction the actual frequency is..,1: Down-counting direction the actual frequency is.."
|
|
newline
|
|
bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow" "0: No trimming error signaled,1: Trimming error signaled"
|
|
bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0: No SYNC missed error signaled,1: SYNC missed error signaled"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNCERR,SYNC error" "0: No SYNC error signaled,1: SYNC error signaled"
|
|
bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0: No expected SYNC signaled,1: Expected SYNC signaled"
|
|
newline
|
|
bitfld.long 0x0 2. "ERRF,Error flag" "0: No synchronization or trimming error signaled,1: Synchronization or trimming error signaled"
|
|
bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0: No SYNC warning signaled,1: SYNC warning signaled"
|
|
newline
|
|
bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0: No SYNC event OK signaled,1: SYNC event OK signaled"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CRS_ICR,CRS interrupt flag clear register"
|
|
bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1"
|
|
bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag" "0,1"
|
|
bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "DBG (Debug Support)"
|
|
base ad:0x40015800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBG_IDCODE,DBG device ID code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
newline
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
newline
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
newline
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
endif
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
newline
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBG_IDCODE,DBG device ID code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBG_IDCODE,DBG device ID code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBG_IDCODE,DBG device ID code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBG_IDCODE,DBG device ID code register"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
endif
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x40020000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
sif (cpuis("STM32C051*"))
|
|
rbitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
|
|
rbitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
|
|
newline
|
|
rbitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
rbitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
rbitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
|
|
rbitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rbitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
|
|
newline
|
|
rbitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
|
|
rbitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
|
|
rbitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
rbitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
|
|
rbitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
|
|
newline
|
|
rbitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rbitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
rbitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
|
|
rbitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
rbitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
|
|
newline
|
|
rbitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
|
|
rbitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
|
|
rbitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rbitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
|
|
rbitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
|
|
newline
|
|
rbitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
rbitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
|
|
rbitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
rbitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
|
|
rbitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
rbitfld.long 0x0 11. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred"
|
|
newline
|
|
rbitfld.long 0x0 10. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred"
|
|
rbitfld.long 0x0 9. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred"
|
|
rbitfld.long 0x0 8. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
newline
|
|
rbitfld.long 0x0 7. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred"
|
|
rbitfld.long 0x0 6. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred"
|
|
rbitfld.long 0x0 5. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
rbitfld.long 0x0 4. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
rbitfld.long 0x0 3. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred"
|
|
rbitfld.long 0x0 2. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred"
|
|
newline
|
|
rbitfld.long 0x0 1. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred"
|
|
rbitfld.long 0x0 0. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
line.long 0x4 "DMA_IFCR,DMA interrupt flag clear register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
|
|
bitfld.long 0x4 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
|
|
bitfld.long 0x4 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
|
|
endif
|
|
bitfld.long 0x4 11. "CTEIF3,transfer error flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CHTIF3,half transfer flag clear for channel 3" "0,1"
|
|
bitfld.long 0x4 9. "CTCIF3,transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x4 8. "CGIF3,global interrupt flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CTEIF2,transfer error flag clear for channel 2" "0,1"
|
|
bitfld.long 0x4 6. "CHTIF2,half transfer flag clear for channel 2" "0,1"
|
|
bitfld.long 0x4 5. "CTCIF2,transfer complete flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CGIF2,global interrupt flag clear for channel 2" "0,1"
|
|
bitfld.long 0x4 3. "CTEIF1,transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x4 2. "CHTIF1,half transfer flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CTCIF1,transfer complete flag clear for channel 1" "0,1"
|
|
bitfld.long 0x4 0. "CGIF1,global interrupt flag clear for channel 1" "0,1"
|
|
line.long 0x8 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x8 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x8 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x8 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x8 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x8 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x8 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x8 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x8 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x8 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x8 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0xC "DMA_CNDTR1,DMA channel 1 number of data to transfer register"
|
|
hexmask.long.word 0xC 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)"
|
|
line.long 0x10 "DMA_CPAR1,DMA channel 1 peripheral address register"
|
|
hexmask.long 0x10 0.--31. 1. "PA,peripheral address"
|
|
line.long 0x14 "DMA_CMAR1,DMA channel 1 memory address register"
|
|
hexmask.long 0x14 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR2,DMA channel 2 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)"
|
|
line.long 0x8 "DMA_CPAR2,DMA channel 2 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR2,DMA channel 2 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR3,DMA channel 3 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216 - 1)"
|
|
line.long 0x8 "DMA_CPAR3,DMA channel 3 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR3,DMA channel 3 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
|
|
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
|
|
newline
|
|
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
|
|
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer (0 to 2<sup>16</sup> - 1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
|
|
endif
|
|
tree.end
|
|
tree "DMAMUX (Direct Memory Access Multiplexer)"
|
|
base ad:0x40020800
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel 0 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel 1 configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel 2 configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: No event i.e. no synchronization nor detection.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
endif
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
sif (cpuis("STM32C051*"))
|
|
rbitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rbitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rbitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rbitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
line.long 0x4 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x4 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x4 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x4 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x4 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x4 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel 0 configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel 1 configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel 2 configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel 3 configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "EXTI (Extended Interrupt and Event Controller)"
|
|
base ad:0x40021800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register"
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable line x (x = 15 to 0)" "0: Disable,1: Enable"
|
|
line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register 1"
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line x (x = 15 to 0)." "0: Disable,1: Enable"
|
|
line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register 1"
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
newline
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line x (x = 15 to 0)" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
line.long 0xC "EXTI_RPR1,EXTI rising edge pending register 1"
|
|
bitfld.long 0xC 15. "RPIF15,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 14. "RPIF14,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 13. "RPIF13,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 12. "RPIF12,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 11. "RPIF11,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 10. "RPIF10,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 9. "RPIF9,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 8. "RPIF8,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 7. "RPIF7,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 6. "RPIF6,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 5. "RPIF5,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 4. "RPIF4,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 3. "RPIF3,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 2. "RPIF2,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0xC 1. "RPIF1,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
bitfld.long 0xC 0. "RPIF0,Rising edge event pending for configurable line x (x = 15 to 0)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register 1"
|
|
bitfld.long 0x10 15. "FPIF15,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 14. "FPIF14,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 13. "FPIF13,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 12. "FPIF12,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 11. "FPIF11,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 10. "FPIF10,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 9. "FPIF9,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 8. "FPIF8,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 7. "FPIF7,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 6. "FPIF6,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 5. "FPIF5,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 4. "FPIF4,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 3. "FPIF3,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 2. "FPIF2,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
newline
|
|
bitfld.long 0x10 1. "FPIF1,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
bitfld.long 0x10 0. "FPIF0,Falling edge event pending for configurable line x (x = 15 to 0)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT34,Rising trigger event configuration bit of configurable line 34" "0: Disable,1: Enable"
|
|
line.long 0x4 "EXTI_FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x4 2. "FT34,Falling trigger event configuration bit of configurable line 34." "0: Disable,1: Enable"
|
|
line.long 0x8 "EXTI_SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x8 2. "SWI34,Software rising edge event trigger on line 34" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
line.long 0xC "EXTI_RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0xC 2. "RPIF34,Rising edge event pending for configurable line 34" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
line.long 0x10 "EXTI_FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x10 2. "FPIF34,Falling edge event pending for configurable line 34" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT34,Rising trigger event configuration bit of configurable line 34" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT34,Rising trigger event configuration bit of configurable line 34" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "EXTI_RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT34,Rising trigger event configuration bit of configurable line 34" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "EXTI_FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x0 2. "FT34,Falling trigger event configuration bit of configurable line 34." "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "EXTI_FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x0 2. "FT34,Falling trigger event configuration bit of configurable line 34." "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "EXTI_FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x0 2. "FT34,Falling trigger event configuration bit of configurable line 34." "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EXTI_SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x0 2. "SWI34,Software rising edge event trigger on line 34" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EXTI_SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x0 2. "SWI34,Software rising edge event trigger on line 34" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "EXTI_SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x0 2. "SWI34,Software rising edge event trigger on line 34" "0: No effect,1: Rising edge event generated on the corresponding.."
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "EXTI_RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0x0 2. "RPIF34,Rising edge event pending for configurable line 34" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "EXTI_RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0x0 2. "RPIF34,Rising edge event pending for configurable line 34" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "EXTI_RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0x0 2. "RPIF34,Rising edge event pending for configurable line 34" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EXTI_FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x0 2. "FPIF34,Falling edge event pending for configurable line 34" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EXTI_FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x0 2. "FPIF34,Falling edge event pending for configurable line 34" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EXTI_FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x0 2. "FPIF34,Falling edge event pending for configurable line 34" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
|
|
endif
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTIm GPIO port selection (m = 4 * (x - 1))"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection"
|
|
endif
|
|
line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI2"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI0,EXTIm GPIO port selection (m = 4 * (x - 1))"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection"
|
|
endif
|
|
line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI3"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI2"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI0,EXTIm GPIO port selection (m = 4 * (x - 1))"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection"
|
|
endif
|
|
line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI2"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI1"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI0,EXTIm GPIO port selection (m = 4 * (x - 1))"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection"
|
|
endif
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "EXTI_IMR1,EXTI CPU wakeup with interrupt mask register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x0 31. "IM31,IM31" "0,1"
|
|
bitfld.long 0x0 25. "IM25,IM25" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "IM23,IM23" "0,1"
|
|
bitfld.long 0x0 19. "IM19,IM19" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "IM,CPU wakeup with interrupt mask"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 31. "IM31,CPU wakeup with interrupt mask on line 31" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 31. "IM31,CPU wakeup with interrupt mask on line 31" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 31. "IM31,CPU wakeup with interrupt mask on line 31" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 31. "IM31,CPU wakeup with interrupt mask on line 31" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 25. "IM25,CPU wakeup with interrupt mask on line 25" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 25. "IM25,CPU wakeup with interrupt mask on line 25" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 25. "IM25,CPU wakeup with interrupt mask on line 25" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 25. "IM25,CPU wakeup with interrupt mask on line 25" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 23. "IM23,CPU wakeup with interrupt mask on line 23" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 23. "IM23,CPU wakeup with interrupt mask on line 23" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 23. "IM23,CPU wakeup with interrupt mask on line 23" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 23. "IM23,CPU wakeup with interrupt mask on line 23" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on line 19" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on line 19" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on line 19" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on line 19" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
newline
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on line x (x = 15 to 0)" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
endif
|
|
line.long 0x4 "EXTI_EMR1,EXTI CPU wakeup with event mask register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x4 31. "EM31,EM31" "0,1"
|
|
bitfld.long 0x4 25. "EM25,EM25" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EM23,EM23" "0,1"
|
|
bitfld.long 0x4 19. "EM19,EM19" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "EM,CPU wakeup with event generation mask"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 31. "EM31,CPU wakeup with event generation mask on line 31" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 31. "EM31,CPU wakeup with event generation mask on line 31" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 31. "EM31,CPU wakeup with event generation mask on line 31" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 31. "EM31,CPU wakeup with event generation mask on line 31" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 25. "EM25,CPU wakeup with event generation mask on line 25" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 25. "EM25,CPU wakeup with event generation mask on line 25" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 25. "EM25,CPU wakeup with event generation mask on line 25" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 25. "EM25,CPU wakeup with event generation mask on line 25" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 23. "EM23,CPU wakeup with event generation mask on line 23" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 23. "EM23,CPU wakeup with event generation mask on line 23" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 23. "EM23,CPU wakeup with event generation mask on line 23" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 23. "EM23,CPU wakeup with event generation mask on line 23" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event generation mask on line 19" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event generation mask on line 19" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event generation mask on line 19" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event generation mask on line 19" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
newline
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event generation mask on line x (x = 15 to 0)" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "EXTI_IMR2,EXTI CPU wakeup with interrupt mask register 2"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on line 34" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
line.long 0x4 "EXTI_EMR2,EXTI CPU wakeup with event mask register 2"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event generation mask on line 34" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "EXTI_IMR2,EXTI CPU wakeup with interrupt mask register 2"
|
|
bitfld.long 0x0 4. "IM36,CPU wake-up with interrupt mask on line 36" "0: wake-up with interrupt masked,1: wake-up with interrupt unmasked"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on line 34" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
line.long 0x4 "EXTI_EMR2,EXTI CPU wakeup with event mask register 2"
|
|
bitfld.long 0x4 4. "EM36,CPU wake-up with event generation mask on line 36" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event generation mask on line 34" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "EXTI_IMR2,EXTI CPU wakeup with interrupt mask register 2"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on line 34" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
line.long 0x4 "EXTI_EMR2,EXTI CPU wakeup with event mask register 2"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event generation mask on line 34" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "EXTI_IMR2,EXTI CPU wakeup with interrupt mask register 2"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on line 34" "0: wakeup with interrupt masked,1: wakeup with interrupt unmasked"
|
|
line.long 0x4 "EXTI_EMR2,EXTI CPU wakeup with event mask register 2"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event generation mask on line 34" "0: wakeup with event generation masked,1: wakeup with event generation unmasked"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32C092*"))
|
|
tree "FDCAN (FD Controller Area Network)"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX=0),1: The CAN bus is recessive (FDCANx_RX=1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop-back mode" "0: Reset value loop-back mode is disabled,1: Loop-back mode is enabled (see Power-down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non-ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,Transmit pause enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tless thansub>qless.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation FDCAN_TEST holds reset values,1: Test mode write access to FDCAN_TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN can be set in power-down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted operation mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was cleared by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus-off status" "0: The FDCAN is not in bus-off state.,1: The FDCAN is in bus-off state."
|
|
rbitfld.long 0x4 6. "EW,Warning status" "0: Both error counters are below the error-warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the error-active state.,1: The FDCAN is in the error-passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No error occurred since LEC[2:0] has been..,1: Stuff error.,2: Form error.,3: Ack error.,4: Bit1 error.,5: Bit0 error.,6: CRC error.,7: No change."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC[2:0].."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus-off status" "0: Bus-off status unchanged,1: Bus-off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error-warning status unchanged,1: Error-warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error-passive status unchanged,1: Error-passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO new entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus-off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,Bit and line error grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RXFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RXFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,Number of extended filter elements in the list"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,Number of standard filter elements in the list"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
endif
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLASH_ACR,FLASH access control register"
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software enable" "0: Debugger disabled,1: Debugger enabled"
|
|
newline
|
|
bitfld.long 0x0 16. "EMPTY,Main flash memory area empty" "0: Main flash memory area programmed,1: Main flash memory area empty"
|
|
newline
|
|
bitfld.long 0x0 11. "ICRST,CPU Instruction cache reset" "0: CPU Instruction cache is not reset,1: CPU Instruction cache is reset"
|
|
newline
|
|
bitfld.long 0x0 9. "ICEN,CPU Instruction cache enable" "0: CPU Instruction cache is disabled,1: CPU Instruction cache is enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "PRFTEN,CPU Prefetch enable" "0: CPU Prefetch disabled,1: CPU Prefetch enabled"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LATENCY,Flash memory access latency" "0: Zero wait states,1: One wait state,?,?,?,?,?,?"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "FLASH_KEYR,FLASH key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,FLASH key"
|
|
line.long 0x4 "FLASH_OPTKEYR,FLASH option key register"
|
|
hexmask.long 0x4 0.--31. 1. "OPTKEY,Option byte key"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "FLASH_SR,FLASH status register"
|
|
rbitfld.long 0x0 18. "CFGBSY,Programming or erase configuration busy." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 16. "BSY1,Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OPTVERR,Option and Engineering bits loading validity error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "FASTERR,Fast programming error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MISSERR,Fast programming data miss error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PGSERR,Programming sequence error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SIZERR,Size error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PGAERR,Programming alignment error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WRPERR,Write protection error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PROGERR,Programming error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OPERR,Operation error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
|
|
line.long 0x4 "FLASH_CR,FLASH control register"
|
|
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection enable" "0: Disable (securable area accessible),1: Enable (securable area not accessible)"
|
|
newline
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,Option byte load launch" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 24. "EOPIE,End-of-operation interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 18. "FSTPG,Fast programming enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 17. "OPTSTRT,Start of modification of option bytes" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "STRT,Start erase operation" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x4 3.--6. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number selection"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PER,Page erase enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x4 0. "PG,Flash memory programming enable" "0: Disable,1: Enable"
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "FLASH_OPTR,FLASH option register"
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable bit" "0: Internal resets are propagated as simple pulse..,1: Internal resets drives NRST pin low until it is.."
|
|
newline
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST pin configuration" "?,1: Reset input only: a low level on the NRST pin..,2: Standard GPIO: only internal RESET is possible,3: Bidirectional reset: the NRST pin is configured.."
|
|
newline
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*")||cpuis("STM32C051*"))
|
|
bitfld.long 0x0 26. "NBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1"
|
|
newline
|
|
bitfld.long 0x0 25. "NBOOT1,Boot configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NBOOT_SEL,BOOT0 signal source selection" "0: BOOT0 pin (legacy mode),1: nBOOT0 option bit"
|
|
newline
|
|
bitfld.long 0x0 15. "NRST_SHDW,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "NRST_STDBY,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NRST_STOP,None" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 26. "nBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1"
|
|
newline
|
|
bitfld.long 0x0 25. "nBOOT1,Boot configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "nBOOT_SEL,BOOT0 signal source selection" "0: BOOT0 pin (legacy mode),1: nBOOT0 option bit"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 26. "NBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1"
|
|
newline
|
|
bitfld.long 0x0 25. "NBOOT1,Boot configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NBOOT_SEL,BOOT0 signal source selection" "0: BOOT0 pin (legacy mode),1: nBOOT0 option bit"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 26. "NBOOT0,nBOOT0 option bit" "0: nBOOT0 = 0,1: nBOOT0 = 1"
|
|
newline
|
|
bitfld.long 0x0 25. "NBOOT1,Boot configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "NBOOT_SEL,BOOT0 signal source selection" "0: BOOT0 pin (legacy mode),1: nBOOT0 option bit"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 23. "SECURE_MUXING_EN,Multiple-bonding security" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 22. "RAM_PARITY_CHECK,SRAM parity check control enable/disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x0 21. "HSE_NOT_REMAPPED,HSE remapping enable/disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog,1: Software window watchdog"
|
|
newline
|
|
bitfld.long 0x0 18. "IWGD_STDBY,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter is frozen in Stop..,1: Independent watchdog counter is running in Stop.."
|
|
newline
|
|
bitfld.long 0x0 16. "IWDG_SW,None" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 15. "nRST_SHDW,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "nRST_STDBY,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "nRST_STOP,None" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 15. "NRST_SHDW,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "NRST_STDBY,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NRST_STOP,None" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 15. "NRST_SHDW,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "NRST_STDBY,None" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NRST_STOP,None" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 11.--12. "BORF_LEV,BOR threshold at falling VDD supply" "0: BOR falling level 1 with threshold around 2.0 V,1: BOR falling level 2 with threshold around 2.2 V,2: BOR falling level 3 with threshold around 2.5 V,3: BOR falling level 4 with threshold around 2.8 V"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "BORR_LEV,BOR threshold at falling VDD supply" "0: BOR rising level 1 with threshold around 2.1 V,1: BOR rising level 2 with threshold around 2.3 V,2: BOR rising level 3 with threshold around 2.6 V,3: BOR rising level 4 with threshold around 2.9 V"
|
|
newline
|
|
bitfld.long 0x0 8. "BOR_EN,Brown out reset enable" "0: Configurable brown out reset disabled power-on..,1: Configurable brown out reset enabled values of.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDP,Read protection level"
|
|
line.long 0x4 "FLASH_PCROP1ASR,FLASH PCROP area A start address register"
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
endif
|
|
line.long 0x8 "FLASH_PCROP1AER,FLASH PCROP area A end address register"
|
|
bitfld.long 0x8 31. "PCROP_RDP,PCROP area erase upon RDP level regression" "0: The software can only set this bit,1: Erased"
|
|
newline
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x8 0.--5. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x8 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
endif
|
|
line.long 0xC "FLASH_WRP1AR,FLASH WRP area A address register"
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0xC 16.--19. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0xC 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0xC 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0xC 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0xC 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
line.long 0x10 "FLASH_WRP1BR,FLASH WRP area B address register"
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x10 16.--19. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x10 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x10 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x10 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x10 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x10 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x10 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x10 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x10 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x10 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x10 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
line.long 0x14 "FLASH_PCROP1BSR,FLASH PCROP area B start address register"
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x14 0.--5. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x14 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x14 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
endif
|
|
line.long 0x18 "FLASH_PCROP1BER,FLASH PCROP area B end address register"
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x18 0.--5. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x18 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.word 0x18 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x18 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.word 0x18 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.word 0x18 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
endif
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "FLASH_SECR,FLASH security register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user area" "0: Boot based on the pad/option bit configuration,1: Boot forced from Main flash memory"
|
|
newline
|
|
sif (cpuis("STM32C011*"))
|
|
hexmask.long.byte 0x0 0.--4. 1. "SEC_SIZE,Securable memory area size"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "SEC_SIZE,Securable memory area size"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
tree.end
|
|
tree "GPIO (General Purpose I/Os)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "GPIOA"
|
|
base ad:0x50000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOA_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOA_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOA_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOA_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
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bitfld.long 0x0 13. "BS13,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOA_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOA_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "GPIOB"
|
|
base ad:0x50000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOB_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOB_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register"
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOB_IDR,GPIO port input data register"
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bitfld.long 0x0 15. "ID15,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 14. "ID14,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 13. "ID13,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 12. "ID12,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 11. "ID11,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 10. "ID10,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 9. "ID9,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 8. "ID8,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 7. "ID7,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 6. "ID6,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 5. "ID5,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 4. "ID4,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 3. "ID3,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 2. "ID2,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 1. "ID1,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 0. "ID0,Port x input data I/O y (y = 15 to 0)" "0,1"
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group.long 0x14++0x3
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line.long 0x0 "GPIOB_ODR,GPIO port output data register"
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bitfld.long 0x0 15. "OD15,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 14. "OD14,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 13. "OD13,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 12. "OD12,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 11. "OD11,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 10. "OD10,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 9. "OD9,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 8. "OD8,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 7. "OD7,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 6. "OD6,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 5. "OD5,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 4. "OD4,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 3. "OD3,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 2. "OD2,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 1. "OD1,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 0. "OD0,Port output data I/O y (y = 15 to 0)" "0,1"
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wgroup.long 0x18++0x3
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line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register"
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bitfld.long 0x0 31. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 30. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 29. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 28. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 27. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 26. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 25. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 24. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 23. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 22. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 21. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 20. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 19. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 18. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 17. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 16. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 15. "BS15,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 14. "BS14,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 13. "BS13,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 12. "BS12,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 11. "BS11,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 10. "BS10,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 9. "BS9,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 8. "BS8,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 7. "BS7,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 6. "BS6,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 5. "BS5,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 4. "BS4,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 3. "BS3,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 2. "BS2,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 1. "BS1,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 0. "BS0,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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|
group.long 0x1C++0xB
|
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line.long 0x0 "GPIOB_LCKR,GPIO port configuration lock register"
|
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bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
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bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
|
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bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
|
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bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
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bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
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bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
|
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bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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newline
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bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y (y = 0 to 7)"
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hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y (y = 0 to 7)"
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newline
|
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hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y (y = 0 to 7)"
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hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y (y = 0 to 7)"
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newline
|
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hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y (y = 0 to 7)"
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|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y (y = 0 to 7)"
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newline
|
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hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y (y = 0 to 7)"
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hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y (y = 0 to 7)"
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|
line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
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hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
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hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
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hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
newline
|
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bitfld.long 0x0 13. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
bitfld.long 0x0 12. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
newline
|
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bitfld.long 0x0 11. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
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bitfld.long 0x0 9. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
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bitfld.long 0x0 7. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
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bitfld.long 0x0 5. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "GPIOC"
|
|
base ad:0x50000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOC_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOC_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOC_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOC_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOC_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "GPIOD"
|
|
base ad:0x50000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOD_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOD_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOD_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y (y = 15 to 0)" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOD_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y (y = 15 to 0)" "0,1"
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|
bitfld.long 0x0 12. "OD12,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y (y = 15 to 0)" "0,1"
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|
bitfld.long 0x0 4. "OD4,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y (y = 15 to 0)" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y (y = 15 to 0)" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOD_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y (y = 0 to 7)"
|
|
line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "GPIOF"
|
|
base ad:0x50001400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOF_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y (y = 15 to 0)" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOF_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y (y = 15 to 0)" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y (y = 15 to 0)" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register"
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y (y = 15 to 0)" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOF_IDR,GPIO port input data register"
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bitfld.long 0x0 15. "ID15,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 14. "ID14,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 13. "ID13,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 12. "ID12,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 11. "ID11,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 10. "ID10,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 9. "ID9,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 8. "ID8,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 7. "ID7,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 6. "ID6,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 5. "ID5,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 4. "ID4,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 3. "ID3,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 2. "ID2,Port x input data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 1. "ID1,Port x input data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 0. "ID0,Port x input data I/O y (y = 15 to 0)" "0,1"
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group.long 0x14++0x3
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line.long 0x0 "GPIOF_ODR,GPIO port output data register"
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bitfld.long 0x0 15. "OD15,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 14. "OD14,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 13. "OD13,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 12. "OD12,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 11. "OD11,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 10. "OD10,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 9. "OD9,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 8. "OD8,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 7. "OD7,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 6. "OD6,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 5. "OD5,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 4. "OD4,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 3. "OD3,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 2. "OD2,Port output data I/O y (y = 15 to 0)" "0,1"
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newline
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bitfld.long 0x0 1. "OD1,Port output data I/O y (y = 15 to 0)" "0,1"
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bitfld.long 0x0 0. "OD0,Port output data I/O y (y = 15 to 0)" "0,1"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register"
|
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bitfld.long 0x0 31. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 30. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 29. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 28. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 27. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 26. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 25. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 24. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 23. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 22. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 21. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 20. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 19. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 18. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 17. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 16. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 15. "BS15,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 14. "BS14,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 13. "BS13,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 12. "BS12,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 11. "BS11,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 10. "BS10,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 9. "BS9,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 8. "BS8,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 7. "BS7,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 6. "BS6,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 5. "BS5,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 4. "BS4,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 3. "BS3,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 2. "BS2,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 1. "BS1,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y (y = 15 to 0)" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
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line.long 0x0 "GPIOF_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
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bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y (y = 15 to 0)" "0: Port configuration not locked,1: Port configuration locked"
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|
line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y (y = 0 to 7)"
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hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y (y = 0 to 7)"
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newline
|
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hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y (y = 0 to 7)"
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|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y (y = 0 to 7)"
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|
newline
|
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hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y (y = 0 to 7)"
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|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y (y = 0 to 7)"
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newline
|
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hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y (y = 0 to 7)"
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|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y (y = 0 to 7)"
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|
line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
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hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
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hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y (y = 8 to 15)"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y (y = 8 to 15)"
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|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
newline
|
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bitfld.long 0x0 13. "BR13,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
newline
|
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bitfld.long 0x0 11. "BR11,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
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bitfld.long 0x0 9. "BR9,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
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|
newline
|
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bitfld.long 0x0 7. "BR7,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
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bitfld.long 0x0 3. "BR3,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y (y = 15 to 0)" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "GPIOA"
|
|
base ad:0x50000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOA_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOA_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOA_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOA_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOA_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y"
|
|
line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOA_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "GPIOB"
|
|
base ad:0x50000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOB_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOB_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOB_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOB_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOB_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y"
|
|
line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOB_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "GPIOC"
|
|
base ad:0x50000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOC_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOC_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOC_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOC_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOC_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y"
|
|
line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOC_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "GPIOD"
|
|
base ad:0x50000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOD_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOD_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 7. "OT7,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 3. "OT3,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 1. "OT1,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register"
|
|
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
newline
|
|
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
|
|
line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register"
|
|
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
newline
|
|
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "GPIOD_IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "ID15,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "ID14,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ID13,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "ID12,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ID11,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "ID10,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ID9,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "ID8,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ID7,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "ID6,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ID5,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "ID4,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ID3,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "ID2,Port x input data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ID1,Port x input data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "ID0,Port x input data I/O y" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "GPIOD_ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "OD15,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 14. "OD14,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OD13,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 12. "OD12,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OD11,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 10. "OD10,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OD9,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 8. "OD8,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OD7,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 6. "OD6,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OD5,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 4. "OD4,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OD3,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 2. "OD2,Port output data I/O y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OD1,Port output data I/O y" "0,1"
|
|
bitfld.long 0x0 0. "OD0,Port output data I/O y" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register"
|
|
bitfld.long 0x0 31. "BR15,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 30. "BR14,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 29. "BR13,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 28. "BR12,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 27. "BR11,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 26. "BR10,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 25. "BR9,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 24. "BR8,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 23. "BR7,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 22. "BR6,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 20. "BR4,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 19. "BR3,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 18. "BR2,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 17. "BR1,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
bitfld.long 0x0 16. "BR0,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 15. "BS15,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 14. "BS14,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BS13,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 12. "BS12,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 10. "BS10,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BS9,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 8. "BS8,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BS7,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 6. "BS6,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BS5,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 4. "BS4,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BS3,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 2. "BS2,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOD_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y"
|
|
line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOD_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "GPIOF"
|
|
base ad:0x50001400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "GPIOF_MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "MODE11,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "MODE9,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "MODE7,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 12.--13. "MODE6,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODE5,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 8.--9. "MODE4,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MODE3,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 4.--5. "MODE2,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "MODE1,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
bitfld.long 0x0 0.--1. "MODE0,Port x configuration for I/O y" "0: Input,1: Output,2: Alternate function,3: Analog"
|
|
line.long 0x4 "GPIOF_OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 13. "OT13,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 11. "OT11,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
|
|
newline
|
|
bitfld.long 0x4 9. "OT9,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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|
bitfld.long 0x4 8. "OT8,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 7. "OT7,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 6. "OT6,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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newline
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bitfld.long 0x4 5. "OT5,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 4. "OT4,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
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bitfld.long 0x4 3. "OT3,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 2. "OT2,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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|
newline
|
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bitfld.long 0x4 1. "OT1,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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bitfld.long 0x4 0. "OT0,Port x configuration for I/O y" "0: Output push-pull (reset state),1: Output open-drain"
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|
line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register"
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bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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newline
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bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration for I/O y" "0: Very low speed,1: Low speed,2: High speed,3: Very high speed"
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line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register"
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bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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newline
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bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
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rgroup.long 0x10++0x3
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line.long 0x0 "GPIOF_IDR,GPIO port input data register"
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bitfld.long 0x0 15. "ID15,Port x input data I/O y" "0,1"
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bitfld.long 0x0 14. "ID14,Port x input data I/O y" "0,1"
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newline
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bitfld.long 0x0 13. "ID13,Port x input data I/O y" "0,1"
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bitfld.long 0x0 12. "ID12,Port x input data I/O y" "0,1"
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newline
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bitfld.long 0x0 11. "ID11,Port x input data I/O y" "0,1"
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bitfld.long 0x0 10. "ID10,Port x input data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 9. "ID9,Port x input data I/O y" "0,1"
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bitfld.long 0x0 8. "ID8,Port x input data I/O y" "0,1"
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newline
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bitfld.long 0x0 7. "ID7,Port x input data I/O y" "0,1"
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bitfld.long 0x0 6. "ID6,Port x input data I/O y" "0,1"
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newline
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bitfld.long 0x0 5. "ID5,Port x input data I/O y" "0,1"
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bitfld.long 0x0 4. "ID4,Port x input data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 3. "ID3,Port x input data I/O y" "0,1"
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bitfld.long 0x0 2. "ID2,Port x input data I/O y" "0,1"
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newline
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bitfld.long 0x0 1. "ID1,Port x input data I/O y" "0,1"
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bitfld.long 0x0 0. "ID0,Port x input data I/O y" "0,1"
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group.long 0x14++0x3
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line.long 0x0 "GPIOF_ODR,GPIO port output data register"
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bitfld.long 0x0 15. "OD15,Port output data I/O y" "0,1"
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|
bitfld.long 0x0 14. "OD14,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 13. "OD13,Port output data I/O y" "0,1"
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|
bitfld.long 0x0 12. "OD12,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 11. "OD11,Port output data I/O y" "0,1"
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bitfld.long 0x0 10. "OD10,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 9. "OD9,Port output data I/O y" "0,1"
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|
bitfld.long 0x0 8. "OD8,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 7. "OD7,Port output data I/O y" "0,1"
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bitfld.long 0x0 6. "OD6,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 5. "OD5,Port output data I/O y" "0,1"
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bitfld.long 0x0 4. "OD4,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 3. "OD3,Port output data I/O y" "0,1"
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bitfld.long 0x0 2. "OD2,Port output data I/O y" "0,1"
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newline
|
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bitfld.long 0x0 1. "OD1,Port output data I/O y" "0,1"
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bitfld.long 0x0 0. "OD0,Port output data I/O y" "0,1"
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wgroup.long 0x18++0x3
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line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register"
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bitfld.long 0x0 31. "BR15,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 30. "BR14,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 29. "BR13,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 28. "BR12,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 27. "BR11,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 26. "BR10,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 25. "BR9,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 24. "BR8,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 23. "BR7,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 22. "BR6,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 21. "BR5,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 20. "BR4,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 19. "BR3,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 18. "BR2,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
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bitfld.long 0x0 17. "BR1,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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bitfld.long 0x0 16. "BR0,Port x reset I/O y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 15. "BS15,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 14. "BS14,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 13. "BS13,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 12. "BS12,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 11. "BS11,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 10. "BS10,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 9. "BS9,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 8. "BS8,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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|
newline
|
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bitfld.long 0x0 7. "BS7,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
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bitfld.long 0x0 6. "BS6,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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newline
|
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bitfld.long 0x0 5. "BS5,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 4. "BS4,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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|
newline
|
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bitfld.long 0x0 3. "BS3,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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bitfld.long 0x0 2. "BS2,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
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|
newline
|
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bitfld.long 0x0 1. "BS1,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
bitfld.long 0x0 0. "BS0,Port x set I/O y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "GPIOF_LCKR,GPIO port configuration lock register"
|
|
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
|
|
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
|
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
newline
|
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bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
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|
newline
|
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bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
|
|
line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x pin y"
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|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x pin y"
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|
newline
|
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hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x pin y"
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|
newline
|
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hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x pin y"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x pin y"
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|
newline
|
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hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x pin y"
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hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x pin y"
|
|
line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O y"
|
|
newline
|
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hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O y"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O y"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O y"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "GPIOF_BRR,GPIO port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 14. "BR14,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 13. "BR13,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 12. "BR12,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 11. "BR11,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 10. "BR10,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 9. "BR9,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 8. "BR8,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 7. "BR7,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 6. "BR6,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 4. "BR4,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 3. "BR3,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 2. "BR2,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
newline
|
|
bitfld.long 0x0 1. "BR1,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
bitfld.long 0x0 0. "BR0,Port x reset I/O y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*")||cpuis("STM32C051*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA,8-bit receive data"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,I2C control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disabled.,1: Wake-up from Stop mode enabled."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
line.long 0x4 "I2C_CR2,I2C control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master sends only the first seven bits of.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
|
|
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,I2C own address 2 register"
|
|
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don t care. Only OA2[7:2]..,2: OA2[2:1] are masked and don t care. Only..,3: OA2[3:1] are masked and don t care. Only..,4: OA2[4:1] are masked and don t care. Only..,5: OA2[5:1] are masked and don t care. Only..,6: OA2[6:1] are masked and don t care. Only OA2[7]..,7: OA2[7:1] are masked and don t care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,I2C timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
|
|
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled. hen SCL is low.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/underrun (slave mode)" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer complete reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer complete (master mode)" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received flag" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/underrun flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,I2C PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
|
|
line.long 0x4 "I2C_RXDR,I2C receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,I2C transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,IWDG prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,IWDG reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,IWDG window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value"
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,IWDG key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,IWDG status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "PWR (Power Control)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PWR_CR1,PWR control register 1"
|
|
bitfld.long 0x0 5. "FPD_SLP,Flash memory powered down during Sleep mode" "0: Flash memory idle,1: Flash memory powered down"
|
|
bitfld.long 0x0 3. "FPD_STOP,Flash memory powered down during Stop mode" "0: Flash memory idle,1: Flash memory powered down"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop mode,?,?,3: Standby mode,?,?,?,?"
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PWR_CR2,PWR control register 1"
|
|
bitfld.long 0x0 8.--9. "PVM_VDDIO2,supply voltage monitoring" "0: Monitoring disabled; IOs in isolation mode,1: Monitoring enabled; IOs enabled or in isolation..,2: Monitoring bypassed; IOs enabled,?"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PWR_CR2,PWR control register 1"
|
|
bitfld.long 0x0 8.--9. "PVM_VDDIO2,supply voltage monitoring" "0: Monitoring disabled; IOs in isolation mode,1: Monitoring enabled; IOs enabled or in isolation..,2: Monitoring bypassed; IOs enabled,?"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PWR_CR2,PWR control register 1"
|
|
bitfld.long 0x0 8.--9. "PVM_VDDIO2,supply voltage monitoring" "0: Monitoring disabled; IOs in isolation mode,1: Monitoring enabled; IOs enabled or in isolation..,2: Monitoring bypassed; IOs enabled,?"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PWR_CR2,PWR control register 1"
|
|
bitfld.long 0x0 8.--9. "PVM_VDDIO2,supply voltage monitoring" "0: Monitoring disabled; IOs in isolation mode,1: Monitoring enabled; IOs enabled or in isolation..,2: Monitoring bypassed; IOs enabled,?"
|
|
endif
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "PWR_CR3,PWR control register 3"
|
|
bitfld.long 0x0 15. "EIWUL,Enable internal wakeup line" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 10. "APC,Apply pull-up and pull-down configuration" "0: Not applied,1: Applied"
|
|
newline
|
|
bitfld.long 0x0 5. "EWUP6,Enable WKUP6 wakeup pin" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 4. "EWUP5,Enable WKUP5 wakeup pin" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 4. "EWUP5,Enable WKUP5 wakeup pin" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 4. "EWUP5,Enable WKUP5 wakeup pin" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 4. "EWUP5,Enable WKUP5 wakeup pin" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 3. "EWUP4,Enable WKUP4 wakeup pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EWUP3,Enable WKUP3 wakeup pin" "0,1"
|
|
bitfld.long 0x0 1. "EWUP2,Enable WKUP2 wakeup pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EWUP1,Enable WKUP1 wakeup pin" "0,1"
|
|
line.long 0x4 "PWR_CR4,PWR control register 4"
|
|
bitfld.long 0x4 5. "WP6,WKUP6 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 4. "WP5,WKUP5 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 4. "WP5,WKUP5 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 4. "WP5,WKUP5 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 4. "WP5,WKUP5 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 3. "WP4,WKUP4 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
bitfld.long 0x4 2. "WP3,WKUP3 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
bitfld.long 0x4 1. "WP2,WKUP2 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
newline
|
|
bitfld.long 0x4 0. "WP1,WKUP1 wakeup pin polarity" "0: High level or rising edge,1: Low level or falling edge"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "PWR_SR1,PWR status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby/Shutdown flag" "0: The device did not enter Standby or Shutdown mode,1: The device entered Standby or Shutdown mode"
|
|
newline
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
line.long 0x4 "PWR_SR2,PWR status register 2"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 13. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply voltage monitoring output flag" "0: Not ready,1: Ready"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 13. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply voltage monitoring output flag" "0: Not ready,1: Ready"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 13. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply voltage monitoring output flag" "0: Not ready,1: Ready"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 13. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply voltage monitoring output flag" "0: Not ready,1: Ready"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power-down,1: Flash memory ready to be accessed"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "PWR_SCR,PWR status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "PWR_PUCRA,PWR Port A pull-up control register"
|
|
bitfld.long 0x0 15. "PU15,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PU13,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PU11,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PU9,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PU7,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PU3,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PU1,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port A pull-up bit i (i = 15 to 0)" "0,1"
|
|
line.long 0x4 "PWR_PDCRA,PWR Port A pull-down control register"
|
|
bitfld.long 0x4 15. "PD15,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PD13,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "PD11,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "PD9,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PD7,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PD3,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PD1,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port A pull-down bit i (i = 15 to 0)" "0,1"
|
|
line.long 0x8 "PWR_PUCRB,PWR Port B pull-up control register"
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 7. "PU7,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 6. "PU6,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit i" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit i" "0,1"
|
|
endif
|
|
line.long 0xC "PWR_PDCRB,PWR Port B pull-down control register"
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 7. "PD7,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 6. "PD6,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit i (i = 15 to 0)" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit i" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit i" "0,1"
|
|
endif
|
|
line.long 0x10 "PWR_PUCRC,PWR Port C pull-up control register"
|
|
bitfld.long 0x10 15. "PU15,Port C pull-up bit i (i = 15 to 13 7 to 6)" "0,1"
|
|
bitfld.long 0x10 14. "PU14,Port C pull-up bit i (i = 15 to 13 7 to 6)" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 12. "PU12,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "PU11,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 10. "PU10,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "PU9,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 8. "PU8,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "PU5,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 4. "PU4,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "PU3,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 2. "PU2,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PU1,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 0. "PU0,Port C pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 12. "PU12,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "PU11,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 10. "PU10,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "PU9,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 8. "PU8,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "PU5,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 4. "PU4,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "PU3,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 2. "PU2,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PU1,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 0. "PU0,Port C pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 12. "PU12,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "PU11,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 10. "PU10,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "PU9,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 8. "PU8,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "PU5,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 4. "PU4,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "PU3,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 2. "PU2,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PU1,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 0. "PU0,Port C pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 12. "PU12,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "PU11,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 10. "PU10,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "PU9,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 8. "PU8,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "PU5,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 4. "PU4,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "PU3,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 2. "PU2,Port C pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "PU1,Port C pull-up bit i" "0,1"
|
|
bitfld.long 0x10 0. "PU0,Port C pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit i (i = 15 to 13 7 to 6)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit i (i = 15 to 13 7 to 6)" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit i (i = 15 to 13 7 to 6)" "0,1"
|
|
endif
|
|
line.long 0x14 "PWR_PDCRC,PWR Port C pull-down control register"
|
|
bitfld.long 0x14 15. "PD15,Port C pull-down bit i (i = 15 14 13 7 6)" "0,1"
|
|
bitfld.long 0x14 14. "PD14,Port C pull-down bit i (i = 15 14 13 7 6)" "0,1"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "PD11,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PD9,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "PD5,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "PD3,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "PD1,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Port C pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "PD11,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PD9,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "PD5,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "PD3,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "PD1,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Port C pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "PD11,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PD9,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "PD5,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "PD3,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "PD1,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Port C pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "PD11,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PD9,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "PD5,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "PD3,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Port C pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "PD1,Port C pull-down bit i" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Port C pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit i (i = 15 14 13 7 6)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit i (i = 15 14 13 7 6)" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit i (i = 15 14 13 7 6)" "0,1"
|
|
endif
|
|
line.long 0x18 "PWR_PUCRD,PWR Port D pull-up control register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 9. "PU9,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 8. "PU8,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 9. "PU9,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 8. "PU8,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 9. "PU9,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 8. "PU8,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 9. "PU9,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 8. "PU8,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 6. "PU6,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 5. "PU5,Port D pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "PU4,Port D pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 6. "PU6,Port D pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "PU5,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 4. "PU4,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 6. "PU6,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 5. "PU5,Port D pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "PU4,Port D pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 6. "PU6,Port D pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "PU5,Port D pull-up bit i" "0,1"
|
|
bitfld.long 0x18 4. "PU4,Port D pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 3. "PU3,Port D pull-up bit i (i = 3 to 0)" "0,1"
|
|
bitfld.long 0x18 2. "PU2,Port D pull-up bit i (i = 3 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "PU1,Port D pull-up bit i (i = 3 to 0)" "0,1"
|
|
bitfld.long 0x18 0. "PU0,Port D pull-up bit i (i = 3 to 0)" "0,1"
|
|
line.long 0x1C "PWR_PDCRD,PWR Port D pull-down control register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 5. "PD5,Port D pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "PD5,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 5. "PD5,Port D pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "PD5,Port D pull-down bit i" "0,1"
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x1C 3. "PD3,Port D pull-down bit i (i = 3 to 0)" "0,1"
|
|
bitfld.long 0x1C 2. "PD2,Port D pull-down bit i (i = 3 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "PD1,Port D pull-down bit i (i = 3 to 0)" "0,1"
|
|
bitfld.long 0x1C 0. "PD0,Port D pull-down bit i (i = 3 to 0)" "0,1"
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "PWR_PUCRF,PWR Port F pull-up control register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 3. "PU3,Port F pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 3. "PU3,Port F pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 3. "PU3,Port F pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 3. "PU3,Port F pull-up bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 2. "PU2,Port F pull-up bit i (i = 2 to 0)" "0,1"
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x0 1. "PU1,Port F pull-up bit i (i = 2 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PU0,Port F pull-up bit i (i = 2 to 0)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 1. "PU1,Port F pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PU0,Port F pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 1. "PU1,Port F pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PU0,Port F pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 1. "PU1,Port F pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PU0,Port F pull-up bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 1. "PU1,Port F pull-up bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PU0,Port F pull-up bit i" "0,1"
|
|
endif
|
|
line.long 0x4 "PWR_PDCRF,PWR Port F pull-down control register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 3. "PD3,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 3. "PD3,Port F pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 3. "PD3,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 3. "PD3,Port F pull-down bit i" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 2. "PD2,Port F pull-down bit i (i = 2 to 0)" "0,1"
|
|
sif (cpuis("STM32C031*"))
|
|
bitfld.long 0x4 1. "PD1,Port F pull-down bit i (i = 2 to 0)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PD0,Port F pull-down bit i (i = 2 to 0)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 1. "PD1,Port F pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PD0,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x4 1. "PD1,Port F pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PD0,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x4 1. "PD1,Port F pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PD0,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x4 1. "PD1,Port F pull-down bit i" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "PD0,Port F pull-down bit i" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PWR_SR1,PWR status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter Standby mode,1: The device entered Standby mode"
|
|
newline
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "PWR_SR2,PWR status register 2"
|
|
bitfld.long 0x0 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power-down,1: Flash memory ready to be accessed"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "PWR_SCR,PWR status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "PWR_BKP0R,PWR backup 0 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x4 "PWR_BKP1R,PWR backup 1 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x8 "PWR_BKP2R,PWR backup 2 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0xC "PWR_BKP3R,PWR backup 3 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BKP,Backup bitfield"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PWR_SR1,PWR status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter Standby mode,1: The device entered Standby mode"
|
|
newline
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "PWR_SR2,PWR status register 2"
|
|
bitfld.long 0x0 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power-down,1: Flash memory ready to be accessed"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "PWR_SCR,PWR status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "PWR_BKP0R,PWR backup 0 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x4 "PWR_BKP1R,PWR backup 1 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x8 "PWR_BKP2R,PWR backup 2 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0xC "PWR_BKP3R,PWR backup 3 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BKP,Backup bitfield"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PWR_SR1,PWR status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter Standby mode,1: The device entered Standby mode"
|
|
newline
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "PWR_SR2,PWR status register 2"
|
|
bitfld.long 0x0 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power-down,1: Flash memory ready to be accessed"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "PWR_SCR,PWR status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "PWR_BKP0R,PWR backup 0 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x4 "PWR_BKP1R,PWR backup 1 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x8 "PWR_BKP2R,PWR backup 2 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0xC "PWR_BKP3R,PWR backup 3 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BKP,Backup bitfield"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "PWR_SR1,PWR status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter Standby mode,1: The device entered Standby mode"
|
|
newline
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "PWR_SR2,PWR status register 2"
|
|
bitfld.long 0x0 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power-down,1: Flash memory ready to be accessed"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "PWR_SCR,PWR status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x70++0xF
|
|
line.long 0x0 "PWR_BKP0R,PWR backup 0 register"
|
|
hexmask.long.word 0x0 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x4 "PWR_BKP1R,PWR backup 1 register"
|
|
hexmask.long.word 0x4 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0x8 "PWR_BKP2R,PWR backup 2 register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BKP,Backup bitfield"
|
|
line.long 0xC "PWR_BKP3R,PWR backup 3 register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BKP,Backup bitfield"
|
|
endif
|
|
tree.end
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "RCC_CR,RCC clock control register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 23. "HSIUSB48RDY,HSIUSB48 clock ready flag" "0: Not ready,1: Ready"
|
|
bitfld.long 0x0 22. "HSIUSB48ON,HSIUSB48 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 23. "HSIUSB48RDY,HSIUSB48 clock ready flag" "0: Not ready,1: Ready"
|
|
bitfld.long 0x0 22. "HSIUSB48ON,HSIUSB48 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 23. "HSIUSB48RDY,HSIUSB48 clock ready flag" "0: Not ready,1: Ready"
|
|
bitfld.long 0x0 22. "HSIUSB48ON,HSIUSB48 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 23. "HSIUSB48RDY,HSIUSB48 clock ready flag" "0: Not ready,1: Ready"
|
|
bitfld.long 0x0 22. "HSIUSB48ON,HSIUSB48 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 19. "CSSON,Clock security system enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0: No bypass,1: Bypass"
|
|
newline
|
|
rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: Not ready,1: Ready"
|
|
bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 11.--13. "HSIDIV,HSI48 clock division factor" "0: 1,1: 2,2: 4 (reset value),3: 8,4: 16,5: 32,6: 64,7: 128"
|
|
rbitfld.long 0x0 10. "HSIRDY,HSI48 clock ready flag" "0: Not ready,1: Ready"
|
|
newline
|
|
bitfld.long 0x0 9. "HSIKERON,HSI48 always-enable for peripheral kernels." "0: HSI48 oscillator enable depends on the HSION bit,1: HSI48 oscillator is active in Run and Stop modes"
|
|
bitfld.long 0x0 8. "HSION,HSI48 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "HSIKERDIV,HSI48 kernel clock division factor" "0: 1,1: 2,2: 3 (reset value),3: 4,4: 5,5: 6,6: 7,7: 8"
|
|
bitfld.long 0x0 2.--4. "SYSDIV,System clock division factor" "0: 1,1: 2,2: 3 (reset value),3: 4,4: 5,5: 6,6: 7,7: 8"
|
|
line.long 0x4 "RCC_ICSCR,RCC internal clock source calibration register"
|
|
hexmask.long.byte 0x4 8.--14. 1. "HSITRIM,HSI48 clock trimming"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HSICAL,HSI48 clock calibration"
|
|
line.long 0x8 "RCC_CFGR,RCC clock configuration register"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 12.--14. "PPRE,APB prescaler" "?,?,?,?,4: 2,5: 4,6: 8,7: 16"
|
|
hexmask.long.byte 0x8 8.--11. 1. "HPRE,AHB prescaler"
|
|
newline
|
|
rbitfld.long 0x8 3.--5. "SWS,System clock switch status" "0: HSISYS,1: HSE,?,3: LSI,4: LSE,?,?,?"
|
|
bitfld.long 0x8 0.--2. "SW,System clock switch" "0: HSISYS,1: HSE,?,3: LSI,4: LSE,?,?,?"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSIUSB48CAL,HSIUSB48 clock calibration"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSIUSB48CAL,HSIUSB48 clock calibration"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSIUSB48CAL,HSIUSB48 clock calibration"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "RCC_CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSIUSB48CAL,HSIUSB48 clock calibration"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RCC_CIER,RCC clock interrupt enable register"
|
|
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI16 ready interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYIE,HSIUSB48 ready interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYIE,HSIUSB48 ready interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYIE,HSIUSB48 ready interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYIE,HSIUSB48 ready interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: Iterrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI16 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYF,HSIUSB48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYF,HSIUSB48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYF,HSIUSB48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYF,HSIUSB48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,RCC clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI16 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYC,HSIUSB48 ready interrupt clear" "0: No effect,1: Clear HSIUSB48RDYF flag"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYC,HSIUSB48 ready interrupt clear" "0: No effect,1: Clear HSIUSB48RDYF flag"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYC,HSIUSB48 ready interrupt clear" "0: No effect,1: Clear HSIUSB48RDYF flag"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 2. "HSIUSB48RDYC,HSIUSB48 ready interrupt clear" "0: No effect,1: Clear HSIUSB48RDYF flag"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
|
|
group.long 0x24++0x2F
|
|
line.long 0x0 "RCC_IOPRSTR,RCC I/O port reset register"
|
|
bitfld.long 0x0 5. "GPIOFRST,I/O port F reset" "0: no effect,1: Reset I/O port F"
|
|
bitfld.long 0x0 3. "GPIODRST,I/O port D reset" "0: no effect,1: Reset I/O port D"
|
|
newline
|
|
bitfld.long 0x0 2. "GPIOCRST,I/O port C reset" "0: no effect,1: Reset I/O port C"
|
|
bitfld.long 0x0 1. "GPIOBRST,I/O port B reset" "0: no effect,1: Reset I/O port B"
|
|
newline
|
|
bitfld.long 0x0 0. "GPIOARST,I/O port A reset" "0: no effect,1: Reset I/O port A"
|
|
line.long 0x4 "RCC_AHBRSTR,RCC AHB peripheral reset register"
|
|
bitfld.long 0x4 12. "CRCRST,CRC reset" "0: No effect,1: Reset CRC"
|
|
bitfld.long 0x4 8. "FLASHRST,Flash memory interface reset" "0: No effect,1: Reset Flash memory interface"
|
|
newline
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 and DMAMUX reset" "0: No effect,1: Reset DMA1 and DMAMUX"
|
|
line.long 0x8 "RCC_APBRSTR1,RCC APB peripheral reset register 1"
|
|
bitfld.long 0x8 28. "PWRRST,Power interface reset" "0: No effect,1: Reset PWR"
|
|
bitfld.long 0x8 27. "DBGRST,Debug support reset" "0: No effect,1: Reset DBG"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0: No effect,1: Reset I2C1"
|
|
bitfld.long 0x8 17. "USART2RST,USART2 reset" "0: No effect,1: Reset USART2"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRS reset" "0: No effect,1: Reset CRS"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRS reset" "0: No effect,1: Reset CRS"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRS reset" "0: No effect,1: Reset CRS"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRS reset" "0: No effect,1: Reset CRS"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
|
|
bitfld.long 0x8 13. "USBRST,USB reset" "0: No effect,1: Reset USB"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
|
|
bitfld.long 0x8 13. "USBRST,USB reset" "0: No effect,1: Reset USB"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
|
|
bitfld.long 0x8 13. "USBRST,USB reset" "0: No effect,1: Reset USB"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
|
|
bitfld.long 0x8 13. "USBRST,USB reset" "0: No effect,1: Reset USB"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 1. "TIM3RST,TIM3 timer reset" "0: No effect,1: Reset TIM3"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
|
|
endif
|
|
line.long 0xC "RCC_APBRSTR2,RCC APB peripheral reset register 2"
|
|
bitfld.long 0xC 20. "ADCRST,ADC reset" "0: No effect,1: Reset ADC"
|
|
bitfld.long 0xC 18. "TIM17RST,TIM16 timer reset" "0: No effect,1: Reset TIM17 timer"
|
|
newline
|
|
bitfld.long 0xC 17. "TIM16RST,TIM16 timer reset" "0: No effect,1: Reset TIM16 timer"
|
|
bitfld.long 0xC 15. "TIM14RST,TIM14 timer reset" "0: No effect,1: Reset TIM14 timer"
|
|
newline
|
|
bitfld.long 0xC 14. "USART1RST,USART1 reset" "0: No effect,1: Reset USART1"
|
|
bitfld.long 0xC 12. "SPI1RST,SPI1 reset" "0: No effect,1: Reset SPI1"
|
|
newline
|
|
bitfld.long 0xC 11. "TIM1RST,TIM1 timer reset" "0: No effect,1: Reset TIM1 timer"
|
|
bitfld.long 0xC 0. "SYSCFGRST,SYSCFG reset" "0: No effect,1: Reset SYSCFG"
|
|
line.long 0x10 "RCC_IOPENR,RCC I/O port clock enable register"
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable" "0: Disable,1: Enable"
|
|
line.long 0x14 "RCC_AHBENR,RCC AHB peripheral clock enable register"
|
|
bitfld.long 0x14 12. "CRCEN,CRC clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x14 8. "FLASHEN,Flash memory interface clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 and DMAMUX clock enable" "0: Disable,1: Enable"
|
|
line.long 0x18 "RCC_APBENR1,RCC APB peripheral clock enable register 1"
|
|
bitfld.long 0x18 28. "PWREN,Power interface clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 27. "DBGEN,Debug support clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 21. "I2C1EN,I2C1 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 17. "USART2EN,USART2 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRS clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRS clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRS clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRS clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 13. "USBEN,USB clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 13. "USBEN,USB clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 13. "USBEN,USB clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 13. "USBEN,USB clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 11. "WWDGEN,WWDG clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x18 10. "RTCAPBEN,RTC APB clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x18 1. "TIM3EN,TIM3 timer clock enable" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0: Disable,1: Enable"
|
|
endif
|
|
line.long 0x1C "RCC_APBENR2,RCC APB peripheral clock enable register 2"
|
|
bitfld.long 0x1C 20. "ADCEN,ADC clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x1C 18. "TIM17EN,TIM16 timer clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x1C 17. "TIM16EN,TIM16 timer clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x1C 15. "TIM14EN,TIM14 timer clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x1C 14. "USART1EN,USART1 clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x1C 12. "SPI1EN,SPI1 clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x1C 11. "TIM1EN,TIM1 timer clock enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x1C 0. "SYSCFGEN,SYSCFG clock enable" "0: Disable,1: Enable"
|
|
line.long 0x20 "RCC_IOPSMENR,RCC I/O port in Sleep mode clock enable register"
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
line.long 0x24 "RCC_AHBSMENR,RCC AHB peripheral clock enable in Sleep/Stop mode register"
|
|
bitfld.long 0x24 12. "CRCSMEN,CRC clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x24 9. "SRAMSMEN,SRAM clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x24 8. "FLASHSMEN,Flash memory interface clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 and DMAMUX clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
line.long 0x28 "RCC_APBSMENR1,RCC APB peripheral clock enable in Sleep/Stop mode register 1"
|
|
bitfld.long 0x28 28. "PWRSMEN,Power interface clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 27. "DBGSMEN,Debug support clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x28 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x28 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x28 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x28 22. "I2C2SMEN,I2C2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x28 21. "I2C1SMEN,I2C1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 17. "USART2SMEN,USART2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x28 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x28 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x28 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x28 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x28 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x28 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x28 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x28 14. "SPI2SMEN,SPI2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x28 11. "WWDGSMEN,WWDG clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x28 10. "RTCAPBSMEN,RTC APB clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x28 1. "TIM3SMEN,TIM3 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
endif
|
|
line.long 0x2C "RCC_APBSMENR2,RCC APB peripheral clock enable in Sleep/Stop mode register 2"
|
|
bitfld.long 0x2C 20. "ADCSMEN,ADC clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x2C 18. "TIM17SMEN,TIM16 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x2C 17. "TIM16SMEN,TIM16 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x2C 15. "TIM14SMEN,TIM14 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x2C 14. "USART1SMEN,USART1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
bitfld.long 0x2C 12. "SPI1SMEN,SPI1 clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x2C 11. "TIM1SMEN,TIM1 timer clock enable during Sleep mode" "0: Disable,1: Enable"
|
|
bitfld.long 0x2C 0. "SYSCFGSMEN,SYSCFG clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "RCC_CCIPR,RCC peripherals independent clock configuration register"
|
|
bitfld.long 0x0 30.--31. "ADCSEL,ADCs clock source selection" "0: System clock,?,2: HSIKER,?"
|
|
bitfld.long 0x0 14.--15. "I2S1SEL,I2S1 clock source selection" "0: SYSCLK,?,2: HSIKER,3: I2S_CKIN"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,?"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,3: LSE"
|
|
endif
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "RCC_CSR1,RCC control/status register 1"
|
|
bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0: LSI,1: LSE"
|
|
bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 16. "RTCRST,RTC domain software reset" "0: No effect,1: Reset"
|
|
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: No clock,1: LSE,2: LSI,3: HSE divided by 32"
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure Detection" "0: No failure detected,1: Failure detected"
|
|
newline
|
|
bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive capability" "0: low driving capability,1: medium-low driving capability,2: medium-high driving capability,3: high driving capability"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 3. "LSEDRV,LSE oscillator drive capability" "0: medium-high driving capability,1: high driving capability"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 3. "LSEDRV,LSE oscillator drive capability" "0: medium-high driving capability,1: high driving capability"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 3. "LSEDRV,LSE oscillator drive capability" "0: medium-high driving capability,1: high driving capability"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 3. "LSEDRV,LSE oscillator drive capability" "0: medium-high driving capability,1: high driving capability"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: Not bypassed,1: Bypassed"
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: Not ready,1: Ready"
|
|
newline
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0: Disable,1: Enable"
|
|
line.long 0x4 "RCC_CSR2,RCC control/status register 2"
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0: No illegal mode reset occurred,1: Illegal mode reset occurred"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0: No window watchdog reset occurred,1: Window watchdog reset occurred"
|
|
newline
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0: No independent watchdog reset occurred,1: Independent watchdog reset occurred"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred"
|
|
newline
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0: No BOR or POR occurred,1: BOR or POR occurred"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0: No reset from NRST pin occurred,1: Reset from NRST pin occurred"
|
|
newline
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0: No reset from Option byte loading occurred,1: Reset from Option byte loading occurred"
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flags" "0: No effect,1: Clear reset flags"
|
|
newline
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: Not ready,1: Ready"
|
|
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,RCC clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI48 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1"
|
|
bitfld.long 0x0 30.--31. "ADCSEL,ADCs clock source selection" "0: System clock,?,2: HSIKER,?"
|
|
bitfld.long 0x0 14.--15. "I2S1SEL,I2S1 clock source selection" "0: SYSCLK,?,2: HSIKER,3: I2S_CKIN"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,?"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,3: LSE"
|
|
line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2"
|
|
bitfld.long 0x4 12. "USBSEL,USB clock source selection" "0: HSIUSB48,1: HSE"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,RCC clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI48 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1"
|
|
bitfld.long 0x0 30.--31. "ADCSEL,ADCs clock source selection" "0: System clock,?,2: HSIKER,?"
|
|
bitfld.long 0x0 14.--15. "I2S1SEL,I2S1 clock source selection" "0: SYSCLK,?,2: HSIKER,3: I2S_CKIN"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,?"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,3: LSE"
|
|
line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2"
|
|
bitfld.long 0x4 12. "USBSEL,USB clock source selection" "0: HSIUSB48,1: HSE"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,RCC clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI48 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1"
|
|
bitfld.long 0x0 30.--31. "ADCSEL,ADCs clock source selection" "0: System clock,?,2: HSIKER,?"
|
|
bitfld.long 0x0 14.--15. "I2S1SEL,I2S1 clock source selection" "0: SYSCLK,?,2: HSIKER,3: I2S_CKIN"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,?"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,3: LSE"
|
|
line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2"
|
|
bitfld.long 0x4 12. "USBSEL,USB clock source selection" "0: HSIUSB48,1: HSE"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "RCC_CIFR,RCC clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI48 ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: Interrupt not pending,1: Interrupt pending"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "RCC_CICR,RCC clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
|
|
newline
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI48 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
|
|
newline
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "RCC_CCIPR1,RCC peripherals independent clock configuration register 1"
|
|
bitfld.long 0x0 30.--31. "ADCSEL,ADCs clock source selection" "0: System clock,?,2: HSIKER,?"
|
|
bitfld.long 0x0 14.--15. "I2S1SEL,I2S1 clock source selection" "0: SYSCLK,?,2: HSIKER,3: I2S_CKIN"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,?"
|
|
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSIKER,3: LSE"
|
|
line.long 0x4 "RCC_CCIPR2,RCC peripherals independent clock configuration register 2"
|
|
bitfld.long 0x4 12. "USBSEL,USB clock source selection" "0: HSIUSB48,1: HSE"
|
|
endif
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "RTC_CR,RTC control register"
|
|
bitfld.long 0x0 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0x0 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0x0 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0x0 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
newline
|
|
bitfld.long 0x0 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,?,?"
|
|
bitfld.long 0x0 20. "POL,Output polarity" "0: The pin is high when ALRAF is asserted..,1: The pin is low when ALRAF is asserted (depending.."
|
|
newline
|
|
bitfld.long 0x0 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
bitfld.long 0x0 18. "BKP,Backup" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
bitfld.long 0x0 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
newline
|
|
bitfld.long 0x0 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
bitfld.long 0x0 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
bitfld.long 0x0 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
bitfld.long 0x0 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
newline
|
|
bitfld.long 0x0 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60 Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
bitfld.long 0x0 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day dont care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is dont.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours dont care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes dont care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds dont care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x0 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x0 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU,Date units in BCD format"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x0 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x0 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x0 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x0 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU,Date units in BCD format"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x0 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x0 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x0 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x0 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU,Date units in BCD format"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x0 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x0 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x0 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x0 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DU,Date units in BCD format"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x0 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
bitfld.long 0x0 3. "TSMF,Timestamp masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32C051*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI1_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI1_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI1_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI1_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI1_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI1_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI1_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI1_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI1_I2SCFGR,SPI1_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI1_I2SPR,SPI1_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
sif (cpuis("STM32C011*"))
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI1_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI1_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI1_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI1_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI1_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI1_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI1_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI1_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI1_I2SCFGR,SPI1_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI1_I2SPR,SPI1_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPIx_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPIx_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPIx_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPIx_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SYSCFG_CFGR1,SYSCFG configuration register 1"
|
|
bitfld.long 0x0 24. "I2C_PC14_FMP,Fast Mode Plus (FM+) enable for PC14" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 23. "I2C_PA10_FMP,Fast Mode Plus (FM+) enable for PA10" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 22. "I2C_PA9_FMP,Fast Mode Plus (FM+) enable for PA9" "0: Disable,1: Enable"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x0 21. "I2C2_FMP,Fast Mode Plus (FM+) enable for I2C2" "0: Disable disabled if not enabled through I2C_y_FMP,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 21. "I2C2_FMP,Fast Mode Plus (FM+) enable for I2C2" "0: Disable disabled if not enabled through I2C_y_FMP,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 21. "I2C2_FMP,Fast Mode Plus (FM+) enable for I2C2" "0: Disable disabled if not enabled through I2C_y_FMP,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 21. "I2C2_FMP,Fast Mode Plus (FM+) enable for I2C2" "0: Disable disabled if not enabled through I2C_y_FMP,1: Enable"
|
|
endif
|
|
bitfld.long 0x0 20. "I2C1_FMP,Fast Mode Plus (FM+) enable for I2C1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 19. "I2C_PB9_FMP,Fast Mode Plus (FM+) enable for PB9" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 18. "I2C_PB8_FMP,Fast Mode Plus (FM+) enable for PB8" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 17. "I2C_PB7_FMP,Fast Mode Plus (FM+) enable for PB7" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "I2C_PB6_FMP,Fast Mode Plus (FM+) enable for PB6" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IR_MOD,IR Modulation Envelope signal selection" "0: TIM16,1: USART1,2: USART2,?"
|
|
bitfld.long 0x0 5. "IR_POL,IR output polarity selection" "0: Output of IRTIM (IR_OUT) is not inverted,1: Output of IRTIM (IR_OUT) is inverted"
|
|
newline
|
|
bitfld.long 0x0 4. "PA12_RMP,PA12 pin remapping" "0: No remap (PA12),1: Remap (PA10)"
|
|
bitfld.long 0x0 3. "PA11_RMP,PA11 pin remapping" "0: No remap (PA11),1: Remap (PA9)"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "MEM_MODE,Memory mapping selection bits" "?,1: System Flash memory,?,3: Embedded SRAM"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
bitfld.long 0x0 0. "LOCKUP_LOCK,Cortex<Superscript><Default Font>-M0+ LOCKUP enable" "0: Disable,1: Enable"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "SYSCFG_CFGR3,SYSCFG configuration register 3"
|
|
bitfld.long 0x0 10.--11. "PINMUX5,Pin GPIO multiplexer 5" "0: PA3,1: PA4,2: PA5,3: PA6"
|
|
bitfld.long 0x0 8.--9. "PINMUX4,Pin GPIO multiplexer 4" "0: PA7,1: PA12,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "PINMUX3,Pin GPIO multiplexer 3" "0: PA14,1: PB6,2: PC15,?"
|
|
bitfld.long 0x0 4.--5. "PINMUX2,Pin GPIO multiplexer 2" "0: PA8,1: PA11,?,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PINMUX1,Pin GPIO multiplexer 1" "0: PF2,1: PA0,2: PA1,3: PA2"
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x0 0.--1. "PINMUX0,Pin GPIO multiplexer 0" "0: PB7,1: PC14,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x0 0.--1. "PINMUX0,Pin GPIO multiplexer 0" "0: PB7,?,?,?"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x0 0.--1. "PINMUX0,Pin GPIO multiplexer 0" "0: PB7,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x0 0.--1. "PINMUX0,Pin GPIO multiplexer 0" "0: PB7,?,?,?"
|
|
endif
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
|
|
rgroup.long 0x88++0x17
|
|
line.long 0x0 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
|
|
bitfld.long 0x0 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
|
|
bitfld.long 0x4 1. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
|
|
line.long 0x8 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x8 1. "CRS,CRS interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
bitfld.long 0x8 1. "CRS,CRS interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
bitfld.long 0x8 1. "CRS,CRS interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
bitfld.long 0x8 1. "CRS,CRS interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 0. "RCC,Reset and clock control interrupt request pending" "0,1"
|
|
line.long 0xC "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
|
|
bitfld.long 0xC 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
|
|
bitfld.long 0xC 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
|
|
line.long 0x10 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
|
|
bitfld.long 0x10 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x10 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
|
|
line.long 0x14 "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
|
|
bitfld.long 0x14 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
|
|
bitfld.long 0x14 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
|
|
rgroup.long 0xA4++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1 channel 1interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
|
|
bitfld.long 0x4 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x4 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
|
|
group.long 0xAC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
|
|
sif (cpuis("STM32C051*"))
|
|
rbitfld.long 0x0 2. "DMA_CH5,DMA channel 5 interrupt request pending" "0,1"
|
|
rbitfld.long 0x0 1. "DMA_CH4,DMA channel 5 interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rbitfld.long 0x0 2. "DMA_CH5,DMA channel 5 interrupt request pending" "0,1"
|
|
rbitfld.long 0x0 1. "DMA_CH4,DMA channel 5 interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rbitfld.long 0x0 2. "DMA_CH5,DMA channel 5 interrupt request pending" "0,1"
|
|
rbitfld.long 0x0 1. "DMA_CH4,DMA channel 5 interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rbitfld.long 0x0 2. "DMA_CH5,DMA channel 5 interrupt request pending" "0,1"
|
|
rbitfld.long 0x0 1. "DMA_CH4,DMA channel 5 interrupt request pending" "0,1"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x0 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
|
|
rgroup.long 0xB0++0xB
|
|
line.long 0x0 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
|
|
bitfld.long 0x0 0. "ADC,ADC interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
|
|
bitfld.long 0x4 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
|
|
bitfld.long 0x4 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
|
|
bitfld.long 0x4 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
|
|
line.long 0x8 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
|
|
bitfld.long 0x8 0. "TIM1_CC,Timer 1 capture compare interrupt request pending" "0,1"
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
|
|
bitfld.long 0x0 0. "TIM3,Timer 3 interrupt request pending" "0,1"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
|
|
bitfld.long 0x0 0. "TIM14,Timer 14 interrupt request pending" "0,1"
|
|
rgroup.long 0xD4++0xB
|
|
line.long 0x0 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
|
|
bitfld.long 0x0 0. "TIM16,Timer 16 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
|
|
bitfld.long 0x4 0. "TIM17,Timer 17 interrupt request pending" "0,1"
|
|
line.long 0x8 "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
|
|
bitfld.long 0x8 0. "I2C1,I2C1 interrupt request pending combined with EXTI line 23" "0,1"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
|
|
bitfld.long 0x0 0. "SPI1,SPI1 interrupt request pending" "0,1"
|
|
rgroup.long 0xEC++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
|
|
bitfld.long 0x0 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
|
|
bitfld.long 0x4 0. "USART2,USART2 interrupt request pending (EXTI line 26)" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE1,SYSCFG interrupt line 1 status register"
|
|
bitfld.long 0x4 1. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply monitoring interrupt request pending (EXTI line 34)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
|
|
bitfld.long 0x0 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
|
|
bitfld.long 0x0 1. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
|
|
bitfld.long 0x0 0. "RCC,Reset and clock control interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
|
|
bitfld.long 0x0 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
|
|
bitfld.long 0x0 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
|
|
bitfld.long 0x0 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE8,SYSCFG interrupt line 8 status register"
|
|
bitfld.long 0x4 0. "USB,USB interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1 channel 1interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
|
|
bitfld.long 0x0 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
|
|
bitfld.long 0x0 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
|
|
bitfld.long 0x0 0. "ADC,ADC interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
|
|
bitfld.long 0x0 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xB8++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
|
|
bitfld.long 0x0 0. "TIM1_CC,Timer 1 capture compare interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE15,SYSCFG interrupt line 15 status register"
|
|
bitfld.long 0x4 0. "TIM2,TIM2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
|
|
bitfld.long 0x0 0. "TIM3,Timer 3 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
|
|
bitfld.long 0x0 0. "TIM14,Timer 14 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xD4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
|
|
bitfld.long 0x0 0. "TIM16,Timer 16 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
|
|
bitfld.long 0x0 0. "TIM17,Timer 17 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xDC++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
|
|
bitfld.long 0x0 0. "I2C1,I2C1 interrupt request pending combined with EXTI line 23" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE24,SYSCFG interrupt line 24 status register"
|
|
bitfld.long 0x4 0. "I2C2,I2C2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
|
|
bitfld.long 0x0 0. "SPI1,SPI1 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE26,SYSCFG interrupt line 26 status register"
|
|
bitfld.long 0x4 0. "SPI2,SPI2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
|
|
bitfld.long 0x0 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
|
|
bitfld.long 0x0 0. "USART2,USART2 interrupt request pending (EXTI line 26)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE1,SYSCFG interrupt line 1 status register"
|
|
bitfld.long 0x4 1. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply monitoring interrupt request pending (EXTI line 34)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
|
|
bitfld.long 0x0 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
|
|
bitfld.long 0x0 1. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
|
|
bitfld.long 0x0 0. "RCC,Reset and clock control interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
|
|
bitfld.long 0x0 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
|
|
bitfld.long 0x0 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
|
|
bitfld.long 0x0 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE8,SYSCFG interrupt line 8 status register"
|
|
bitfld.long 0x4 0. "USB,USB interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1 channel 1interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
|
|
bitfld.long 0x0 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
|
|
bitfld.long 0x0 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
|
|
bitfld.long 0x0 0. "ADC,ADC interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
|
|
bitfld.long 0x0 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xB8++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
|
|
bitfld.long 0x0 0. "TIM1_CC,Timer 1 capture compare interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE15,SYSCFG interrupt line 15 status register"
|
|
bitfld.long 0x4 0. "TIM2,TIM2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
|
|
bitfld.long 0x0 0. "TIM3,Timer 3 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
|
|
bitfld.long 0x0 0. "TIM14,Timer 14 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xD4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
|
|
bitfld.long 0x0 0. "TIM16,Timer 16 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
|
|
bitfld.long 0x0 0. "TIM17,Timer 17 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xDC++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
|
|
bitfld.long 0x0 0. "I2C1,I2C1 interrupt request pending combined with EXTI line 23" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE24,SYSCFG interrupt line 24 status register"
|
|
bitfld.long 0x4 0. "I2C2,I2C2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
|
|
bitfld.long 0x0 0. "SPI1,SPI1 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE26,SYSCFG interrupt line 26 status register"
|
|
bitfld.long 0x4 0. "SPI2,SPI2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
|
|
bitfld.long 0x0 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
|
|
bitfld.long 0x0 0. "USART2,USART2 interrupt request pending (EXTI line 26)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE1,SYSCFG interrupt line 1 status register"
|
|
bitfld.long 0x4 1. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply monitoring interrupt request pending (EXTI line 34)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
|
|
bitfld.long 0x0 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
|
|
bitfld.long 0x0 1. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
|
|
bitfld.long 0x0 0. "RCC,Reset and clock control interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
|
|
bitfld.long 0x0 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
|
|
bitfld.long 0x0 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
|
|
bitfld.long 0x0 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE8,SYSCFG interrupt line 8 status register"
|
|
bitfld.long 0x4 0. "USB,USB interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1 channel 1interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
|
|
bitfld.long 0x0 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
|
|
bitfld.long 0x0 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
|
|
bitfld.long 0x0 0. "ADC,ADC interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
|
|
bitfld.long 0x0 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xB8++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
|
|
bitfld.long 0x0 0. "TIM1_CC,Timer 1 capture compare interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE15,SYSCFG interrupt line 15 status register"
|
|
bitfld.long 0x4 0. "TIM2,TIM2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
|
|
bitfld.long 0x0 0. "TIM3,Timer 3 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
|
|
bitfld.long 0x0 0. "TIM14,Timer 14 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xD4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
|
|
bitfld.long 0x0 0. "TIM16,Timer 16 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
|
|
bitfld.long 0x0 0. "TIM17,Timer 17 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xDC++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
|
|
bitfld.long 0x0 0. "I2C1,I2C1 interrupt request pending combined with EXTI line 23" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE24,SYSCFG interrupt line 24 status register"
|
|
bitfld.long 0x4 0. "I2C2,I2C2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
|
|
bitfld.long 0x0 0. "SPI1,SPI1 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE26,SYSCFG interrupt line 26 status register"
|
|
bitfld.long 0x4 0. "SPI2,SPI2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
|
|
bitfld.long 0x0 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
|
|
bitfld.long 0x0 0. "USART2,USART2 interrupt request pending (EXTI line 26)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE1,SYSCFG interrupt line 1 status register"
|
|
bitfld.long 0x4 1. "PVM_VDDIO2_OUT,V<sub>DDIO2</sub> supply monitoring interrupt request pending (EXTI line 34)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
|
|
bitfld.long 0x0 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x8C++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
|
|
bitfld.long 0x0 1. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
|
|
bitfld.long 0x0 0. "RCC,Reset and clock control interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
|
|
bitfld.long 0x0 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
|
|
bitfld.long 0x0 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0x9C++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
|
|
bitfld.long 0x0 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE8,SYSCFG interrupt line 8 status register"
|
|
bitfld.long 0x4 0. "USB,USB interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1 channel 1interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
|
|
bitfld.long 0x0 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
|
|
bitfld.long 0x0 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xB0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
|
|
bitfld.long 0x0 0. "ADC,ADC interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
|
|
bitfld.long 0x0 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
|
|
bitfld.long 0x0 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
|
|
bitfld.long 0x0 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xB8++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
|
|
bitfld.long 0x0 0. "TIM1_CC,Timer 1 capture compare interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE15,SYSCFG interrupt line 15 status register"
|
|
bitfld.long 0x4 0. "TIM2,TIM2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
|
|
bitfld.long 0x0 0. "TIM3,Timer 3 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
|
|
bitfld.long 0x0 0. "TIM14,Timer 14 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xD4++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
|
|
bitfld.long 0x0 0. "TIM16,Timer 16 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
|
|
bitfld.long 0x0 0. "TIM17,Timer 17 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xDC++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
|
|
bitfld.long 0x0 0. "I2C1,I2C1 interrupt request pending combined with EXTI line 23" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE24,SYSCFG interrupt line 24 status register"
|
|
bitfld.long 0x4 0. "I2C2,I2C2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x0 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
|
|
bitfld.long 0x0 0. "SPI1,SPI1 interrupt request pending" "0,1"
|
|
line.long 0x4 "SYSCFG_ITLINE26,SYSCFG interrupt line 26 status register"
|
|
bitfld.long 0x4 0. "SPI2,SPI2 interrupt request pending" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
|
|
bitfld.long 0x0 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
rgroup.long 0xF0++0x3
|
|
line.long 0x0 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
|
|
bitfld.long 0x0 0. "USART2,USART2 interrupt request pending (EXTI line 26)" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "TIM (Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32C011*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM1_CR1,TIM1 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "TIM1_CR2,TIM1 control register 2"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register"
|
|
bitfld.long 0x4 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x4 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is not connected (reserved..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM1_DIER,TIM1 DMA/interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TIM1_SR,TIM1 status register"
|
|
bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM1_EGR,TIM1 event generation register"
|
|
bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM1_CCMR1_input,TIM1 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM1_CCMR1_output,TIM1 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM1_CCMR2_input,TIM1 capture/compare mode register 2 [alternate]"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "TIM1_CCMR2_output,TIM1 capture/compare mode register 2 [alternate]"
|
|
bitfld.long 0x0 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "TIM1_CNT,TIM1 counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM1_PSC,TIM1 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM1_ARR,TIM1 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM1_RCR,TIM1 repetition counter register"
|
|
hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM1_CCR1,TIM1 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "TIM1_CCR2,TIM1 capture/compare register 2"
|
|
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.word 0x3C++0x1
|
|
line.word 0x0 "TIM1_CCR3,TIM1 capture/compare register 3"
|
|
hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "TIM1_CCR4,TIM1 capture/compare register 4"
|
|
hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM1_BDTR,TIM1 break and dead-time register"
|
|
bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM1_DCR,TIM1 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "TIM1_DMAR,TIM1 DMA address for full transfer"
|
|
hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "TIM1_CCMR3,TIM1 capture/compare mode register 3"
|
|
bitfld.long 0x0 24. "OC6M2,Output compare 6 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC5M2,Output compare 5 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x4 "TIM1_CCR5,TIM1 capture/compare register 5"
|
|
bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM1_CCR6,TIM1 capture/compare register 6"
|
|
hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "TIM1_AF1,TIM1 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x4 "TIM1_AF2,TIM1 Alternate function register 2"
|
|
bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x8 "TIM1_TISEL,TIM1 timer input selection register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 tCK_INT,2: tDTS = 4 tCK_INT,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM3_CR2,TIM3 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM3_SMCR,TIM3 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x0 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is unconnected.,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x0 0.--2. "SMS1,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM3_SR,TIM3 status register"
|
|
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM3_EGR,TIM3 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM3_CCMR1_input,TIM3 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM3_CCMR1_output,TIM3 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 24. "OC2M2,Output compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM3_CCMR2_input,TIM3 capture/compare mode register 2 [alternate]"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TIM3_CCMR2_output,TIM3 capture/compare mode register 2 [alternate]"
|
|
bitfld.long 0x0 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M1,Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M1,Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register"
|
|
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT,TIM3 counter [alternate]"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT_alternate,TIM3 counter [alternate]"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM3_PSC,TIM3 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM3_ARR,TIM3 auto-reload register"
|
|
hexmask.long.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM3_DCR,TIM3 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM3_DMAR,TIM3 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM3_AF1,TIM3 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM3_TISEL,TIM3 timer input selection register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM14_CR1,TIM14 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 tCK_INT,2: tDTS = 4 tCK_INT,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM14_SR,TIM14 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM14_EGR,TIM14 event generation register"
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1_input,TIM14 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1_output,TIM14 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM14_CNT,TIM14 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM14_PSC,TIM14 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM14_ARR,TIM14 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM14_CCR1,TIM14 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x68++0x1
|
|
line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM16_CR1,TIM16 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM16_CR2,TIM16 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM16_SR,TIM16 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM16_EGR,TIM16 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_input,TIM16 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_output,TIM16 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM16_CNT,TIM16 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM16_PSC,TIM16 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM16_ARR,TIM16 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM16_RCR,TIM16 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM16_CCR1,TIM16 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM16_DCR,TIM16 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM16_DMAR,TIM16 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM16_AF1,TIM16 alternate function register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM16_TISEL,TIM16 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM17_CR1,TIM17 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM17_CR2,TIM17 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM17_DIER,TIM17 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM17_SR,TIM17 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM17_EGR,TIM17 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1_input,TIM17 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1_output,TIM17 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM17_CCER,TIM17 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM17_CNT,TIM17 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM17_PSC,TIM17 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM17_ARR,TIM17 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM17_RCR,TIM17 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM17_CCR1,TIM17 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM17_BDTR,TIM17 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM17_DCR,TIM17 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM17_DMAR,TIM17 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM17_AF1,TIM17 alternate function register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM17_TISEL,TIM17 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM1_CR1,TIM1 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "TIM1_CR2,TIM1 control register 2"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
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|
newline
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bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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|
newline
|
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bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register"
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bitfld.long 0x4 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x4 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
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|
newline
|
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bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
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bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
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|
newline
|
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bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
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hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
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newline
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bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x4 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
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newline
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bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is not connected (reserved..,1: OCREF_CLR_INT is connected to ETRF"
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bitfld.long 0x4 0.--2. "SMS1,Slave mode selection" "0,1,2,3,4,5,6,7"
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|
group.word 0xC++0x1
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line.word 0x0 "TIM1_DIER,TIM1 DMA/interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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|
newline
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bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
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bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
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|
newline
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bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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|
newline
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bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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|
newline
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bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
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bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
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bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
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newline
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bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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|
newline
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bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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group.long 0x10++0x3
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line.long 0x0 "TIM1_SR,TIM1 status register"
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bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1"
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bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1"
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newline
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bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
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bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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newline
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bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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newline
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bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
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newline
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bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
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bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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newline
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bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
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bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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newline
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bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
|
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bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
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bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM1_EGR,TIM1 event generation register"
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|
bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
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bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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|
newline
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bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
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|
newline
|
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bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
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bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
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|
newline
|
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bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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|
newline
|
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bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "TIM1_CCMR1_input,TIM1 capture/compare mode register 1 [alternate]"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x7
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line.long 0x0 "TIM1_CCMR1_output,TIM1 capture/compare mode register 1 [alternate]"
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bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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newline
|
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bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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line.long 0x4 "TIM1_CCMR2_input,TIM1 capture/compare mode register 2 [alternate]"
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hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
|
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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group.long 0x1C++0xB
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line.long 0x0 "TIM1_CCMR2_output,TIM1 capture/compare mode register 2 [alternate]"
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bitfld.long 0x0 24. "OC4M2,Output compare 4 mode" "0,1"
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bitfld.long 0x0 16. "OC3M2,Output compare 3 mode" "0,1"
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newline
|
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bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
|
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bitfld.long 0x0 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register"
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bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
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bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
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newline
|
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bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
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bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
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|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
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newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
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bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
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|
newline
|
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bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
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|
newline
|
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bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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|
newline
|
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bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
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|
newline
|
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bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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|
newline
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bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x8 "TIM1_CNT,TIM1 counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
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|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM1_PSC,TIM1 prescaler"
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hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
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group.word 0x2C++0x1
|
|
line.word 0x0 "TIM1_ARR,TIM1 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
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group.word 0x30++0x1
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line.word 0x0 "TIM1_RCR,TIM1 repetition counter register"
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hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
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line.word 0x0 "TIM1_CCR1,TIM1 capture/compare register 1"
|
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hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "TIM1_CCR2,TIM1 capture/compare register 2"
|
|
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.word 0x3C++0x1
|
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line.word 0x0 "TIM1_CCR3,TIM1 capture/compare register 3"
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hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "TIM1_CCR4,TIM1 capture/compare register 4"
|
|
hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM1_BDTR,TIM1 break and dead-time register"
|
|
bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1"
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|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
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bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
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bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
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hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
newline
|
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bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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|
newline
|
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bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
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|
newline
|
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM1_DCR,TIM1 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "TIM1_DMAR,TIM1 DMA address for full transfer"
|
|
hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "TIM1_CCMR3,TIM1 capture/compare mode register 3"
|
|
bitfld.long 0x0 24. "OC6M2,Output compare 6 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC5M2,Output compare 5 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC6M1,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC5M1,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x4 "TIM1_CCR5,TIM1 capture/compare register 5"
|
|
bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM1_CCR6,TIM1 capture/compare register 6"
|
|
hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "TIM1_AF1,TIM1 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x4 "TIM1_AF2,TIM1 Alternate function register 2"
|
|
bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x8 "TIM1_TISEL,TIM1 timer input selection register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C031*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM16_CR1,TIM16 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM16_CR2,TIM16 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM16_SR,TIM16 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM16_EGR,TIM16 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_input,TIM16 capture/compare mode register 1 [alternate]"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_output,TIM16 capture/compare mode register 1 [alternate]"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM16_CNT,TIM16 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM16_PSC,TIM16 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM16_ARR,TIM16 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM16_RCR,TIM16 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM16_CCR1,TIM16 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM16_DCR,TIM16 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM16_DMAR,TIM16 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM16_AF1,TIM16 alternate function register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM16_TISEL,TIM16 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM1_CR1,TIM1 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub>=t<sub>CK_INT</sub>,1: t<sub>DTS</sub>=2*t<sub>CK_INT</sub>,2: t<sub>DTS</sub>=4*t<sub>CK_INT</sub>,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "TIM1_CR2,TIM1 control register 2"
|
|
hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register"
|
|
bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x4 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is not connected (reserved..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x4 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM1_DIER,TIM1 DMA/interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "TIM1_SR,TIM1 status register"
|
|
bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM1_EGR,TIM1 event generation register"
|
|
bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM1_CCMR1,TIM1 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM1_CCMR1_ALTERNATE1,TIM1 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM1_CCMR2,TIM1 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "TIM1_CCMR2_ALTERNATE1,TIM1 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "TIM1_CNT,TIM1 counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM1_PSC,TIM1 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM1_ARR,TIM1 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM1_RCR,TIM1 repetition counter register"
|
|
hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM1_CCR1,TIM1 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "TIM1_CCR2,TIM1 capture/compare register 2"
|
|
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.word 0x3C++0x1
|
|
line.word 0x0 "TIM1_CCR3,TIM1 capture/compare register 3"
|
|
hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value"
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "TIM1_CCR4,TIM1 capture/compare register 4"
|
|
hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM1_BDTR,TIM1 break and dead-time register"
|
|
bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM1_DCR,TIM1 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "TIM1_DMAR,TIM1 DMA address for full transfer"
|
|
hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "TIM1_CCMR3,TIM1 capture/compare mode register 3"
|
|
bitfld.long 0x0 24. "OC6M_1,OC6M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC5M_1,OC5M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC6M,OC6M[2:0]: Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC5M,OC5M[2:0]: Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable" "0,1"
|
|
bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1"
|
|
line.long 0x4 "TIM1_CCR5,TIM1 capture/compare register 5"
|
|
bitfld.long 0x4 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x4 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x4 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x0 "TIM1_CCR6,TIM1 capture/compare register 6"
|
|
hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "TIM1_AF1,TIM1 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x4 "TIM1_AF2,TIM1 Alternate function register 2"
|
|
bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x8 "TIM1_TISEL,TIM1 timer input selection register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM2 (General Purpose Timer)"
|
|
base ad:0x40000000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM2_CR1,TIM2 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tless thansub>DTSless than/sub> = tless..,1: tless thansub>DTSless than/sub> = 2 X tless..,2: tless thansub>DTSless than/sub> = 4 X tless..,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode.,1: Center-aligned mode 1.,2: Center-aligned mode 2.,3: Center-aligned mode 3."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM2_CR2,TIM2 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM2_SMCR,TIM2 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is unconnected.,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM2_DIER,TIM2 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM2_SR,TIM2 status register"
|
|
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM2_EGR,TIM2 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register."
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM2_CCMR1,TIM2 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM2_CCMR1_ALTERNATE1,TIM2 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM2_CCMR2,TIM2 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TIM2_CCMR2_ALTERNATE1,TIM2 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM2_CCER,TIM2 capture/compare enable register"
|
|
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM2_CNT,TIM2 counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,Least significant part of counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM2_CNT_ALTERNATE1,TIM2 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM2_PSC,TIM2 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM2_ARR,TIM2 auto-reload register"
|
|
hexmask.long 0x0 0.--31. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIM2_CCR1,TIM2 capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,Low Capture/Compare 1 value"
|
|
line.long 0x4 "TIM2_CCR2,TIM2 capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,Low Capture/Compare 2 value"
|
|
line.long 0x8 "TIM2_CCR3,TIM2 capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,Low Capture/Compare value"
|
|
line.long 0xC "TIM2_CCR4,TIM2 capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,Low Capture/Compare value"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM2_DCR,TIM2 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM2_AF1,TIM2 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM2_TISEL,TIM2 timer input selection register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>CK_INT</sub>,1: t<sub>DTS</sub> = 2 t<sub>CK_INT</sub>,2: t<sub>DTS</sub> = 4 t<sub>CK_INT</sub>,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM3_CR2,TIM3 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM3_SMCR,TIM3 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is unconnected.,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM3_SR,TIM3 status register"
|
|
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM3_EGR,TIM3 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM3_CCMR1,TIM3 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM3_CCMR1_ALTERNATE1,TIM3 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM3_CCMR2,TIM3 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TIM3_CCMR2_ALTERNATE1,TIM3 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register"
|
|
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT,TIM3 counter"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT_ALTERNATE1,TIM3 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM3_PSC,TIM3 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM3_ARR,TIM3 auto-reload register"
|
|
hexmask.long.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4,Capture/Compare value"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM3_DCR,TIM3 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM3_DMAR,TIM3 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM3_AF1,TIM3 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM3_TISEL,TIM3 timer input selection register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM14_CR1,TIM14 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>CK_INT</sub>,1: t<sub>DTS</sub> = 2 t<sub>CK_INT</sub>,2: t<sub>DTS</sub> = 4 t<sub>CK_INT</sub>,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM14_DIER,TIM14 Interrupt enable register"
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM14_SR,TIM14 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM14_EGR,TIM14 event generation register"
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1,TIM14 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM14_CCMR1_ALTERNATE1,TIM14 capture/compare mode register 1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: Reserved.,3: Reserved."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM14_CCER,TIM14 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM14_CNT,TIM14 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM14_PSC,TIM14 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM14_ARR,TIM14 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM14_CCR1,TIM14 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x68++0x1
|
|
line.word 0x0 "TIM14_TISEL,TIM14 timer input selection register"
|
|
hexmask.word.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM16_CR1,TIM16 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t <sub>DTS</sub>= t<sub>CK_INT</sub>,1: t <sub>DTS</sub>= 2 * t<sub>CK_INT</sub>,2: t<sub>DTS</sub> = 4 * t<sub>CK_INT</sub>,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM16_CR2,TIM16 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM16_SR,TIM16 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM16_EGR,TIM16 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1,TIM16 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM16_CCMR1_ALTERNATE1,TIM16 capture/compare mode register 1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM16_CNT,TIM16 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM16_PSC,TIM16 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM16_ARR,TIM16 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM16_RCR,TIM16 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM16_CCR1,TIM16 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM16_DCR,TIM16 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM16_DMAR,TIM16 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM16_AF1,TIM16 alternate function register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM16_TISEL,TIM16 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C051*")||cpuis("STM32C071*")||cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM17_CR1,TIM17 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t <sub>DTS</sub>= t<sub>CK_INT</sub>,1: t <sub>DTS</sub>= 2 * t<sub>CK_INT</sub>,2: t<sub>DTS</sub> = 4 * t<sub>CK_INT</sub>,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM17_CR2,TIM17 control register 2"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM17_DIER,TIM17 DMA/interrupt enable register"
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM17_SR,TIM17 status register"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM17_EGR,TIM17 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1,TIM17 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM17_CCMR1_ALTERNATE1,TIM17 capture/compare mode register 1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM17_CCER,TIM17 capture/compare enable register"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM17_CNT,TIM17 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM17_PSC,TIM17 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM17_ARR,TIM17 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM17_RCR,TIM17 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM17_CCR1,TIM17 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM17_BDTR,TIM17 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM17_DCR,TIM17 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM17_DMAR,TIM17 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM17_AF1,TIM17 alternate function register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM17_TISEL,TIM17 input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM3_CR1,TIM3 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub> = t<sub>CK_INT</sub>,1: t<sub>DTS</sub> = 2 t<sub>CK_INT</sub>,2: t<sub>DTS</sub> = 4 t<sub>CK_INT</sub>,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM3_CR2,TIM3 control register 2"
|
|
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM3_SMCR,TIM3 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is unconnected.,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM3_SR,TIM3 status register"
|
|
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x0 "TIM3_EGR,TIM3 event generation register"
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM3_CCMR1,TIM3 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "TIM3_CCMR1_ALTERNATE1,TIM3 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "?,?,?,?,?,?,6: 4,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "TIM3_CCMR2,TIM3 capture/compare mode register 2"
|
|
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "TIM3_CCMR2_ALTERNATE1,TIM3 capture/compare mode register 2"
|
|
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "?,?,?,?,?,?,6: 4 in TIMx_CCMR1 register,?"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register"
|
|
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT,TIM3 counter"
|
|
hexmask.long 0x0 0.--31. 1. "CNT,counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM3_CNT_ALTERNATE1,TIM3 counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM3_PSC,TIM3 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TIM3_ARR,TIM3 auto-reload register"
|
|
hexmask.long 0x0 0.--31. 1. "ARR,Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,Capture/Compare value"
|
|
line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,Capture/Compare value"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM3_DCR,TIM3 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM3_DMAR,TIM3 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM3_AF1,TIM3 alternate function option register 1"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM3_TISEL,TIM3 timer input selection register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*")||cpuis("STM32C092*"))
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "TIM15_CR1,TIM15 control register 1"
|
|
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
|
|
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: tless thansub>DTS less than/sub>= tless..,1: tless thansub>DTSless than/sub> = 2*tless..,2: tless thansub>DTSless than/sub> = 4*tless..,?"
|
|
newline
|
|
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
|
|
newline
|
|
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIM15_CR2,TIM15 control register 2"
|
|
bitfld.word 0x0 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
|
|
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|
|
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
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|
|
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "TIM15_SMCR,TIM15 slave mode control register"
|
|
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable register"
|
|
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "TIM15_SR,TIM15 status register"
|
|
bitfld.word 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending."
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "TIM15_EGR,TIM15 event generation register"
|
|
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated."
|
|
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register."
|
|
newline
|
|
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM15_CCMR1,TIM15 capture/compare mode register 1"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "TIM15_CCMR1_ALTERNATE1,TIM15 capture/compare mode register 1"
|
|
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable register"
|
|
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
newline
|
|
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active.,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
|
|
newline
|
|
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "TIM15_CNT,TIM15 counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "TIM15_PSC,TIM15 prescaler"
|
|
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "TIM15_ARR,TIM15 auto-reload register"
|
|
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "TIM15_RCR,TIM15 repetition counter register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "TIM15_CCR1,TIM15 capture/compare register 1"
|
|
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "TIM15_CCR2,TIM15 capture/compare register 2"
|
|
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "TIM15_BDTR,TIM15 break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "TIM15_DCR,TIM15 DMA control register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "TIM15_DMAR,TIM15 DMA address for full transfer"
|
|
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TIM15_AF1,TIM15 alternate register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TIM15_TISEL,TIM15 input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32C071*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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|
line.long 0x8 "USART_CR3,USART control register 3"
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|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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|
rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR,USART interrupt and status register"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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|
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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|
newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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|
newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
|
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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|
newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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|
newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
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line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR,USART interrupt and status register"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
|
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line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
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newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
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bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
|
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line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "USART_CR2,USART control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "USART_CR3,USART control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "USART_BRR,USART baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "USART_RTOR,USART receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "USART_RQR,USART request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR,USART interrupt and status register"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "USART_ICR,USART interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "USART_RDR,USART receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "USART_TDR,USART transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "USART_PRESC,USART prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "USART3"
|
|
base ad:0x40004800
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group.long 0x0++0x3
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line.long 0x0 "USART_CR1,USART control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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|
newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
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|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
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|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
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newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
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newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*")||cpuis("STM32C051*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_enabled,USART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_disabled,USART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_enabled,USART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_disabled,USART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
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bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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|
newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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|
newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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|
newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
endif
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
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bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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|
newline
|
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bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
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|
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bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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|
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|
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bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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|
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|
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bitfld.long 0x0 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
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bitfld.long 0x0 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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|
newline
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bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
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bitfld.long 0x0 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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|
bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x4 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x4 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
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bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
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bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x4 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x4 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0x8 "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0xC "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*")||cpuis("STM32C051*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_enabled,USART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_disabled,USART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_enabled,USART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_disabled,USART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
endif
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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|
newline
|
|
bitfld.long 0x0 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x0 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x0 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x4 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x4 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
sif (cpuis("STM32C011*")||cpuis("STM32C031*"))
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
bitfld.long 0x4 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x4 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x4 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0x8 "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0x8 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0xC "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32C051*"))
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C071*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C091*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32C092*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "USART_CR1,USART control register 1"
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|
bitfld.long 0x0 31. "RXFFIE,RXFIFO full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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|
newline
|
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
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bitfld.long 0x0 27. "EOBIE,End-of-block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
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|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not-full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Bbock interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "USART_CR2,USART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,Stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit address detection/4-bit address detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,NSS pin enable" "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "USART_CR3,USART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page 691,?,?,7: number of automatic retransmission attempts"
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on reception error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "USART_BRR,USART baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "USART_RTOR,USART receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "USART_RQR,USART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR,USART interrupt and status register"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "USART_RDR,USART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "USART_TDR,USART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "USART_PRESC,USART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32C071*"))
|
|
tree "USB (Universal Serial Bus Full-Speed)"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "USB_CHEP0R,USB endpoint/channel 0 register"
|
|
bitfld.long 0x0 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x0 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x0 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x0 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x0 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x0 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x0 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x0 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x4 "USB_CHEP1R,USB endpoint/channel 1 register"
|
|
bitfld.long 0x4 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x4 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x4 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x4 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x4 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x4 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x4 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x4 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x4 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x4 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x4 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x8 "USB_CHEP2R,USB endpoint/channel 2 register"
|
|
bitfld.long 0x8 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x8 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x8 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x8 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x8 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x8 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x8 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x8 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x8 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x8 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x8 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0xC "USB_CHEP3R,USB endpoint/channel 3 register"
|
|
bitfld.long 0xC 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0xC 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0xC 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0xC 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0xC 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0xC 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0xC 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0xC 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0xC 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0xC 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0xC 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x10 "USB_CHEP4R,USB endpoint/channel 4 register"
|
|
bitfld.long 0x10 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x10 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x10 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x10 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x10 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x10 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x10 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x10 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x10 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x10 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x10 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x14 "USB_CHEP5R,USB endpoint/channel 5 register"
|
|
bitfld.long 0x14 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x14 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x14 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x14 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x14 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x14 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x14 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x14 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x14 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x14 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x14 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x18 "USB_CHEP6R,USB endpoint/channel 6 register"
|
|
bitfld.long 0x18 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x18 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
bitfld.long 0x18 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x18 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x18 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x18 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x18 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
|
|
newline
|
|
rbitfld.long 0x18 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x18 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x18 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x18 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
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hexmask.long.byte 0x18 0.--3. 1. "EA,endpoint/channel address"
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line.long 0x1C "USB_CHEP7R,USB endpoint/channel 7 register"
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bitfld.long 0x1C 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
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bitfld.long 0x1C 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
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bitfld.long 0x1C 26. "ERR_RX,Received error for an IN transaction" "0,1"
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bitfld.long 0x1C 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
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bitfld.long 0x1C 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
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bitfld.long 0x1C 23. "NAK,Host mode" "0,1"
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hexmask.long.byte 0x1C 16.--22. 1. "DEVADDR,Host mode"
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bitfld.long 0x1C 15. "VTRX,USB valid transaction received" "0,1"
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bitfld.long 0x1C 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
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bitfld.long 0x1C 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
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rbitfld.long 0x1C 11. "SETUP,Setup transaction completed" "0,1"
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bitfld.long 0x1C 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
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bitfld.long 0x1C 8. "EPKIND,endpoint/channel kind" "0,1"
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bitfld.long 0x1C 7. "VTTX,Valid USB transaction transmitted" "0,1"
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bitfld.long 0x1C 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
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bitfld.long 0x1C 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
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newline
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hexmask.long.byte 0x1C 0.--3. 1. "EA,endpoint/channel address"
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group.long 0x40++0x7
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line.long 0x0 "USB_CNTR,USB control register"
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bitfld.long 0x0 31. "HOST,HOST mode" "0: USB Device function,1: USB host function"
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bitfld.long 0x0 17. "DDISCM,Device disconnection mask" "0: Device disconnection interrupt disabled,1: Device disconnection interrupt enabled"
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bitfld.long 0x0 16. "THR512M,512 byte threshold interrupt mask" "0: 512 byte threshold interrupt disabled,1: 512 byte threshold interrupt enabled"
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bitfld.long 0x0 15. "CTRM,Correct transfer interrupt mask" "0: Correct transfer (CTR) interrupt disabled.,1: CTR interrupt enabled an interrupt request is.."
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bitfld.long 0x0 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0: PMAOVR interrupt disabled.,1: PMAOVR interrupt enabled an interrupt request is.."
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bitfld.long 0x0 13. "ERRM,Error interrupt mask" "0: ERR interrupt disabled.,1: ERR interrupt enabled an interrupt request is.."
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bitfld.long 0x0 12. "WKUPM,Wake-up interrupt mask" "0: WKUP interrupt disabled.,1: WKUP interrupt enabled an interrupt request is.."
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bitfld.long 0x0 11. "SUSPM,Suspend mode interrupt mask" "0: Suspend mode request (SUSP) interrupt disabled.,1: SUSP interrupt enabled an interrupt request is.."
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bitfld.long 0x0 10. "RST_DCONM,USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask" "0: RESET interrupt disabled.,1: RESET interrupt enabled an interrupt request is.."
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bitfld.long 0x0 9. "SOFM,Start of frame interrupt mask" "0: SOF interrupt disabled.,1: SOF interrupt enabled an interrupt request is.."
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bitfld.long 0x0 8. "ESOFM,Expected start of frame interrupt mask" "0: Expected start of frame (ESOF) interrupt disabled.,1: ESOF interrupt enabled an interrupt request is.."
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bitfld.long 0x0 7. "L1REQM,LPM L1 state request interrupt mask" "0: LPM L1 state request (L1REQ) interrupt disabled.,1: L1REQ interrupt enabled an interrupt request is.."
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bitfld.long 0x0 5. "L1RES,L1 remote wake-up / resume driver" "0: No effect,1: send signal to host"
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bitfld.long 0x0 4. "L2RES,L2 remote wake-up / resume driver" "0: No effect,1: Send L2 resume signaling to device"
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bitfld.long 0x0 3. "SUSPEN,Suspend state enable" "0: No effect,1: Enter L1/L2 suspend"
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rbitfld.long 0x0 2. "SUSPRDY,Suspend state effective" "0: Normal operation,1: Suspend state"
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bitfld.long 0x0 1. "PDWN,Power down" "0: Exit power down,1: Enter power down mode"
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bitfld.long 0x0 0. "USBRST,USB Reset" "0: No effect,1: USB core is under reset"
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line.long 0x4 "USB_ISTR,USB interrupt status register"
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rbitfld.long 0x4 30. "LS_DCON,Low speed device connected" "0,1"
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rbitfld.long 0x4 29. "DCON_STAT,Device connection status" "0: No device connected,1: FS or LS device connected to the host"
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bitfld.long 0x4 17. "DDISC,Device connection" "0,1"
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bitfld.long 0x4 16. "THR512,512 byte threshold interrupt" "0,1"
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rbitfld.long 0x4 15. "CTR,Completed transfer in host mode" "0,1"
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bitfld.long 0x4 14. "PMAOVR,Packet memory area over / underrun" "0,1"
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bitfld.long 0x4 13. "ERR,Error" "0,1"
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bitfld.long 0x4 12. "WKUP,Wake-up" "0,1"
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bitfld.long 0x4 11. "SUSP,Suspend mode request" "0,1"
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bitfld.long 0x4 10. "RST_DCON,USB reset request (Device mode) or device connect/disconnect (Host mode)" "0,1"
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bitfld.long 0x4 9. "SOF,Start of frame" "0,1"
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bitfld.long 0x4 8. "ESOF,Expected start of frame" "0,1"
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bitfld.long 0x4 7. "L1REQ,LPM L1 state request" "0,1"
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rbitfld.long 0x4 4. "DIR,Direction of transaction" "0,1"
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hexmask.long.byte 0x4 0.--3. 1. "IDN,Device Endpoint / host channel identification number"
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rgroup.long 0x48++0x3
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line.long 0x0 "USB_FNR,USB frame number register"
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bitfld.long 0x0 15. "RXDP,Receive data + line status" "0,1"
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bitfld.long 0x0 14. "RXDM,Receive data - line status" "0,1"
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bitfld.long 0x0 13. "LCK,Locked" "0,1"
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bitfld.long 0x0 11.--12. "LSOF,Lost SOF" "0,1,2,3"
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newline
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hexmask.long.word 0x0 0.--10. 1. "FN,Frame number"
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group.long 0x4C++0x3
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line.long 0x0 "USB_DADDR,USB Device address"
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bitfld.long 0x0 7. "EF,Enable function" "0,1"
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hexmask.long.byte 0x0 0.--6. 1. "ADD,Device address"
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group.long 0x54++0x7
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line.long 0x0 "USB_LPMCSR,LPM control and status register"
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hexmask.long.byte 0x0 4.--7. 1. "BESL,BESL value"
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rbitfld.long 0x0 3. "REMWAKE,bRemoteWake value" "0,1"
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bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: the valid LPM token is NYET.,1: the valid LPM token is ACK."
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bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1"
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line.long 0x4 "USB_BCDR,Battery charging detector"
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bitfld.long 0x4 15. "DPPU_DPD,DP pull-up / DPDM pull-down" "0,1"
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rbitfld.long 0x4 7. "PS2DET,DM pull-up detection status" "0: Normal port detected (connected to SDP ACA CDP..,1: PS2 port or proprietary charger detected."
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newline
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rbitfld.long 0x4 6. "SDET,Secondary detection (SD) status" "0: CDP detected.,1: DCP detected."
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rbitfld.long 0x4 5. "PDET,Primary detection (PD) status" "0: no BCD support detected (connected to SDP or..,1: BCD support detected (connected to ACA CDP or.."
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newline
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bitfld.long 0x4 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
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bitfld.long 0x4 2. "PDEN,Primary detection (PD) mode enable" "0,1"
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newline
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bitfld.long 0x4 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
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tree.end
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endif
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tree "WWDG (System Window Watchdog)"
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base ad:0x40002C00
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group.long 0x0++0xB
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line.long 0x0 "WWDG_CR,WWDG control register"
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bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
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hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
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line.long 0x4 "WWDG_CFR,WWDG configuration register"
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bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK counter clock (PCLK div 4096) div 1,1: CK counter clock (PCLK div 4096) div 2,2: CK counter clock (PCLK div 4096) div 4,3: CK counter clock (PCLK div 4096) div 8,4: CK counter clock (PCLK div 4096) div 16,5: CK counter clock (PCLK div 4096) div 32,6: CK counter clock (PCLK div 4096) div 64,7: CK counter clock (PCLK div 4096) div 128"
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bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
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hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
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line.long 0x8 "WWDG_SR,WWDG status register"
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bitfld.long 0x8 0. "EWIF,Early wakeup interrupt flag" "0,1"
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tree.end
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newline
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AUTOINDENT.OFF
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